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HT46R46E/C46E/R47E/C47E /R48AE/C48AE/R49E Cost-Effective A/D Type 8-Bit MCU
Technical Document
* Tools Information * FAQs * Application Note - HA0049E Read and Write Control of the HT1380 - HA0051E Li Battery Charger Demo Board - Using the HT46R47 - HA0052E Microcontroller Application - Battery Charger - HA0083E Li Battery Charger Demo Board - Using the HT46R46 - HA0075E MCU Reset and Oscillator Circuits Application Note
Features
* Operating voltage: * Up to 0.5ms instruction cycle with 8MHz system clock
fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V
* 13 to 23 bidirectional I/O lines * External interrupt input shared with an I/O line * 8-bit programmable Timer/Event Counter with over-
at VDD=5V
* 4 or 6-level subroutine nesting * 4 channels 8 or 9-bit resolution A/D converter * 1 or 2 channel 8-bit PWM output shared with I/O lines * Bit manipulation instruction * Table read instructions * 63 powerful instructions * All instructions executed in one or two machine
flow interrupt and 7-stage prescaler
* On-chip crystal and RC oscillator * Watchdog Timer function * PFD for audio frequency generation * Power down and wake-up functions to reduce power
cycles
* Low voltage reset function * Range of packaging types
consumption
* 1288 EEPROM data memory
General Description
The Cost-Effective A/D Type MCU Devices are a series of 8-bit high performance RISC architecture microcontrollers, designed especially for applications that interface directly to analog signals, such as those from sensors. All devices include an integrated multi-channel Analog to Digital Converter in addition to one or two Pulse Width Modulation outputs. The usual Holtek MCU features such as power down and wake-up functions, oscillator options, programmable frequency divider, etc. combine to ensure user applications require a minimum of external components. The benefits of integrated A/D and PWM functions, in addition to low power consumption, high performance, I/O flexibility and low-cost, provide these devices with the versatility to suit a wide range of application possibilities such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. EEPROM memory is incorporated into each device, which is useful for applications that require an area of non-volatile memory, perhaps to store information such as calibration parameters, part numbers etc. Many features are common to all devices, however, they differ in areas such as I/O pin count, Program Memory capacity, A/D resolution, stack capacity and package types.
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HT46R46E/C46E/R47E/C47E/R48AE/C48AE/R49E
Device Types
Devices which have the letter R within their part number, indicate that they are OTP devices offering the advantages of easy and effective program updates, using the Holtek range of development and programming tools. These devices provide the designer with the means for fast and low-cost product development cycles. Devices which have the letter C within their part number indicate that they are mask version devices. These devices offer a complementary device for applications that are at a mature state in their design process and have high volume and low cost demands. Fully pin and functionally compatible with their OTP sister devices, the mask version devices provide the ideal substitute for products which have gone beyond their development cycle and are facing cost-down demands. In this datasheet, for convenience, when describing device functions, only the OTP types are mentioned by name, however the same described functions also apply to the Mask type devices.
Selection Table
Most features are common to all devices, the main feature distinguishing them are Program Memory capacity, I/O count, A/D resolution, stack capacity and package types. The following table summarises the main features of each device. Program Data Memory Memory SRAM EEPROM 648 648 888 1288 1288 1288 1288 1288
Part No. HT46R46E HT46C46E HT46R47E HT46C47E
VDD
I/O 13 13 19 23
Timer 8-bit1 8-bit1 8-bit1 8-bit1
Int. 3 3 3 3
A/D
PWM Stack Package Types 4 6 6 6 18DIP/SOP 18DIP/SOP 24SKDIP/SOP 24/28SKDIP/SOP
2.2V~5.5V 1K14 2.2V~5.5V 2K14
8-bit4 8-bit1 9-bit4 8-bit1 9-bit4 8-bit1 9-bit4 8-bit2
HT46R48AE 2.2V~5.5V 2K14 HT46C48AE HT46R49E Note: 2.2V~5.5V 4K15
Part numbers including C are mask version devices, R are OTP devices. For devices that exist in two package formats, the table reflects the situation for the larger package.
Block Diagram
S y s te m R C / X 't a l O s c illa t o r P ro g ra m C o u n te r A d d re s s D e c o d e r
T im in g G e n e ra to r
In s tr u c tio n D ecoder
In s tr u c tio n R e g is te r
P ro g ra m M e m o ry
W DT O s c illa to r D a ta M e m o ry
S ta c k S ta c k P o in te r
A d d re s s D e c o d e r M
U X
MUX M e m o ry P o in te r
ACC L o o k -u p T a b le R e g is te r L o o k -u p T a b le P o in te r T o P ro g ra m M e m o ry C o n fig u r a tio n O p tio n
ALU S h ifte r
EEPROM D a ta M e m o ry
A /D C o n v e rte r
R eset& LVR
C o n fig . R e g is te r
PW M
C o n fig . R e g is te r
T im e r / C o u n te r
PFD
C o n fig . R e g is te r
In te rru p t C ir c u it
C o n fig . R e g is te r
I/O P o rts
D e v ic e P r o g r a m m in g C ir c u itr y
Note:
This block diagram represents the OTP devices, for the Mask devices there is no Device Programming Circuitry.
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Pin Assignment
PB5 PB4 PB5 PB4 P A 3 /P F D 3 4 5 6 7 8 9 10 11 12 P A 3 /P F D 1 2 3 4 5 6 7 8 9 PA2 PA1 PA0 S C L /P B 3 /A N 3 P B 2 /A N 2 P B 1 /A N 1 P B 0 /A N 0 VSS 18 17 16 15 14 13 12 11 10 P A 4 /T M R P A 5 /IN T PA6 PA7 OSC2 OSC1 VDD RES S D A /P D 0 /P W M PA2 PA1 PA0 P B 3 /A N 3 P B 2 /A N 2 P B 1 /A N 1 P B 0 /A N 0 VSS P C 0 /S D A 2 1 24 23 22 21 20 19 18 17 16 15 14 13 PB6 PB7 P A 4 /T M R P A 5 /IN T PA6 PA7 OSC2 OSC1 VDD RES P D 0 /P W M P C 1 /S C L PB5 1 2 3 4 5 6 7 8 9 10 11 12 PB4 P A 3 /P F D PA2 PA1 PA0 P B 3 /A N 3 P B 2 /A N 2 P B 1 /A N 1 P B 0 /A N 0 VSS P C 0 /S D A 24 23 22 21 20 19 18 17 16 15 14 13 PB6 PB7 P A 4 /T M R P A 5 /IN T PA6 PA7 OSC2 OSC1 VDD RES P D 0 /P W M 0 P C 1 /S C L P A 3 /P F D PA2 PA1 PA0 P B 3 /A N 3 P B 2 /A N 2 P B 1 /A N 1 P B 0 /A N 0 VSS P C 0 /S D A P C 1 /S C L PC2 9 10 11 12 13 14 8 7 6 5 4 3 2 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PB6 PB7 P A 4 /T M R P A 5 /IN T PA6 PA7 OSC2 OSC1 VDD RES P D 1 /P W M 1 P D 0 /P W M 0 PC4 PC3
H T 4 6 R 4 6 E /H T 4 6 C 4 6 E H T 4 6 R 4 7 E /H T 4 6 C 4 7 E 1 8 D IP -A /S O P -A
H T 4 6 R 4 8 A E /H T 4 6 C 4 8 A E 2 4 S K D IP -A /S O P -A
H T46R 49E 2 4 S K D IP -A /S O P -A
HT46R49E 2 8 S K D IP -A /S O P -A
Pin Description
HT46R46E, HT46R47E Pad Name PA0~PA2 PA3/PFD PA4/TMR PA5/INT PA6~PA7 I/O Options Pull-high Wake-up PA3 or PFD Description Bidirectional 8-bit input/output port. Each individual pin on this port can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. Pins PA3, PA4 and PA5 are pin-shared with PFD, TMR and INT, respectively. Bidirectional 4-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. PB is pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function and pull-high resistor options are disabled automatically. The SCL pin of the EEPROM is internally connected to the PB3/AN3 pin.
I/O
PB0/AN0 PB1/AN1 PB2/AN2 SCL/PB3/AN3
I/O
Pull-high
SDA/PD0/PWM I/O
Bidirectional 1-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration option determines if Pull-high this pin has a pull-high resistor. The PWM output is pin-shared with pin PD0 PD0 or PWM selected via a configuration option. The SDA pin of the EEPROM is internally connected to the PD0/PWM pin. OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC Crystal or RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency. 3/4 3/4 3/4 Schmitt trigger reset input. Active low. Positive power supply Negative power supply, ground.
OSC1 OSC2 RES VDD VSS Note:
I O I 3/4 3/4
1. Each pin on PA can be programmed through a configuration option to have a wake-up function. 2. Individual pins can be selected to have a pull-high resistor.
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HT46R48AE Pin Name PA0~PA2 PA3/PFD PA4/TMR PA5/INT PA6~PA7 PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4~PB7 I/O Configuration Option Pull-high Wake-up PA3 or PFD Description Bidirectional 8-bit input/output port. Each individual pin on this port can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. Pins PA3, PA4 and PA5 are pin-shared with PFD, TMR and INT, respectively. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. PB is pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function and pull-high resistor options are disabled automatically. Bidirectional 2-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. Pins SDA and SCL of the EEPROM are internally connected to pins PC0 and PC1, respectively. Bidirectional 1-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration option determines if this pin has a pull-high resistor. The PWM output is pin-shared with pin PD0 selected via a configuration option.
I/O
I/O
Pull-high
PC0/SDA PC1/SCL
I/O
Pull-high
PD0/PWM
I/O
Pull-high I/O or PWM
OSC1 OSC2 RES VDD VSS Note:
I O I 3/4 3/4
OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC Crystal or RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency. 3/4 3/4 3/4 Schmitt Trigger reset input. Active low. Positive power supply Negative power supply, ground
1. Each pin on PA can be programmed through a configuration option to have a wake-up function. 2. Individual pins can be selected to have a pull-high resistor. 3. Pins PB4~PB7 exist but are not bonded out on the 20-pin package. 4. Unbonded pins should be setup as outputs or as inputs with pull-high resistors to conserve power.
HT46R49E Pin Name PA0~PA2 PA3/PFD PA4/TMR PA5/INT PA6~PA7 PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4~PB7 I/O Configuration Option Pull-high Wake-up PA3 or PFD Description Bidirectional 8-bit input/output port. Each individual pin on this port can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. Pins PA3, PA4 and PA5 are pin-shared with PFD, TMR and INT, respectively. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. PB is pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function and pull-high resistor options are disabled automatically. Bidirectional 5-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. Pins SDA and SCL of the EEPROM are internally connected to pins PC0 and PC1, respectively.
I/O
I/O
Pull-high
PC0/SDA PC1/SCL PC2~PC4
I/O
Pull-high
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Pin Name I/O Configuration Option Pull-high I/O or PWM Description Bidirectional 2-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration option determines if this pin has a pull-high resistor. The PWM output are pin-shared with pins PD0 and PD1 selected via a configuration option.
PD0/PWM0 PD1/PWM1
I/O
OSC1 OSC2 RES VDD VSS Note:
I O I 3/4 3/4
OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC Crystal or RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency. 3/4 3/4 3/4 Schmitt Trigger reset input. Active low. Positive power supply Negative power supply, ground
1. Each pin on PA can be programmed through a configuration option to have a wake-up function. 2. Individual pins can be selected to have a pull-high resistor. 3. Pins PC2~PC4 and pin PD1/PWM1 exist but are not bonded out on the 24-pin package. 4. Unbonded pins should be setup as outputs or as inputs with pull-high resistors to conserve power.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol Parameter Test Conditions VDD 3/4 3/4 3V 5V 3V 5V 5V 3V 5V 3V 5V 3/4 3/4 3/4 Conditions fSYS=4MHz fSYS=8MHz No load, fSYS=4MHz ADC disable No load, fSYS=4MHz ADC disable No load, fSYS=8MHz ADC disable No load, system HALT No load, system HALT 3/4 3/4 3/4 Min. 2.2 3.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 Typ. 3/4 3/4 0.6 2 0.8 2.5 4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max. 5.5 5.5 1.5 4 1.5 4 8 5 10 1 2 0.3VDD VDD 0.4VDD
Ta=25C Unit V V mA mA mA mA mA mA mA mA mA V V V
VDD
Operating Voltage
IDD1
Operating Current (Crystal OSC)
IDD2 IDD3 ISTB1
Operating Current (RC OSC) Operating Current (Crystal OSC, RC OSC) Standby Current (WDT Enabled)
ISTB2 VIL1 VIH1 VIL2
Standby Current (WDT Disabled) Input Low Voltage for I/O Ports, TMR and INT Input High Voltage for I/O Ports, TMR and INT Input Low Voltage (RES)
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Symbol VIH2 VLVR IOL Parameter Input High Voltage (RES) Low Voltage Reset I/O Port Sink Current Test Conditions VDD 3/4 3/4 3V 5V 3V 5V 3V 5V 3/4 3/4 3V 5V Conditions 3/4 3/4 VOL=0.1VDD VOL=0.1VDD VOH=0.9VDD VOH=0.9VDD 3/4 3/4 3/4 3/4 3/4 Min. 0.9VDD 2.7 4 10 -2 -5 20 10 0 3/4 3/4 3/4 Typ. 3/4 3.0 8 20 -4 -10 60 30 3/4 0.5 0.5 1.5 Max. VDD 3.3 3/4 3/4 3/4 3/4 100 50 VDD 1 1 3 Unit V V mA mA mA mA kW kW V LSB mA mA
IOH
I/O Port Source Current
RPH VAD EAD IADC
Pull-high Resistance A/D Input Voltage A/D Conversion Error Additional Power Consumption if A/D Converter is Used
EEPROM - D.C. Characteristics
Symbol VDD ICC1 ICC2 VIL VIH VOL ILI ILO ISTB1 ISTB2 CIN COUT Parameter Operating Voltage Operating Current Operating Current Input Low Voltage Input High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Standby Current Standby Current Input Capacitance (See Note) Output Capacitance (See Note) Test Conditions VDD 3/4 5V 5V 3/4 3/4 Conditions 3/4 Read at 100kHz Write at 100kHz 3/4 3/4 VIN=0 or VDD VOUT=0 or VDD VIN=0 or VDD Min. 2.2 3/4 3/4 -1 0.7VDD 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max. 5.5 2 5 0.3VDD VDD+0.5 0.4 1 1 4 3 6 8
Ta=25C
Unit V mA mA V V V mA mA mA mA pF pF
2.4V IOL=2.1mA 5V 5V 5V
2.4V VIN=0 or VDD 3/4 3/4 f=1MHz 25C f=1MHz 25C
A.C. Characteristics
Symbol fSYS fTIMER tWDTOSC tWDT1 tWDT2 Parameter System Clock Test Conditions VDD 3/4 3/4 3/4 3/4 3V 5V 3/4 3/4 Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5.5V 3/4 3/4 3/4 3/4 Min. 400 400 0 0 45 32 2 2
15 17
Ta=25C Typ. 3/4 3/4 3/4 3/4 90 65 3/4 3/4 Max. 4000 8000 4000 8000 180 130 2
16
Unit kHz kHz kHz kHz ms ms tWDTOSC tSYS
Timer I/P Frequency (TMR)
Watchdog Oscillator Period Watchdog Time-out Period (RC) Watchdog Time-out Period (System Clock)
218
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Symbol tRES tSST tLVR tINT tAD1 tAD2 tADC1 tADC2 tADCS1 tADCS2 Parameter External Reset Low Pulse Width System Start-up Timer Period Low Voltage Reset Time Interrupt Pulse Width A/D Clock Period HT46R46E A/D Clock Period HT46R47E/HT46R48AE/HT46R49E A/D Conversion Time HT46R46E A/D Conversion Time HT46R47E/HT46R48AE/HT46R49E A/D Sampling Time HT46R46E A/D Sampling Time HT46R47E/HT46R48AE/HT46R49E Test Conditions VDD 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Conditions 3/4 Wake-up from HALT 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Min. 1 3/4 0.25 1 0.5 1 3/4 3/4 3/4 3/4 Typ. 3/4 1024 1 3/4 3/4 3/4 64 76 32 32 Max. 3/4 3/4 2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Unit ms *tSYS ms ms ms ms tAD1 tAD2 tAD1 tAD2
Note: *tSYS=1/fSYS
EEPROM - A.C. Characteristics
Symbol fSK tHIGH tLOW tr tf tHD:STA Parameter Clock Frequency Clock High Time Clock Low Time SDA and SCL Rise Time SDA and SCL Fall Time START Condition Hold Time Note Note After this period the first clock pulse is generated Only relevant for repeated START condition 3/4 3/4 3/4 3/4 Remark 3/4 3/4 3/4 Standard Mode* Min. 3/4 4000 4700 3/4 3/4 4000 Max. 100 3/4 3/4 1000 300 3/4 VCC=5V10% Min. 3/4 600 1200 3/4 3/4 600 Max. 400 3/4 3/4 300 300 3/4
Ta=25C
Unit kHz ns ns ns ns ns
tSU:STA tHD:DAT tSU:DAT tSU:STO tAA tBUF tSP tWR Note:
START Condition Setup Time Data Input Hold Time Data Input Setup Time STOP Condition Setup Time Output Valid from Clock Bus Free Time Input Filter Time Constant (SDA and SCL Pins) Write Cycle Time
4000 0 200 4000 3/4
3/4 3/4 3/4 3/4 3500 3/4 100 5
600 0 100 600 3/4 1200 3/4 3/4
3/4 3/4 3/4 3/4 900 3/4 50 5
ns ns ns ns ns ns
Time in which the bus must be free before a new 4700 transmission can start Noise suppression time 3/4 3/4 3/4
ns ms
These parameters are periodically sampled but not 100% tested * The standard mode means VCC=2.2V to 5.5V
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System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes these devices suitable for low-cost, high-volume production for controller applications requiring from 1K up to 4K words of Program Memory and 64 to 128 bytes of Data Memory storage. Clocking and Pipelining The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. When the RC oscillator is used, OSC2 is freed for use as a T1 phase clock synchronizing pin. This T1 phase clock has a frequency of fSYS/4 with a 1:3 high/low duty cycle. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications
O s c illa to r C lo c k ( S y s te m C lo c k ) P h a s e C lo c k T 1 P h a s e C lo c k T 2 P h a s e C lo c k T 3 P h a s e C lo c k T 4 P ro g ra m C o u n te r PC PC+1 PC+2
P ip e lin in g
F e tc h In s t. (P C ) E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 ) E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 ) E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1 2 3 4 5 6 D ELAY: : :
M O V A ,[1 2 H ] C ALL D ELAY C P L [1 2 H ]
F e tc h In s t. 1
E x e c u te In s t. 1 F e tc h In s t. 2 E x e c u te In s t. 2 F e tc h In s t. 3 F lu s h P ip e lin e F e tc h In s t. 6 E x e c u te In s t. 6 F e tc h In s t. 7
NOP
Instruction Fetching
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Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as JMP or CALL that demand a jump to a non-consecutive Program Memory address. For the Cost-Effective A/D Type series of microcontrollers, note that the Program Counter width varies with the Program Memory capacity depending upon which device is selected. However, it must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section.
Program Counter Bits Mode b11 Initial Reset External Interrupt Timer/Event Counter Overflow A/D Converter Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine PC11 PC10 #11 S11 #10 S10 PC9 #9 S9 PC8 #8 S8 0 0 0 0 b10 0 0 0 0 b9 0 0 0 0 b8 0 0 0 0 b7 0 0 0 0 b6 0 0 0 0 b5 0 0 0 0 b4 0 0 0 0 b3 0 0 1 1 b2 0 1 0 1 b1 0 0 0 0 b0 0 0 0 0
Program Counter + 2 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program Counter Note: PC11~PC8: Current Program Counter bits @7~@0: PCL bits #11~#0: Instruction code address bits S11~S0: Stack register bits For the HT46R49E, the Program Counter is 12 bits wide, i.e. from b11~b0. For the HT46R47E and HT46R48AE, the Program Counter is 11 bits wide, i.e. From b10~b0, therefore the b11 column in the table is not applicable. For the HT46R46E, the Program Counter is 10 bits wide, i.e. from b9~b0, therefore the b11 and b10 the columns in the table are not applicable.
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Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack can have either 4 or 6 levels depending upon which device is selected and is neither part of the data nor part of the program space, and is neither readable nor writable. The activated level is indexed by the Stack Pointer, SP, and is neither readable nor writable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack.
P ro g ra m C o u n te r
* Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
* Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
* Increment and Decrement INCA, INC, DECA, DEC * Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
SIZA, SDZA, CALL, RET, RETI
Program Memory
The Program Memory is the location where the user code or program is stored. For microcontrollers, two types of Program Memory are usually supplied. The first type is the One-Time Programmable, OTP, memory where users can program their application code into the device. Devices with OTP memory are denoted by having an R within their device name. By using the appropriate programming tools, OTP devices offer users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. OTP devices are also applicable for use in applications that require low or medium volume production runs. The other type of memory is the mask ROM memory, denoted by having a C within the device name. These devices offer the most cost effective solutions for high volume products. Structure The Program Memory has a capacity of 1K by 14, 2K by 14 or 4K by 15 bits depending upon which device is selected. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by separate table pointer registers. Special Vectors Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
* Location 000H
T o p o f S ta c k S ta c k P o in te r
S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k L e v e l 3 P ro g ra m M e m o ry
B o tto m
o f S ta c k
S ta c k L e v e l N
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. Note: For the HT46R46E, 4 levels of stack are available and for the HT46R47E, HT46R48AE and HT46R49E, 6 levels of stack are available.
Arithmetic and Logic Unit - ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions:
* Arithmetic operations: ADD, ADDM, ADC, ADCM,
This vector is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution.
* Location 004H
This vector is used by the external interrupt. If the external interrupt pin on the device goes low, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full.
* Location 008H
SUB, SUBM, SBC, SBCM, DAA
This internal vector is used by the Timer/Event Counter. If a counter overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full.
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H T46R 46E 000H 004H 008H 00C H 010H 014H 300H 3FFH 400H 7FFH 800H FFFH 1 4 b its 1 4 b its 1 5 b its N o t Im p le m e n te d In itia lis a tio n V e c to r E x te rn a l In te rru p t V e c to r T im e r /E v e n t C o u n te r In te rru p t V e c to r H T46R 47E H T46R 48A E In itia lis a tio n V e c to r E x te rn a l In te rru p t V e c to r T im e r /E v e n t C o u n te r In te rru p t V e c to r H T46R 49E In itia lis a tio n V e c to r E x te rn a l In te rru p t V e c to r T im e r /E v e n t C o u n te r In te rru p t V e c to r
A /D C o n v e rte r In te rru p t V e c to r
A /D C o n v e rte r In te rru p t V e c to r
A /D C o n v e rte r In te rru p t V e c to r
Program Memory Structure
* Location 00CH
This internal vector is used by the A/D converter. When an A/D conversion cycle is complete, the program will jump to this location and begin execution if the A/D interrupt is enabled and the stack is not full. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the lower order address of the look up data to be retrieved in the table pointer register, TBLP. This register defines the lower 8-bit address of the look-up table. After setting up the table pointer, the table data can be retrieved from the current Program Memory page or last Program Memory page using the TABRDC[m] or TABRDL [m] instructions, respectively. When these instructions are executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as 0.
The following diagram illustrates the addressing/data flow of the look-up table:
P ro g ra m C o u n te r H ig h B y te TBLP P ro g ra m M e m o ry
TBLH T a b le C o n te n ts H ig h B y te
S p e c ifie d b y [m ] T a b le C o n te n ts L o w B y te
Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the HT46R47E microcontroller. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is 700H which refers to the start address of the last page within the 2K Program Memory of the HT46R47E microcontroller. The table pointer is setup here to have an initial value of 06H. This will ensure that the first data read from the data table will be at the Program Memory address 706H or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the TABRDC [m] instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the TABRDL [m] instruction is executed.
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tempreg1 tempreg2 db db : : a,06h tblp,a : : tempreg1 ? ? ; temporary register #1 ; temporary register #2
mov mov
; initialise table pointer - note that this address ; is referenced ; to the last page or present page
tabrdl
; ; ; ;
transfers value in table referenced by table pointer to tempregl data at prog. memory address 706H transferred to tempreg1 and TBLH
dec tabrdl
tblp tempreg2
; reduce value of table pointer by one ; ; ; ; ; ; ; ; transfers value in table referenced by table pointer to tempreg2 data at prog.memory address 705H transferred to tempreg2 and TBLH in this example the data 1AH is transferred to tempreg1 and data 0FH to register tempreg2 the value 00H will be transferred to the high byte register TBLH
: : org dc 700h ; sets initial address of last page (for HT46R47E)
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : :
Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation.
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control.
Table Location Bits Instruction b11 TABRDC [m] TABRDL [m] PC11 1 b10 PC10 1 b9 PC9 1 b8 PC8 1 b7 @7 @7 b6 @6 @6 b5 @5 @5 b4 @4 @4 b3 @3 @3 b2 @2 @2 b1 @1 @1 b0 @0 @0
Table Location Note: PC11~PC8: Current Program Counter bits @7~@0: Table Pointer TBLP bits For the HT46R49E the Table address location is 12 bits, i.e. from b11~b0. For the HT46R47E and HT46R48AE, the Table address location is 11 bits, i.e. from b10~b0. For the HT46R46E, the Table address location is 10 bits, i.e. from b9~b0.
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00H S p e c ia l P u r p o s e D a ta M e m o ry 3FH 40H G e n e ra l P u rp o s e D a ta M e m o ry 7FH HT46R46E and HT46R47E 7FH HT46R48AE BFH HT46R49E 00H S p e c ia l P u r p o s e D a ta M e m o ry 27H 28H G e n e ra l P u rp o s e D a ta M e m o ry G e n e ra l P u rp o s e D a ta M e m o ry 00H S p e c ia l P u r p o s e D a ta M e m o ry 3FH 40H
Data Memory Structure Note: Most of the Data Memory bits can be directly manipulated using the SET [m].i and CLR [m].i with the exception of a few dedicated bits. The Data Memory can also be accessed through the memory pointer register MP.
Structure The two sections of Data Memory, the Special Purpose and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are 8 bits wide but the length of each memory section is dictated by the type of microcontroller chosen. The start address of the Data Memory for all devices is the address 00H. Registers which are common to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both read and write operations. By using the SET [m].i and CLR [m].i instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value 00H.
of internal functions such as timers, interrupts, etc., as well as external functions such as I/O data control and A/D converter operation. The location of these registers within the Data Memory begins at the address 00H. Any unused Data Memory locations between these special function registers and the point where the General Purpose Memory begins is reserved for future expansion purposes, attempting to read data from these locations will return a value of 00H. Indirect Addressing Register - IAR The IAR register, located at Data Memory address 00H, is not physically implemented. This special register allows what is known as indirect addressing, which permits data manipulation using Memory Pointers instead of the usual direct memory addressing method where the actual memory address is defined. Any actions on the IAR register will result in corresponding read/write operations to the memory location specified by the Memory Pointer MP. Reading the IAR register indirectly will return a result of 00H and writing to the register indirectly will result in no operation. Memory Pointer - MP One Memory Pointer, known as MP, is physically implemented in Data Memory. The Memory Pointer can be written to and manipulated in the same way as normal registers providing an easy way of addressing and tracking data. When using any operation on the indirect addressing register IAR, it is actually the address specified by the Memory Pointer that the microcontroller will be directed to. For devices with 64 or 88 bytes of RAM Data Memory, bit 7 of the Memory Pointer is not implemented. However, it must be noted that when the Memory Pointer for these devices is read, bit 7 will be read as high.
Special Function Registers
To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation
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00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H HT46R46E IA R MP HT46R47E IA R MP HT46R48AE IA R MP HT46R49E IA R MP
AC PC TB TB
C L
LP LH
AC PC TB TB
C L
LP LH
AC PC TB TB
C L
LP LH
AC PC TB TB
L LP LH
C
STATUS IN T C TM R TM RC
STATUS IN T C TM R TM RC
STATUS IN T C TM R TM RC
STATUS IN T C TM R TM RC
P PA P PB B
A C C
P PA P PB B
A C C
PD PDC PW M
PD PDC PW M
PA PAC PB PBC PC PCC PD PDC PW M
PA PAC PB PBC PC PCC PD PDC PW M0 PW M1
ADR ADCR ACSR
AD AD AD AC
RL RH CR SR
AD AD AD AC
RL RH CR SR
AD AD AD AC
RL RH CR SR
: U n u s e d , re a d a s "0 0 "
Special Purpose Data Memory
The following example shows how to clear a section of four RAM locations already defined as locations adres1 to adres4. data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov mov mov mov loop: clr inc sdz jmp continue: The important point to note here is that in the example shown above, no reference is made to specific RAM addresses. IAR mp block loop ; clear the data at address defined by MP ; increment memory pointer ; check if last memory location has been cleared a,04h ; setup size of block block,a a,offset adres1 ; Accumulator loaded with first RAM address mp,a ; setup memory pointer with first RAM address
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Accumulator - ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register - PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers - TBLP, TBLH These two special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates the location where the table data is located. Its value must be setup before any table read commands are executed. Its value can be changed, for example using the INC or DEC instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location.
b7 TO PDF OV Z AC
Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the CLR WDT or HALT instruction. The PDF flag is affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations.
* C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
* AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.
* Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
* OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
* PDF is cleared by a system power-up or executing the
CLR WDT instruction. PDF is set by executing the HALT instruction.
* TO is cleared by a system power-up or executing the
CLR WDT or HALT instruction. TO is set by a WDT time-out.
b0 C
S T A T U S R e g is te r
Ar Ca Au Ze Ov ith m e r r y fla x ilia r y r o fla g e r flo w g tic /L o g ic O p e r a tio n F la g s c a r r y fla g fla g an n tim e a g e m e n t F la g s fla g e - o u t fla g n te d , re a d a s "0 "
S y s te m M Pow erdow W a tc h d o g N o t im p le m
Status Register
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In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Interrupt Control Register - INTC This 8-bit register, known as the INTC register, controls the operation of both external and internal timer interrupts. By setting various bits within this register using standard bit manipulation instructions, the enable/disable function of each interrupt can be independently controlled. A master interrupt bit within this register, the EMI bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt routine is entered to disable further interrupt and is set by executing the RETI instruction. Timer/Event Counter Registers - TMR, TMRC All devices possess a single internal 8-bit count-up timer. An associated register known as TMR is the location where the timers 8-bit value is located. This register can also be preloaded with fixed data to allow different time intervals to be setup. An associated control register, known as TMRC, contains the setup information for this timer, which determines in what mode the timer is to be used as well as containing the timer on/off control function. Input/Output Ports and Control Registers Within the area of Special Function Registers, the I/O registers and their associated control registers play a prominent role. All I/O ports have a designated register correspondingly labeled as PA, PB, PC and PD. These labeled I/O registers are mapped to specific addresses within the Data Memory as shown in the Data Memory table, which are used to transfer the appropriate output or input data on that port. With each I/O port there is an associated control register labeled PAC, PBC, PCC and PDC, also mapped to specific addresses with the Data Memory. The control register specifies which pins of that port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. During program initialization, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits using the SET [m].i and CLR [m].i instructions. The ability to change I/O pins from output to input and vice versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices. Pulse Width Modulator Registers PWM, PWM0, PWM1 Each device contains either one or two Pulse Width Modulators. Each one has its own related independent control register. For devices with a single PWM function this is register is known as PWM, while for devices with two PWM functions, their control register names are PWM0 and PWM1. The 8-bit contents of these registers, defines the duty cycle value for the modulation cycle of the corresponding Pulse Width Modulator. A/D Converter Registers ADR, ADRL, ADRH, ADCR, ACSR Each device contains a 4-channel 8-bit or 9-bit A/D converter. The correct operation of the A/D requires the use of one or two data registers, a control register and a clock source register. For the HT46R46E device, which has an 8-bit A/D converter, there is a single data register, known as ADR. For the other devices, which contain a 9-bit A/D converter, there are two data registers, a high byte data register known as ADRH, and a low byte data register known as ADRL. These are the register locations where the digital value is placed after the completion of an analog to digital conversion cycle. The channel selection and configuration of the A/D converter is setup via the control register ADCR while the A/D clock frequency is defined by the clock source register, ACSR.
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EEPROM Data Memory
All devices contain an internal 1K capacity EEPROM memory with a 1288 bit structure. An EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. Accessing the EEPROM Data Memory The internal EEPROM Data Memory has an I2C structure and as such is accessed via a 2-line serial interface for data transfer. These two lines are the Serial Data line on pin SDA, and the Serial Clock line on pin SCL. The Function HT46R46E/HT46R47E EEPROM Pin I/O Pin Capacity SDA PD0 SCL PB3 1288 bits EEPROM I/O Shared Pins HT46R48AE/HT46R49E SDA PC0 SCL PC1 SDA line is bi-directional and is the line where the data is written to and read from the EEPROM. The SCL line is an input line and is the clock signal for both the reading and writing of data. These two EEPROM pins are shared with I/O pins as shown in the table. Any pull-high resistors configuration options for these pin shared pins also remain valid for the EEPROM. Care must be taken if these pins are used as normal I/O pins, as any signals on the pins may be seen by the EEPROM as a valid read or write operation command. If this happens the EEPROM may inadvertently generate signals on its SDA line which could create unexpected programming errors. The Internal EEPROM can be directly controlled using the pin-shared I/O pins or it can be directly connected to an external I2C bus and controlled by some other external master device. In this latter case care should be taken to ensure that the pin-shared I/Os for the SDA and SCL lines are both setup as inputs. Device
* SCL Pin
D a ta m u s t n o t c h a n g e w h e n S C L is h ig h SDA SCL D a ta o n ly a llo w e d to c h a n g e w h e n S C L is lo w
This is the clock input pin to the EEPROM. Writing data into the EEPROM is implemented on the low to high edge of this pin. Reading data out of the EEPROM is implemented on the high to low edge. Any data on the SDA line that is to be sent to the EEPROM on the next rising clock edge is only allowed to change state when the SCL line is low. If the SCL line is high and the data on the SDA line changes, this will be interpreted as a START or STOP condition.
* SDA Pin
Clock/Data Relationship The sequence of events to read or write data to the EEPROM follows the same pattern. All operations must begin with a START condition and end with a STOP condition. Inserted between the START and STOP conditions are the device address, a read/write bit and address and data information. All control information, addresses and data is sent in 8-bit format to the EEPROM, if successfully received the EEPROM will respond with an acknowledge signal allowing the next 8-bits to be received or transmitted.
This is the EEPROM data pin. As the pin is used for both reading and writing of data it is bi-directional. As the pin has an open-drain output, it can be wire-OR c o n n e ct e d t o o t h e r ex t e r nal o p e n - d r a i n o r open-collector outputs. Otherwise it must be connected to a pull-high resistor for correct operation, which can be implemented using the pull-high configuration option for the corresponding shared I/O pin.
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M u s t a lw a y s b e s e t fo r a n y r e a d o r w r ite S ta rt 1 0 1 0 0 0 0 R /W In fo r m a tio n d e p e n d s o n ty p e o f r e a d o r w r ite ACK A d d re s s /D a ta A c k n o w le d g e s ig n a l fr o m EEPROM SDA 8 9 SCL S to p C o n d itio n S to p
D e v ic e a d d r e s s fix e d d a ta SDA SCL S ta r t C o n d itio n SDA SCL
R e a d = "1 " W r ite = " 0 "
A c k n o w le SDA EE 9
dge p u lle d lo w b y P R O M d u r in g th c lo c k p u ls e
Data Transfer Protocol
* START Condition
A start condition must be transmitted to the EEPROM prior to transmitting the device address and before any other address or data information is transmitted. A start condition is implemented by a high to low transition on the SDA line with the SCL line high.
* Device Address
This must always immediately follow the transmitted START condition and is implemented by clocking into the EEPROM a 1010000 7-bit sequence. Clocking the device address into the EEPROM is implemented on the low to high edge of the SCL line. The data on the SDA line must therefore be stable before the SCL line changes from low to high. Any changes on the SDA line when the SCL line is high could be interpreted as a START or STOP condition.
* R/W Bit
pin. Therefore after the 7-bit device address and the R/W bit, which constitutes a total of 8-bits, has been transmitted to the EEPROM, on the next clock cycle the EEPROM will respond with an acknowledge signal. After this, the 8-bit data address information can then be sent to the EEPROM, after which again the EEPROM will respond with an acknowledge, on the ninth clock pulse. Data information can then be transmitted or received in a similar way.
* Data Address
This follows the device address sequence and informs the EEPROM if a read or write operation is to be implemented. For a read operation, this bit should be high, for a write operation the bit should be low.
* Acknowledge
Although the EEPROM internal data structure is 1288 bits and as such requires a 7-bit address to access the data, however an 8-bit address must be transmitted to the EEPROM. The address is transmitted in an MSB bit first format. As the 8th bit, which will be the MSB and the first bit to be transmitted is redundant, its value can be either zero or one. Note that the address is clocked into the EEPROM on the low to high edge of the SCL clock line.
* STOP Condition
After the EEPROM has successfully received any 8-bits of information, it will transmit an acknowledge signal by pulling the SDA line low. A clock pulse for this EEPROM generated acknowledge signal, which will be the ninth clock pulse, must be supplied on the SCL
A stop condition must be transmitted to the EEPROM at the end of any read or write operation to terminate the operation. The successful reception of a stop condition by the EEPROM will cause it to enter its Power Down Mode and await the next start bit. A stop condition is implemented by a low to high transition on the SDA line with the SCL line high.
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Read Operations There are three kinds of read operation. These are current address read, random read and sequential read.
* Current Address Read
Inside the EEPROM is an internal counter which will point to the present EEPROM address. This internal counter will increment by one each time a read or write operation is executed. The value of the counter will be stored as long as the EEPROM is powered up, only when power is removed will the counter lose its value. If it is required to read the data at the address that this internal counter is pointing to, then it is not necessary to send any address information to the EEPROM. Therefore for a current address read operation to be executed, after the device address and read/write bit information has been sent, if the read/write bit is set high, then after the EEPROM sends its acknowledge signal by pulling SDA low on the ninth clock pulse, it will transmit its internal 8-bits of data at this address on the following eight clock pulses. After the 8-bits of data have been received, no acknowledge is sent but a STOP condition should be transmitted by the receiving device to end the read execution.
* Random Read
low. After the 8-bit address has been transmitted, in an MSB first format, the EEPROM will respond with another acknowledge signal. At this point, the internal counter is now pointing to the requested address. Now the data can be read out by sending another start, device address and read/write bit information, but this time with the read/write bit set high to indicate a read operation. After the EEPROM acknowledges this in the usual way, the 8-bits of data at the requested address can be read out. As this read operation is the same as the current address read operation, no acknowledge signal will be generated but a stop condition must be sent to the EEPROM to end the read execution.
* Sequential Read
A random read operation allows data at any address within the EEPROM to be read out. For this to happen, a start condition, device address and read/write bit must first be transmitted. Then after the usual acknowledge signal is received from the EEPROM, the required EEPROM internal address information must be transmitted. In this case, as an address is being written to the EEPROM, the read/write bit should be
D e v ic e a d d r e s s SDA 1 S ta rt 0 1 0 0 0 0 R
A sequential read allows more than one byte of data to be read out of the EEPROM sequentially. It utilises the EEPROM internal counter, which points to the EEPROM internal address, and which will increment by one automatically after each byte of data has been read out. A sequential read operation is started by first executing a random read or current read to setup the start address of the data to be read out. After the first byte of data has been read out of the EEPROM using the current read or random read, instead of sending a STOP condition, an acknowledge is sent instead. This is achieved by the receiving device pulling the SDA line low on the clock pulse after the eighth data bit. When the EEPROM receives this acknowledge it will automatically increment its internal counter allowing the next byte of data to be read out. Note that when the address counter reaches its maximum value its next value will automatically roll over to zero.
D a ta fro m EEPROM S to p
R /W h ig h -- R e a d
A c k n o w le d g e fro m E E P R O M S D A p u lle d lo w
N o a c k n o w le d g e S D A flo a ts h ig h
Current Address Read
D e v ic e a d d r e s s SDA S ta rt 1 01 0 0 0 0W 1 A c k n o w le d g e fro m E E P R O M S D A p u lle d lo w S ta rt W o rd a d d re s s D e v ic e a d d r e s s 01 0 0 0 0R N o a c k n o w le d g e S D A flo a ts h ig h D a ta S to p
R /W lo w - - W r ite
R /W h ig h -- R e a d
Random Read
C u rre n t a d d re s s re a d o r r a n d o m r e a d o p e r a tio n SDA 0 R /W h ig h -- R e a d 0R A c k n o w le d g e fr o m r e c e iv in g d e v ic e S D A p u lle d lo w N o a c k n o w le d g e S D A flo a ts h ig h
D a ta n
D a ta n + 1
D a ta n + x
S to p
Sequential Read
Rev. 1.20
19
August 15, 2007
HT46R46E/C46E/R47E/C47E/R48AE/C48AE/R49E
Write Operations There is only one write operation which is a byte write.
* Byte Write * Internal Write Cycle
A byte write operation allows a single byte of data to be written into the EEPROM. For this to happen, a start condition, device address and read/write bit must first be transmitted. Then after the usual acknowledge signal is received from the EEPROM, the required EEPROM internal address information where the data is to be written must be transmitted. In this case, as an address is being written to the EEPROM, the read/write bit should be low. After the 8-bit address has been transmitted in an MSB format, the EEPROM will respond with another acknowledge signal. At this point the internal counter is now pointing to the requested address. Now the 8-bits of data to be written, in an MSB format, can be transmitted to the EEPROM. When the last bit has been received the EEPROM will respond with the usual acknowledge signal, after which a STOP condition should be transmitted to the EEPROM. After the EEPROM receives the STOP condition it will enter its internal write cycle. The internal write cycle is fully controlled and timed by the EEPROM and when running, no other EEPROM operations can be executed.
D e v ic e a d d r e s s SDA 1 0 S ta rt 1 0 0 0 0 W
After a write operation is executed and when the EEPROM receives the final STOP condition at the end of the write operation, it will enter its internally controlled and timed internal write cycle. When the internal write cycle is executing, no other operations can be carried out on the EEPROM. Before executing further operations on the EEPROM, therefore, a time delay must be provided, whose value should be equal to the maximum write cycle time, tWR, as specified in the EEPROM A.C. Characteristics table. However as only a maximum time is provided, a better method, using polling to determine when the write cycle has finished, can be used. To do this a START condition, followed by a device address and read/write bit low, is transmitted to the EEPROM. If the write cycle has completed the EEPROM will respond with an acknowledge signal, which means the SDA line will be pulled low. If the write cycle has not completed then no acknowledge signal will be generated and the SDA line will remain high.
W o rd a d d re s s
D a ta
S to p
R /W lo w - - W r ite
A c k n o w le d g e fr o m
EEPROM
- - S D A p u lle d lo w
Byte Write
S e n d W r ite C o m m a n d S e n d S to p C o n d itio n to In itia te In te r n a l W r ite C y c le S e n d S ta rt S e n d D e v ic e A d d r e s s R /W = 0
In te r n a l w r ite c y c le s till r u n n in g No
A c k n o w le d g e R e c e iv e d SDA=0 Yes
N e x t O p e r a tio n
Internal Write Cycle Busy Polling
Rev. 1.20
20
August 15, 2007
HT46R46E/C46E/R47E/C47E/R48AE/C48AE/R49E
EEPROM Timing Diagram The Timing Diagram shows in more detail the timing relationship between SCL and SDA. The specific timing values are provided in the EEPROM A.C. Characteristf SCL tS
U
tics table. These timings must be carefully managed by the programmer during application program development, especially if the device is used at higher clock speeds.
tr tL
OW D
tH
IG H
:S
TA
tH tS
P
:S
TA
tH
D
:D
AT
tS
U
:D
AT
tS
U
:S
TO
SDA SDA OUT
tA
A
tB V a lid V a lid
UF
Timing Diagram
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all ports and wake-up options on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. Depending upon which device or package is chosen, the microcontroller range provides from 13 to 23 bidirectional input/output lines labeled with port names PA, PB, PC and PD. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction MOV A,[m], where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selectable via configuration options and are implemented using a weak PMOS transistor. Port A Wake-up Each device has a HALT instruction enabling the microcontroller to enter a Power Down Mode and preserve power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. After a HALT instruction forces the microcontroller into entering a HALT condition, the processor will remain idle or in a low-power state until the logic condition of the selected wake-up pin on Port A changes from high to low. This function is especially suitable for applications that can be woken up via external switches. Note that each pin on Port A can be selected individually to have this wake-up feature. I/O Port Control Registers Each I/O port has its own control register PAC, PBC, PCC and PDC, to control the input/output configuration. With this control register, each CMOS output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a 1. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a 0, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application program control.
Rev. 1.20
21
August 15, 2007
HT46R46E/C46E/R47E/C47E/R48AE/C48AE/R49E
* External Interrupt Input * A/D Inputs
The external interrupt pin INT is pin-shared with the I/O pin PA5. For applications not requiring an external interrupt input, the pin-shared external interrupt pin can be used as a normal I/O pin, however to do this, the external interrupt enable bits in the INTC register must be disabled.
* External Timer Clock Input
The external timer pin TMR is pin-shared with the I/O pin PA4. To configure it to operate as a timer input, the corresponding control bits in the timer control register must be correctly set. For applications that do not require an external timer input, the pin can be used as a normal I/O pin. Note that if used as a normal I/O pin the timer mode control bits in the timer control register must select the timer mode, which has an internal clock source, to prevent the input pin from interfering with the timer operation.
* PFD Output
Each device has four A/D converter inputs. All of these analog inputs are pin-shared with I/O pins on Port B. If these pins are to be used as A/D inputs and not as normal I/O pins then the corresponding bits in the A/D Converter Control Register, ADCR, must be properly set. There are no configuration options associated with the A/D function. If used as I/O pins, then full pull-high resistor configuration options remain, however if used as A/D inputs then any pull-high resistor options associated with these pins will be automatically disconnected.
* SCL/SDA EEPROM Pins
Each device contains a PFD function whose single output is pin-shared with PA3. The output function of this pin is chosen via a configuration option and remains fixed after the device is programmed. Note that the corresponding bit of the port control register, PAC.3, must setup the pin as an output to enable the PFD output. If the PAC port control register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high option, even if the PFD configuration option has been selected.
* PWM Outputs
The internal EEPROM has two active pins, a clock pin, SCL, and a data pin, SDA. The SDA pin is shared with pin PD0 on the HT46R46E and HT46R47E devices and with pin PC0 on the other devices. The SCL pin is shared with pin PB3 on the HT46R46E and HT46R47E devices and with pin PC1 on the other devices. Data can be transmitted to and from the EEPROM using their corresponding I/O shared pins. The EEPROM pins, SCL and SDA, can also be connected to an external I2C bus, allowing it to be controlled by an external I2C master device. In this case the I/O pins must be setup as inputs. Care must also be taken if these pins are used as normal I/O pins as the internal EEPROM may interpret regular I/O pin data as EEPROM read or write commands, which could result in unexpected programming errors. Note that there is no configuration option associated with these shared pins. I/O Pin Structures The following diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins.
All devices contain one or two PWM outputs pin shared with pins PD0 and PD1. The PWM output functions are chosen via configuration options and remain fixed after the device is programmed. Note that the corresponding bit or bits of the port control register, PDC, must setup the pin as an output to enable the PWM output. If the PDC port control register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high option, even if the PWM configuration option has been selected.
C o n tr o l B it Q D CK S Q
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
P u ll- H ig h O p tio n
V
DD
W eak P u ll- u p
I/O D a ta B it Q D CK S Q
M
P in
W r ite D a ta R e g is te r
R e a d D a ta R e g is te r S y s te m W a k e -u p
U X
W a k e - u p O p tio n
P A o n ly
Non-pin-shared Function Input/Output Ports
Rev. 1.20
22
August 15, 2007
HT46R46E/C46E/R47E/C47E/R48AE/C48AE/R49E
C o n tr o l B it Q D CK S Q P u ll- H ig h O p tio n V
DD
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
W eak P u ll- u p
D a ta B it Q D CK S Q
M
P A 4 /T M R P A 5 /IN T
W r ite D a ta R e g is te r
Read IN TM Sy
D a ta T fo r R fo r s te m
Re PA PA Wa
g is te r 5 o n ly 4 o n ly k e -u p
U X
W a k e - u p O p tio n
PA4/PA5 Input/Output Ports
V C o n tr o l B it Q D CK S Q P u ll- H ig h O p tio n
DD
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
W eak P u ll- u p
D a ta B it Q D W r ite D a ta R e g is te r CK S Q
M U X
P A 3 /P F D P D 0 /P W M /S D A P D 0 /P W M 0 P D 1 /P W M 1 ( H T 4 6 R 4 9 E 2 8 - p in p a c k a g e o n ly )
PFD
orPW M
W a v e fo rm
M U X
P F D /P W M
O p tio n
R e a d D a ta R e g is te r EEPROM
SDA
PA3/PFD and PD/PWM Input/Output Ports
Rev. 1.20
23
August 15, 2007
HT46R46E/C46E/R47E/C47E/R48AE/C48AE/R49E
V C o n tr o l B it Q D CK S Q P u ll- H ig h O p tio n
DD
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
W eak P u ll- u p
P B 0 /A N 0 ~ P B 3 /A N 3 D a ta B it Q D CK S Q
M U X
P B 3 /A N 3 /S C L (H T 4 6 R 4 6 E , H T 4 6 R 4 7 E o n ly )
W r ite D a ta R e g is te r
R e a d D a ta R e g is te r PCR2 PCR1 PCR0 T o A /D C o n v e rte r
A n a lo g In p u t S e le c to r
AC S2~ACS0 EEPROM SCL
PB Input/Output Ports
V C o n tr o l B it Q D CK S Q P u ll- H ig h O p tio n
DD
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
W eak P u ll- u p
P C 0 /S D A P C 1 /S C L D a ta B it Q D CK S Q
M U X
W r ite D a ta R e g is te r
R e a d D a ta R e g is te r EEPROM EEPROM
SDA SCL
PC0/SDA and PC1/SCL Input/Output Ports - HT46R48AE, HT46R49E Only
Rev. 1.20
24
August 15, 2007
HT46R46E/C46E/R47E/C47E/R48AE/C48AE/R49E
Programming Considerations Within the user program, one of the first things to consider is port initialization. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. If the port control registers, PAC, PBC, PCC and PDC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA, PB, PC and PD, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the SET [m].i and CLR [m].i instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.
T1 S y s te m C lo c k T2 T3 T4 T1 T2 T3 T4
Timer/Event Counters
The provision of timers form an important part of any microcontroller giving the designer a means of carrying out time related functions. Each device contains an internal 8-bit count-up timer. With three operating modes, the timers can be configured to operate as a general timer, external event counter or as a pulse width measurement device. The provision of an internal 8-stage prescaler to the timer clock circuitry gives added range to the timer. There are two registers related to the Timer/Event Counter, TMR and TMRC. The TMR register is the register that contains the actual timing value. Writing to TMR places an initial starting value in the Timer/Event Counter preload register while reading TMR retrieves the contents of the Timer/Event Counter. The TMRC register is a Timer/Event Counter control register, which defines the timer options, and determines how the timer is to be used. The timer clock source can be configured to come from the internal system clock source or from an external clock on shared pin PA4/TMR. Configuring the Timer/Event Counter Input Clock Source
P o rt D a ta
W r ite to P o r t
R e a d fro m
P o rt
Read/Write Timing Port A has the additional capability of providing wake-up functions. When the device is in the Power Down Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Note that some devices have different package types which may result in some I/O pins not being bonded out. If these pins are setup as inputs they may oscillate and increase power consumption, especially notable if the device is in the Power Down Mode. It is therefore recommended that any unbonded pins should be setup as outputs, or if setup as inputs, then they should be connected to pull-high resistors.
The internal timers clock source can originate from either the system clock or from an external clock source. The system clock input timer source is used when the timer is in the timer mode or in the pulse width measurement mode. The internal timer clock also passes through a prescaler, the value of which is conditioned by the bits PSC0, PSC1 and PSC2. An external clock source is used when the timer is in the event counting mode, the clock source being provided on pin-shared pin PA4/TMR. Depending upon the condition of the TE bit, each high to low, or low to high transition on the PA4/TMR pin will increment the counter by one.
D a ta B u s P r e lo a d R e g is te r PSC2~PSC0 (1 /1 ~ 1 /1 2 8 ) TM 1 TM 0 T im e r /E v e n t C o u n te r TON 8 - B it T im e r /E v e n t C o u n te r 2 O v e r flo w to In te rru p t R e lo a d
fS
YS
8 - S ta g e P r e s c a le r
T im e r /E v e n t C o u n te r M o d e C o n tro l
P A 4 /T M R In p u t
TE
PFD
8-bit Timer/Event Counter Structure
Rev. 1.20
25
August 15, 2007
HT46R46E/C46E/R47E/C47E/R48AE/C48AE/R49E
Timer Register - TMR The TMR register is an 8-bit special function register location within the special purpose Data Memory where the actual timer value is stored. The value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the PA4/TMR pin. The timer will count from the initial value loaded by the preload register to the full count value of FFH at which point the timer overflows and an internal interrupt signal generated. The timer value will then be reset with the initial preload register value and continue counting. For a maximum full range count of 00H to FFH the preload register must first be cleared to 00H. It should be noted that after power-on the preload register will be in an unknown condition. Note that if the Timer/Event Counter is not running and data is written to its preload register, this data will be immediately written into the actual counter. However, if the counter is enabled and counting, any new data written into the preload register during this period will remain in the preload register and will only be written into the actual counter the next time an overflow occurs. Timer Control Register - TMRC The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in three different modes, the options of which are determined by the contents of the Timer Control Register TMRC. Together with the TMR register, these two registers control the full operation of the Timer/Event Counters. Before the timer can be used, it is essential that the TMRC register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. To choose which of the three modes the timer is to operate in, the timer mode, the event counting mode or the pulse width measurement mode, bits TM0 and TM1 must be set to the required logic levels. The timer-on bit TON or bit 4 of the TMRC register provides the basic on/off control of the timer, setting the bit high allows the counter to run, clearing the bit stops the counter. Bits 0~2 of the TMRC register determine the division ratio of the input clock prescaler. The prescaler bit settings have no effect if an external clock source is used. If the timer is in the event count or pulse width measurement mode the active transition edge level type is selected by the logic level of the TE or bit 3 of the TMRC register.
b7 TM 1 TM 0 TON TE
b0 PSC2PSC1PSC0 TM RC T im e r P PSC2 0 0 0 0 1 1 1 1 E ventC 1:coun 0:coun P u ls e W 1 : s ta rt 0 : s ta rt R e g is te r r e s c a le r R a te S e le PSC0 PSC1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 o u n te r A c tiv e E d g t o n fa llin g e d g e t o n r is in g e d g e id th M e a s u r e m e n c o u n tin g o n r is in g c o u n tin g o n fa llin g ct T im e r 1 :1 1 :2 1 :4 1 :8 1 :1 1 :3 1 :6 1 :1 e S e le c t R a te
6 2
4 28
t A c tiv e E d g e S e le c t e d g e , s to p o n fa llin g e d g e e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r C o u n tin g E n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " O p e r a tin g M o d e S e le c t TM 1 TM 0 0 no m od 0 0 eventc 1 1 tim e r m 0 1 p u ls e w 1
e a v a ila b le o u n te r m o d e ode id th m e a s u r e m e n t m o d e
Timer/Event Counter Control Register
Rev. 1.20
26
August 15, 2007
HT46R46E/C46E/R47E/C47E/R48AE/C48AE/R49E
Configuring the Timer Mode In this mode, the timer can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the counter overflows. To operate in this mode, bits TM1 and TM0 of the TMRC register must be set to 1 and 0 respectively. In this mode, the internal clock is used as the timer clock. The input clock frequency to the timer is fSYS divided by the value programmed into the timer prescaler, the value of which is determined by bits PSC0~PSC2 of the TMRC register. The timer-on bit, TON must be set high to enable the timer to run. Each time an internal clock high to low transition occurs, the timer increments by one. When the timer is full and overflows, the timer will be reset to the value already loaded into the preload register and continue counting. If the timer interrupt is enabled, an interrupt signal will also be generated. The timer interrupt can be disabled by ensuring that the ETI bit in the INTC register is cleared to zero. It should be noted that a timer overflow is one of the wake-up sources. Configuring the Event Counter Mode In this mode, a number of externally changing logic events, occurring on external pin PA4/TMR, can be recorded by the internal timer. For the timer to operate in the event counting mode, bits TM1 and TM0 of the TMRC register must be set to 0 and 1 respectively. The timer-on bit, TON must be set high to enable the timer to count. With TE low, the counter will increment each time the PA4/TMR pin receives a low to high transition. If the TE bit is high, the counter will increment each time TMR receives a high to low transition. As in the case of the other two modes, when the counter is full and overflows, the timer will be reset to the value already loaded into the preload register and continue counting. If the timer interrupt is enabled, an interrupt signal will also be generated. The timer interrupt can be disabled by ensuring that the ETI bit in the INTC register is cleared to zero. To ensure that the external pin PA4/TMR is configured to operate as an event counter input pin, two things have to happen. The first is to ensure that the TM0 and TM1 bits place the timer/event counter in the event counting mode, the second is to ensure that the port control register configures the pin as an input. It should be noted that a timer overflow is one of the wake-up sources. Also in the Event Counting mode, the Timer/Event Counter will continue to record externally changing logic events on the timer input pin, even if the microcontroller is in the Power Down Mode. As a result when the timer overflows it will generate a wake-up and if the interrupts are enabled also generate a timer interrupt signal. Configuring the Pulse Width Measurement Mode In this mode, the width of external pulses applied to the pin-shared external pin PA4/TMR can be measured. In the Pulse Width Measurement Mode, the timer clock source is supplied by the internal clock. For the timer to operate in this mode, bits TM0 and TM1 must both be set high. If the TE bit is low, once a high to low transition has been received on the PA4/TMR pin, the timer will start counting until the PA4/TMR pin returns to its original high level. At this point the TON bit will be automatically reset to zero and the timer will stop counting. If the TE bit is high, the timer will begin counting once a low to high transition has been received on the PA4/TMR pin and stop counting when the PA4/TMR pin returns to its original low level. As before, the TON bit will be automatically reset to zero and the timer will stop counting. It is important to note that in the Pulse Width Measurement Mode, the TON bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the TON bit can only be reset to zero under program control. The residual value in the timer, which can now be read by the program, therefore represents the length of the pulse received on pin PA4/TMR. As the TON bit has now been reset any further transitions on the PA4/TMR pin will be ignored. Not until the TON bit is again set high by the program can the timer begin further pulse width measurements. In this way single shot pulse measurements can be easily made. It should be noted that in this mode the counter is controlled by logical transitions on the PA4/TMR pin and not by the logic level.
P r e s c a le r O u tp u t
In c re m e n t T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N + 1
Timer Mode Timing Chart
E x te rn a l E v e n t In c re m e n t T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Chart
Rev. 1.20
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As in the case of the other two modes, when the counter is full and overflows, the timer will be reset to the value already loaded into the preload register. If the timer interrupt is enabled, an interrupt signal will also be generated. To ensure that the external pin PA4/TMR is configured to operate as a pulse width measuring input pin, two things have to happen. The first is to ensure that the TM0 and TM1 bits place the timer/event counter in the pulse width measuring mode, the second is to ensure that the port control register configures the pin as an input. It should be noted that a timer overflow is one of the wake-up sources. Programmable Frequency Divider - PFD The PFD output is pin-shared with the I/O pin PA3. The PFD function is selected via configuration option, however, if not selected, the pin can operate as a normal I/O pin. The timer overflow signal is the clock source for the PFD circuit. The output frequency is controlled by loading the required values into the timer prescaler registers to give the required division ratio. The counter, driven by the system clock which is divided by the prescaler value, will begin to count-up from this preload register value until full, at which point an overflow signal is generated, causing the PFD output to change state. The counter will then be automatically reloaded with the preload register value and continue counting-up. For the PFD output to function, it is essential that the corresponding bit of the Port A control register PAC bit 3 is setup as an output. If setup as an input the PFD output will not function, however, the pin can still be used as a normal input pin. The PFD output will only be activated if
E x te rn a l T M R P in In p u t TON ( w ith T E = 0 )
bit PA3 is set to 1. This output data bit is used as the on/off control bit for the PFD output. Note that the PFD output will be low if the PA3 output data bit is cleared to 0. Using this method of frequency generation, and if a crystal oscillator is used for the system clock, very precise values of frequency can be generated. Prescaler Bits PSC0~PSC2 of the TMRC register can be used to define the pre-scaling stages of the internal clock sources of the Timer/Event Counter. The Timer/Event Counter overflow signal can be used to generate signals for the PFD and Timer Interrupt. I/O Interfacing The Timer/Event Counter, when configured to run in the event counter or pulse width measurement mode, require the use of the external PA4/TMR pin for correct operation. As this pin is a shared pin it must be configured correctly to ensure it is setup for use as a Timer/Event Counter input and not as a normal I/O pin. This is implemented by ensuring that the mode select bits in the Timer/Event Counter control register, select either the event counter or pulse width measurement mode. Additionally the Port Control Register PAC bit 4 must be set high to ensure that the pin is setup as an input. Any pull-high resistor configuration option on this pin will remain valid even if the pin is used as a Timer/Event Counter input.
P r e s c a le r O u tp u t In c re m e n t T im e r C o u n te r T im e r +1 +2 +3 +4
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Measure Mode Timing Chart
T im e r O v e r flo w PFD C lo c k
P A 3 D a ta
PFD
O u tp u t a t P A 3
PFD Output Control
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Programming Considerations When configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronized with the overall operation of the microcontroller. In this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. As this is an external event and not sync h ro n iz ed w i t h t h e i n t e r nal t i m e r c l o ck, t h e microcontroller will only see this external event when the next timer clock pulse arrives. As a result, there may be small differences in measured values requiring programmers to take this into account during programming. The same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronized with the internal system or timer clock. When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. After the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. Note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. Setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt control register will be set. If the timer interrupt is enabled this will in turn generate an interrupt signal. However irrespective of whether the interrupts are enabled or not, a Timer/Event counter overflow will also generate a wake-up signal if the device is in a Power-down condition. This situation may occur if the Timer/Event Counter is in the Event Counting Mode and if the external signal continues to change state. In such a case, the Timer/Event Counter will continue to count these external events and if an overflow occurs the device will be woken up from its Power-down condition. To prevent such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the HALT instruction to enter the Power Down Mode. Timer Program Example This program example shows how the Timer/Event Counter registers are setup, along with how the interrupts are enabled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the Timer Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the same bit. This example program sets the Timer/Event Counter to be in the timer mode, which uses the internal system clock as the clock source.
org 04h ; external interrupt vector reti org 08h ; Timer/Event Counter interrupt vector jmp tmrint ; jump here when Timer overflows : org 20h ; main program ;internal Timer/Event Counter interrupt routine tmrint: : ; Timer/Event Counter main program placed here : reti : : begin: ;setup Timer registers mov a,09bh ; setup Timer preload value mov tmr,a; mov a,081h ; setup Timer control register mov tmrc,a ; timer mode and prescaler set to /2 ; setup interrupt register mov a,005h ; enable master interrupt and timer interrupt mov intc,a set tmrc.4 ; start Timer - note Mode bits must be previously setup
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Pulse Width Modulator
Each microcontroller in the Cost-effective A/D Type MCU series contains either one or two Pulse Width Modulation, PWM, outputs. Useful for such applications such as motor speed control, the PWM function provides outputs with a fixed frequency but with a duty cycle that can be varied by setting particular values into the corresponding PWM register. Device HT46R49E Other Devices Channels 2 1 PWM Output Register Mode Pins Name 6+2 6+2 PD0/ PD1 PD0 PWM0/ PWM1 PWM 6+2 PWM Mode Each full PWM cycle, as it is controlled by an 8-bit PWM, PWM0 or PWM1 register, has 256 clock periods. However, in the 6+2 PWM Mode, each PWM cycle is subdivided into four individual sub-cycles known as modulation cycle 0~modulation cycle 3, denoted as i in the table. Each one of these four sub-cycles contains 64 clock cycles. In this mode, a modulation frequency increase by a factor of four is achieved. The 8-bit PWM, PWM0 or PWM1 register value, which represents the overall duty cycle of the PWM waveform, is divided into two groups. The first group which consists of bit2~bit7 is denoted here as the DC value. The second group which consists of bit0~bit1 is known as the AC value. In the 6+2 PWM mode, the duty cycle value of each of the four modulation sub-cycles is shown in the following table. Parameter AC (0~3) iFor devices with one PWM output, a single register, located in the Data Memory is assigned to the Pulse Width Modulator and is known as the PWM register. For devices with two PWM outputs, two registers are provided and are known as PWM0 and PWM1. It is in these registers, that the 8-bit value, which represents the overall duty cycle of one modulation cycle of the output waveform, should be placed. To increase the PWM modulation frequency, each modulation cycle is modulated into four individual modulation sub-sections, known as the 6+2 mode. Note that it is only necessary to write the required modulation value into the corresponding PWM register as the subdivision of the waveform into its sub-modulation cycles is implemented automatically within the microcontroller hardware. For all devices, the PWM clock source is the system clock fSYS. This method of dividing the original modulation cycle into a further 4 sub-cycles enables the generation of higher PWM frequencies, which allow a wider range of applications to be served. As long as the periods of the generated PWM pulses are less than the time constants of the load, the PWM output will be suitable as such long time constant loads will average out the pulses of the PWM output. The difference between what is known as the PWM cycle frequency and the PWM modulation frequency should be understood. As the PWM clock is the system clock, fSYS, and as the PWM value is 8-bits wide, the overall PWM cycle frequency is fSYS/256, while the PWM modulation frequency for the 6+2 mode of operation will be fSYS/64. PWM Modulation Frequency fSYS/64 PWM Cycle Frequency fSYS/256 PWM Cycle Duty (PWM register value)/256
6+2 Mode Modulation Cycle Values The following diagram illustrates the waveforms associated with the 6+2 mode of PWM operation. It is important to note how the single PWM cycle is subdivided into 4 individual modulation cycles, numbered from 0~3 and how the AC value is related to the PWM value. PWM Output Control On all devices, the PWM outputs are pin-shared with pins PD0 and PD1. To operate as PWM outputs and not as I/O pins, the correct PWM configuration options must be selected. A 0 must also be written to the corresponding bits in the I/O port control register PDC to ensure that the required PWM output pin is setup as an output. After these two initial steps have been carried out, and of course after the required PWM value has been written into the PWM register, writing a 1 to the corresponding bit in the PD output data register will enable the PWM data to appear on the pin. Writing a 0 to the corresponding bit in the PD output data register will disable the PWM output function and force the output low. In this way, the Port D data output register can be used as an on/off control for the PWM function. Note that if the configuration options have selected the PWM function, but a 1 has been written to its corresponding bit in the PDC control register to configure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor options.
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fS
YS
/2
[P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M PW M 2 6 /6 4 m o d u la tio n p e r io d : 6 4 /fS M o d u la tio n c y c le 0
YS
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4 M o d u la tio n c y c le 1 PW M
2 6 /6 4 M o d u la tio n c y c le 2 c y c le : 2 5 6 /fS
YS
2 5 /6 4 M o d u la tio n c y c le 3
2 6 /6 4 M o d u la tio n c y c le 0
6+2 PWM Mode
b7 b0 P W M , P W M 0 , P W M 1 R e g is te r AC DC v a lu e v a lu e
Pulse Width Modulation Registers
PWM Programming Example The following sample program shows how the PWM outputs are setup and controlled. Before use the corresponding PWM output configuration options must first be selected. mov mov clr set : : clr a,64h pwm,a pdc.0 pd.0 : : pd.0 ; setup PWM value of 100 decimal which is 64H ; setup pin PD0 as an output ; PD.0=1; enable the PWM output
; disable the PWM output - PD0 will remain low
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Analog to Digital Converter
The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview Each of the devices contains a 4-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either an 8-bit or 9-bit digital value. Device HT46R46E HT46R47E HT46R48AE HT46R49E Input Conversion Input Pins Channels Bits 4 4 4 4 8 9 9 9 PB0~PB3 PB0~PB3 PB0~PB3 PB0~PB3 Converter Data Registers, note that only the high byte register ADRH utilises its full 8-bit contents. The low byte register utilises only 1 bit of its 8-bit contents as it contains only the lowest bit of the 9-bit converted value. In the following tables, D0~D8 are the A/D conversion data result bits. Register ADR Bit 7 D7 Bit 6 D6 Bit 5 D5 Bit 4 D4 Bit 3 D3 Bit 2 D2 Bit 1 D1 Bit 0 D0
A/D Data Register - HT46R46E Bit 7 D0 D8 Bit 6 3/4 D7 Bit 5 3/4 D6 Bit 4 3/4 D5 Bit 3 3/4 D4 Bit 2 3/4 D3 Bit 1 3/4 D2 Bit 0 3/4 D1
Register ADRL ADRH
A/D Data Register - Other Devices A/D Converter Control Register - ADCR To control the function and operation of the A/D converter, a control register known as ADCR is provided. This 8-bit register defines functions such as the selection of which analog channel is connected to the internal A/D converter, which pins are used as analog inputs and which are used as normal I/Os as well as controlling the start function and monitoring the A/D converter end of conversion status. One section of this register contains the bits ACS2~ACS0 which define the channel number. As each of the devices contains only one actual analog to digital converter circuit, each of the individual 4 analog inputs must be routed to the converter. It is the function of the ACS2~ACS0 bits in the ADCR register to determine which analog channel is actually connected to the internal A/D converter. Note that the ACS2 bit must always be assigned a zero value.
The following diagram shows the overall internal structure of the A/D converter, together with its associated registers. A/D Converter Data Registers - ADR, ADRL, ADRH For the HT46R46E device, which has an 8-bit A/D converter, a single register, known as ADR, is used to store the 8-bit analog to digital conversion value. For the remaining devices, which have a 9-bit A/D converter, two registers are required, a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. For devices which use two A/D
A D C S o u rc e fS Y S /2 PB PB PB PB 0 /A 1 /A 2 /A 3 /A N0 N1 N2 N3
C lo c k D iv id e R a tio N V
DD
A C S R R e g is te r A /D r e fe r e n c e v o lta g e ADR or ADRL ADRH A /D D a ta R e g is te r s
ADC
PCR0~PCR2 P in C o n fig u r a tio n B its
ADCS0~ADCS2 C h a n n e l S e le c t B its
START
EOCB
ADCR R e g is te r
S ta r t B it E n d o f C o n v e r s io n B its
A/D Converter Structure
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The ADCR control register also contains the PCR2~PCR0 bits which determine which pins on Port B are used as analog inputs for the A/D converter and which pins are to be used as normal I/O pins. If the 3-bit address on PCR2~PCR0 has a value of 100 or higher, then all four pins, namely AN0, AN1, AN2 and AN3 will all be set as analog inputs. Note that if the PCR2~PCR0 bits are all set to zero, then all the Port B pins will be setup as normal I/Os and the internal A/D converter circuitry will be powered off to reduce the power consumption. The START bit in the ADCR register is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the ADCR register will be set to a 1 and the analog to digital converter will be reset. It is the START bit that is used to control the overall on/off operation of the internal analog to digital converter. The EOCB bit in the ADCR register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D interb7 START EO CB b0 ACS0
nal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. A/D Converter Clock Source Register - ACSR The clock source for the A/D converter, which originates from the system clock fSYS, is first divided by a division ratio, the value of which is determined by the ADCS1 and ADCS0 bits in the ACSR register. Although the A/D clock source is determined by the system clock fSYS, and by bits ADCS1 and ADCS0, there are some limitations on the maximum A/D clock source speed that can be selected. As the minimum value of permissible A/D clock period, tAD, is 0.5ms for the HT46R46E, device, and 1ms for the other devices, care must be taken for system clock speeds in excess of 2MHz. With the exception of the HT46R46E device, for system clock speeds in excess of 2MHz, the ADCS1 and ADCS0 bits should not be set to 00. For the HT46R46E device, for system clock speeds in excess of 4MHz, the ADCS1 and ADCS0 bits should not be set to 00. Doing so will give A/D clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period.
ADCR R e g is te r
PCR2
PCR1
PCR0
ACS2
ACS1
S e le c t A /D c h a n n e l ACS2 ACS1 ACS0 0 0 0 0 0 1 0 1 0 0 1 1 1 X X P o r t B A /D c h a n n e l c o n fig PCR2 PCR1 PCR0 0 0 0 1 0 0 0 1 0 1 1 0 X X 1
:AN :AN :AN :AN :un
0 2 3 d e fin e d , m u s t n o t b e u s e d 1
u r a tio n s :P :P :P :P :P o rt B0 B0 B0 B0 B en ~P ~P ~P A /D ab B1 B2 B3 chann le d a s A e n a b le e n a b le e n a b le e ls N0 da da da - a ll o ff s AN0~AN1 s AN0~AN2 s AN0~AN3
E n d o f A /D c o n v e r s io n fla g 1 : n o t e n d o f A /D c o n v e r s io n - A /D c o n v e r s io n w a itin g o r in p r o g r e s s 0 : e n d o f A /D c o n v e r s io n - A /D c o n v e r s io n e n d e d S ta r t th e A /D c o n v e r s io n 0 (R) 1 (R) 0 : S ta rt 0 (R) 1 : R e s e t A /D c o n v e rte r a n d s e t E O C B to "1 "
A/D Converter Control Register
b7 TEST b0 ADCS1ADCS0 ACSR R e g is te r c k s o u rc e s te s te s te de c lo c k /2 c lo c k /8 c lo c k /3 2 fin e d m m m
S e le c t A /D c o n v e r te r c lo ADCS1 ADCS0 0 0 :sy :sy 0 1 1 0 :sy 1 1 :un F o r te s t m o d e u s e o n ly
N o t im p le m e n te d , r e a d a s " 0 "
A/D Converter Clock Source Register
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A/D Clock Period (tAD) fSYS 1MHz 2MHz 4MHz 8MHz ADCS1, ADCS0=00 (fSYS/2) 2ms 1ms 500ns* 250ns* ADCS1, ADCS0=01 (fSYS/8) 8ms 4ms 2ms 1ms A/D Clock Period Examples ADCS1, ADCS0=10 (fSYS/32) 32ms 16ms 8ms 4ms ADCS1, ADCS0=11 Undefined Undefined Undefined Undefined
A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port B. Bits PCR2~PCR0 in the ADCR register, not configuration options, determine whether the input pins are setup as normal Port B input/output pins or whether they are setup as analog inputs. In this way, pins can be changed under program control to change their function from normal I/O operation to analog inputs and vice versa. Pull-high resistors, which are setup through configuration options, apply to the input pins only when they are used as normal I/O pins, if setup as A/D inputs the pull-high resistors will be automatically disconnected. Note that it is not necessary to first setup the A/D pin as an input in the PBC port control register to enable the A/D input, when the PCR2~PCR0 bits enable an A/D input, the status of the port control register will be overridden. The VDD power supply pin is used as the A/D converter reference voltage, and as such analog inputs must not be allowed to exceed this value. Appropriate measures should also be taken to ensure that the VDD pin remains as stable and noise free as possible. Initialising the A/D Converter The internal A/D converter must be initialised in a special way. Each time the Port B A/D channel selection bits are modified by the program, the A/D converter must be re-initialised. If the A/D converter is not initialised after the channel selection bits are changed, the EOCB flag may have an undefined value, which may produce a false end of conversion signal. To initialise the A/D converter after the channel selection bits have changed, then, within a time frame of one to ten instruction cycles, the START bit in the ADCR register must first be set high and then immediately cleared to zero. This will ensure that the EOCB flag is correctly set to a high condition. Summary of A/D Conversion Steps The following summarizes the individual steps that should be executed in order to implement an A/D conversion process.
* Step 1
Select the required A/D conversion clock by correctly programming bits ADCS1 and ADCS0 in the ACSR register.
* Step 2
Select which channel is to be connected to the internal A/D converter by correctly programming the ACS2~ACS0 bits which are also contained in the ADCR register.
* Step 3
Select which pins on Port B are to be used as A/D inputs and configure them as A/D input pins by correctly programming the PCR2~PCR0 bits in the ADCR register. Note that this step can be combined with Step 2 into a single ADCR register programming operation.
* Step 4
If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, in the INTC interrupt control register must be set to 1 and the A/D converter interrupt bit, EADI, in the INTC register must also be set to 1.
* Step 5
The analog to digital conversion process can now be initialised by setting the START bit in the ADCR register from 0 to 1 and then to 0 again. Note that this bit should have been originally set to 0.
* Step 6
To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an alternative method if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR register is used, the interrupt enable step above can be omitted.
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The following timing diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing.
S T A R T b it s e t h ig h w ith in o n e to te n in s tr u c tio n c y c le s a fte r th e P C R 0 ~ P C R 2 b its c h a n g e s ta te START
EOCB PC R2~ PCR0
A /D 3 2 tA
s a m p lin g tim e
D
A /D
s a m p lin g tim e
D
A /D
s a m p lin g tim e
D
3 2 tA 011B
3 2 tA
000B
100B
000B 1 . P B p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n
AC S2~ ACS0
000B P o w e r-o n R eset R e s e t A /D c o n v e rte r 1 : D e fin e P B c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l
010B S ta rt o f A /D c o n v e r s io n
000B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
001B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
D o n 't c a r e
E n d o f A /D c o n v e r s io n tA A /D
DC
tA A /D N o te : A /D c lo c k m u s t b e fS
YS
DC
tA A /D /3 2
DC
c o n v e r s io n tim e
YS
c o n v e r s io n tim e
c o n v e r s io n tim e
/2 , fS
/8 o r fS
YS
A/D Conversion Timing
The setting up and operation of the A/D converter function is fully under the control of the application program as there are no configuration options associated with the A/D converter. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is dependent upon the device chosen and is a function of the A/D clock period tAD as shown in the table. Device HT46R46E Other Devices A/D Conversion Time 64tAD 76tAD A/D Conversion Time Programming Considerations When programming, special attention must be given to the A/D channel selection bits in the ADCR register. If these bits are all cleared to zero no external pins will be selected for use as A/D input pins allowing the pins to be used as normal I/O pins. When this happens the power
supplied to the internal A/D circuitry will be reduced resulting in a reduction of supply current. This ability to reduce power by turning off the internal A/D function by clearing the A/D channel selection bits may be an important consideration in battery powered applications. Another important programming consideration is that when the A/D channel selection bits change value the A/D converter must be re-initialised. This is achieved by pulsing the START bit in the ADCR register immediately after the channel selection bits have changed state. The exception to this is where the channel selection bits are all cleared, in which case the A/D converter is not required to be re-initialised. A/D Programming Example The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using an EOCB polling method to detect the end of conversion for the HT46R46E clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as ; the A/D clock mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 ; as A/D inputs mov ADCR,a ; and select AN0 to be connected to the A/D ; converter : Rev. 1.20 35 August 15, 2007
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: ; ; ; ; As the Port B channel bits have changed the following START signal (0-1-0) must be issued within 10 instruction cycles
: Start_conversion: clr set clr Polling_EOC: sz jmp mov mov START START START EOCB polling_EOC a,ADR adr_buffer,a : : start_conversion
; reset A/D ; start A/D ; ; ; ; ; ; poll the ADCR register EOCB bit to detect end of A/D conversion continue polling read conversion result value from the ADR register save result to user defined memory
jmp
; start next A/D conversion
Example: using an interrupt method to detect the end of conversion for the HT46R46E clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as ; the A/D clock mov mov a,00100000B ADCR,a : ; ; ; ; : Start_conversion: clr set clr clr set set START START START ADF EADI EMI : : : ; ADC interrupt service routine ADC_ISR: mov acc_stack,a mov a,STATUS mov status_stack,a : : mov a,ADR mov adr_buffer,a : : a,status_stack STATUS,a a,acc_stack As the Port B channel bits have changed the following START signal (0-1-0) must be issued within 10 instruction cycles ; ; ; ; setup ADCR register to configure Port PB0~PB3 as A/D inputs and select AN0 to be connected to the A/D converter
; ; ; ; ;
reset A/D start A/D clear ADC interrupt request flag enable ADC interrupt enable global interrupt
; save ACC to user defined memory ; save STATUS to user defined memory
; read conversion result value from the ADR ; register ; save result to user defined register
EXIT_INT_ISR: mov mov mov reti
; restore STATUS from user defined memory ; restore ACC from user defined memory
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A/D Transfer Function As the HT46R46E device contain an 8-bit A/D converter, their full-scale converted digitized value is equal to 0FFH. Since the full-scale analog input value is equal to the voltage, this gives a single bit analog input value of VDD/256. For the other devices which each contain a 9-bit A/D converter, their full-scale converted digitised value is equal to 1FFH giving a single bit analog input value of VDD/512. The following graphs show the ideal transfer function between the analog input value and the digitised output value for the A/D converters. Note that to reduce the quantisation error, a 0.5 LSB offset is added to the A/D Converter input. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the VDD level.
1 .5 L S B
FFH
FEH FDH A /D C o n v e r s io n R e s u lt 03H 02H 01H 0 1 2 253 254 A n a lo g In p u t V o lta g e 3 255 256 ( V 256
DD
0 .5 L S B
)
Ideal A/D Transfer Function - HT46R46E
1 .5 L S B 1FFH 1FEH 1FD H A /D C o n v e r s io n R e s u lt 03H 02H 01H 0 1 2 509 510 A n a lo g In p u t V o lta g e 3 511 512 ( V 512
DD
0 .5 L S B
)
Ideal A/D Transfer Function - Other Devices
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Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer/Event Counter or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. Each device in this series contains a single external interrupt and two internal interrupts functions. The external interrupt is controlled by the action of the external INT pin, while the internal interrupts are controlled by the Timer/Event Counter overflow and the A/D converter interrupt. Interrupt Register Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by a single INTC register, which is located in Data Memory. By controlling the appropriate enable bits in this register each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. The global enable flag if cleared to zero will disable all interrupts. Interrupt Operation A Timer/Event Counter overflow, an end of A/D conversion or the external interrupt line being pulled low will all generate an interrupt request by setting their corresponding request flag, if their appropriate interrupt enable bit is set. When this happens, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The
b7 ADF TF E IF EADI ETI EEI b0 EMI IN T C R e g is te r M a s te r In te r r u p t G lo b a l E n a b le 1 : g lo b a l e n a b le 0 : g lo b a l d is a b le E x te r n a l In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le T im e r /E v e n t C o u n te r In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le A /D C o n v e r te r In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le E x te r n a l In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e T im e r /E v e n t C o u n te r In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e A /D C o n v e r te r In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e F o r te s t m o d e u s e o n ly . M u s t b e w r itte n a s " 0 " o th e r w is e m a y r e s u lt in u n p r e d ic ta b le o p e r a tio n
Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI statement, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the following diagram with their order of priority. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full.
Interrupt Control Register
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A u to m a tic a lly C le a r e d b y IS R M a n u a lly S e t o r C le a r e d b y S o ftw a r e E x te rn a l In te rru p t R e q u e s t F la g E IF T im e r /E v e n t C o u n te r In te r r u p t R e q u e s t F la g T F A /D C o n v e rte r In te r r u p t R e q u e s t F la g A D F EEI A u to m a tic a lly D is a b le d b y IS R C a n b e E n a b le d M a n u a lly P r io r ity EMI H ig h In te rru p t P o llin g Low
ETI
EADI
Interrupt Structure Interrupt Priority Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source External Interrupt Timer/Event Counter Overflow A/D Converter Interrupt All Devices Priority 1 2 3 interrupt enable bit, ETI, must first be set. An actual Timer/Event Counter interrupt will take place when the Timer/Event Counter request flag, TF, is set, a situation that will occur when the Timer/Event Counter overflows. When the interrupt is enabled, the stack is not full and a Timer/Event Counter overflow occurs, a subroutine call to the timer interrupt vector at location 08H, will take place. When the interrupt is serviced, the timer interrupt request flag, TF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. A/D Interrupt For an A/D interrupt to occur, the global interrupt enable bit, EMI, and the corresponding interrupt enable bit, EADI, must be first set. An actual A/D interrupt will take place when the A/D converter request flag, ADF, is set, a situation that will occur when an A/D conversion process has completed. When the interrupt is enabled, the stack is not full and an A/D conversion process finishes execution, a subroutine call to the A/D interrupt vector at location 0CH, will take place. When the interrupt is serviced, the A/D interrupt request flag, ADF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Programming Considerations By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the INTC register until the corresponding interrupt is serviced or until the request flag is cleared by a software instruction. It is recommended that programs do not use the CALL subroutine instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. All of these interrupts have the capability of waking up the processor when in the Power Down Mode.
In cases where both external and internal interrupts are enabled and where an external and internal interrupt occurs simultaneously, the external interrupt will always have priority and will therefore be serviced first. Suitable masking of the individual interrupts using the INTC register can prevent simultaneous occurrences. External Interrupt For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bit, EEI, must first be set. An actual external interrupt will take place when the external interrupt request flag, EIF, is set, a situation that will occur when a high to low transition appears on the INT line. The external interrupt pin is pin-shared with the I/O pin PA5 and can only be configured as an external interrupt pin if the corresponding external interrupt enable bit in the INTC register has been set. The pin must also be setup as an input by setting the corresponding PAC.5 bit in the port control register. When the interrupt is enabled, the stack is not full and a high to low transition appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 04H, will take place. When the interrupt is serviced, the external interrupt request flag, EIF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor configuration options on this pin will remain valid even if the pin is used as an external interrupt input. Timer/Event Counter Interrupt For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and the corresponding timer Rev. 1.20 39
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Only the Program Counter is pushed onto the stack. If the contents of the register or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance. enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer.
VDD RES S S T T im e - o u t In te rn a l R e s e t 0 .9 V tR
DD
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally:
* Power-on Reset
STD
Power-On Reset Timing Chart For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference.
VDD 100kW RES 0 .1 m F VSS
Basic Reset Circuit For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended.
0 .0 1 m F 100kW RES
10kW
VDD
0 .1 m F VSS
Reset Circuit More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website.
* RES Pin Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast
This type of reset occurs when the microcontroller is already running and the RES pin is forcefully pulled low by external hardware such as an external switch. In this case as in the case of other reset, the Program Counter will reset to zero and program execution initiated from this point.
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RES S S T T im e - o u t In te rn a l R e s e t 0 .4 V 0 .9 V
DD DD
Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 u 1 1 0 u u 1 RESET Conditions RES reset during power-on RES or LVR reset during normal operation WDT time-out reset during normal operation WDT time-out reset during Power Down
tR
STD
RES Reset Timing Chart
* Low Voltage Reset - LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is selected via a configuration option. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected via configuration options.
LVR tR S S T T im e - o u t In te rn a l R e s e t
STD
Note: u stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Program Counter Interrupts WDT Timer/Event Counter Prescaler Condition After RESET Reset to zero All interrupts will be disabled Clear after reset, WDT begins counting Timer Counter will be turned off The Timer Counter Prescaler will be cleared
Low Voltage Reset Timing Chart
* Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to 1.
W D T T im e - o u t
Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack
tR
S S T T im e - o u t In te rn a l R e s e t
STD
WDT Time-out Reset during Normal Operation Timing Chart
* Watchdog Time-out Reset during Power Down
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers.
The Watchdog time-out Reset during Power Down is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set to 1. Refer to the A.C. Characteristics for tSST details.
W D T T im e - o u t
tS
S S T T im e - o u t
ST
WDT Time-out Reset during Power Down Timing Chart
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HT46R46E Register MP ACC PCL TBLP TBLH STATUS INTC TMR TMRC PA PAC PB PBC PD PDC PWM ADR ADCR ACSR Reset (Power-on) 1xxx xxxx xxxx xxxx 0000 0000 xxxx xxxx --xx xxxx --00 xxxx -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 ------------1111 1111 ---1 ---1 RES or LVR Reset 1uuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu --uu uuuu -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 ------------1111 1111 ---1 ---1 WDT Time-out (Normal Operation) 1uuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu --1u uuuu -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 ------------1111 1111 ---1 ---1 WDT Time-out (HALT) 1uuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu --11 uuuu -uuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu ------------uuuu uuuu ---u ---u
xxxx xxxx xxxx xxxx 0100 0000 1----00
xxxx xxxx xxxx xxxx 0100 0000 1----00
xxxx xxxx xxxx xxxx 0100 0000 1----00
uuuu uuuu uuuu uuuu uuuu uuuu u----uu
u stands for unchanged x stands for unknown - stands for unimplemented
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HT46R47E Register MP ACC PCL TBLP TBLH STATUS INTC TMR TMRC PA PAC PB PBC PD PDC PWM ADRL ADRH ADCR ACSR Reset (Power-on) 1xxx xxxx xxxx xxxx 0000 0000 xxxx xxxx --xx xxxx --00 xxxx -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 ------------1111 1111 ---1 ---1 RES or LVR Reset 1uuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu --uu uuuu -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 ------------1111 1111 ---1 ---1 WDT Time-out (Normal Operation) 1uuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu --1u uuuu -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 ------------1111 1111 ---1 ---1 WDT Time-out (HALT) 1uuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu --11 uuuu -uuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu ------------uuuu uuuu ---u ---u
xxxx xxxx x--- ---xxxx xxxx 0100 0000 1----00
xxxx xxxx x--- ---xxxx xxxx 0100 0000 1----00
xxxx xxxx x--- ---xxxx xxxx 0100 0000 1----00
uuuu uuuu u--- ---uuuu uuuu uuuu uuuu u----uu
u stands for unchanged x stands for unknown - stands for unimplemented
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HT46R48AE Register MP ACC PCL TBLP TBLH STATUS INTC TMR TMRC PA PAC PB PBC PC PCC PD PDC PWM ADRL ADRH ADCR ACSR Reset (Power-on) 1xxx xxxx xxxx xxxx 0000 0000 xxxx xxxx --xx xxxx --00 xxxx -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 --------------11 --11 ---1 ---1 RES or LVR Reset 1uuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu --uu uuuu -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 --------------11 --11 ---1 ---1 WDT Time-out (Normal Operation) 1uuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu --1u uuuu -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 --------------11 --11 ---1 ---1 WDT Time-out (HALT) 1uuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu --11 uuuu -uuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --------------uu --uu ---u ---u
xxxx xxxx x--- ---xxxx xxxx 0100 0000 1----00
xxxx xxxx x--- ---xxxx xxxx 0100 0000 1----00
xxxx xxxx x--- ---xxxx xxxx 0100 0000 1----00
uuuu uuuu u--- ---uuuu uuuu uuuu uuuu u----uu
u stands for unchanged x stands for unknown - stands for unimplemented
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HT46R49E Register MP ACC PCL TBLP TBLH STATUS INTC TMR TMRC PA PAC PB PBC PC PCC PD PDC PWM0 PWM1 ADRL ADRH ADCR ACSR Reset (Power-on) xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx -xxx xxxx --00 xxxx -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 ---1 1111 ---1 1111 --------11 --11 RES or LVR Reset uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu --uu uuuu -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 ---1 1111 ---1 1111 --------11 --11 WDT Time-out (Normal Operation) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu --1u uuuu -000 0000 xxxx xxxx 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 ---1 1111 ---1 1111 --------11 --11 WDT Time-out (HALT) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuu ---u uuuu --------uu --uu
xxxx xxxx xxxx xxxx x--- ---xxxx xxxx 0100 0000 1----00
xxxx xxxx xxxx xxxx x--- ---xxxx xxxx 0100 0000 1----00
xxxx xxxx xxxx xxxx x--- ---xxxx xxxx 0100 0000 1----00
uuuu uuuu uuuu uuuu u--- ---uuuu uuuu uuuu uuuu u----uu
u stands for unchanged x stands for unknown - stands for unimplemented
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Oscillator
Various oscillator options offer the user a wide range of functions according to their various application requirements. Two types of system clocks can be selected while various clock source options for the Watchdog Timer, are provided for maximum flexibility. All oscillator options are selected through the configuration options. System Clock Configurations There are two methods of generating the system clock, using an external crystal/ceramic oscillator or an external RC network. The chosen method is selected through the configuration options. System Crystal/Ceramic Oscillator After selecting the correct oscillator configuration option, for most crystal oscillator configurations, the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. However, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer's specification. In most applications, resistor R1 is not required, however for those applications where the LVR function is not used, R1 may be necessary to ensure the oscillator stops running when VDD falls below its operating range.
C1
External System RC Oscillator After selecting the correct configuration option, using the external system RC oscillator requires that a resistor, with a value between 24kW and 1MW, is connected between OSC1 and VDD, and a 470pF capacitor is connected to ground. Although this is a cost effective oscillator configuration, the oscillation frequency can vary with VDD, temperature and process variations and is therefore not suitable for applications where timing is critical or where accurate oscillator frequencies are required. For the value of the external resistor ROSC refer to the Appendix section for typical RC Oscillator vs. Temperature and VDD characteristics graphics.
V R
OSC DD
OSC1 470pF fS
YS
/4 N M O S O p e n D r a in
OSC2
RC Oscillator
OSC1
R1
Note that it is the only microcontroller internal circuitry together with the external resistor, that determine the frequency of the oscillator. The external capacitor shown on the diagram does not influence the frequency of oscillation. The external capacitor is added to improve oscillator stability, especially if the open-drain OSC2 output is utilised in the application circuit.
OSC2
C2
Crystal/Ceramic Oscillator More information regarding the oscillator is located in Application Note HA0075E on the Holtek website.
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Power Down Mode and Wake-up
Power Down Mode All of the Holtek microcontrollers have the ability to enter a Power Down Mode, also known as the HALT Mode or Sleep Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. This occurs because when the device enters the Power Down Mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the MCU must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. Entering the Power Down Mode There is only one way for the device to enter the Power Down Mode and that is to execute the HALT instruction in the application program. When this instruction is executed, the following will occur:
* The system oscillator will stop running and the appli-
inputs. Also note that additional standby current will also be required if the configuration options have enabled the Watchdog Timer internal oscillator. Wake-up After the system enters the Power Down Mode, it can be woken up from one of various sources listed as follows:
* An external reset * An external falling edge on Port A * A system interrupt * A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup via an individual configuration option to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the HALT instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the HALT instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled. No matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal system operation resumes. However, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or more cycles. If the wake-up results in the execution of the next instruction following the HALT instruction, this will be executed immediately after the 1024 system clock period delay has ended.
cation program will stop at the HALT instruction.
* The Data Memory contents and registers will maintain
their present condition.
* The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT oscillator. The WDT will stop if its clock source originates from the system clock.
* The I/O ports will maintain their present condition. * In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the Power Down Mode is to keep the current consumption of the MCU to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimized. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be undonbed pins, which must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS Rev. 1.20 47
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Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. It operates by providing a device reset when the WDT counter overflows. The WDT clock is supplied by one of two sources selected by configuration option: its own self contained dedicated internal WDT oscillator or fSYS/4. Note that if the WDT configuration option has been disabled, then any instruction relating to its operation will result in no operation. I n t h e C os t - E ff e c t i v e A / D Ty p e s e r i e s o f microcontrollers, all Watchdog Timer options, such as enable/disable, WDT clock source and clear instruction type all selected through configuration options. There are no internal registers associated with the WDT in the Cost-Effective A/D Type MCU series. One of the WDT clock sources is an internal oscillator which has an approximate period of 65ms at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The other WDT clock source option is the fSYS/4 clock. Whether the WDT clock source is its own internal WDT oscillator, or from fSYS/4, it is further divided by 16 via an internal 15-bit counter and a clearable single bit counter to give longer Watchdog time-outs. As this ratio is fixed it gives an overall Watchdog Timer time-out value of 215/fS to 216/fS. As the clear instruction only resets the last stage of the divider chain, for this reason the actual division ratio and corresponding Watchdog Timer time-out can vary by a factor of two. The exact division ratio depends upon the residual value in the Watchdog Timer counter before the clear instruction is executed. It is important to realise that as there are no independent internal registers or configuration options associated with the length of the Watchdog Timer time-out, it is completely dependent upon the frequency of fSYS/4 or the internal WDT oscillator. If the fSYS/4 clock is used as the WDT clock source, it should be noted that when the system enters the Power Down Mode, then the instruction clock is stopped and the WDT will lose its protecting purposes. For systems that operate in noisy environments, using the internal WDT oscillator is strongly recommended. Under normal program operation, a WDT time-out will initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a WDT time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the WDT. The first is an external hardware reset, which means a low level on the RES pin, the second is using the watchdog software instructions and the third is via a HALT instruction. There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use the single CLR WDT instruction while the second is to use the two commands CLR WDT1 and CLR WDT2. For the first option, a simple execution of CLR WDT will clear the WDT while for the second option, both CLR WDT1 and CLR WDT2 must both be executed to successfully clear the WDT. Note that for this second option, if CLR WDT1 is used to clear the WDT, successive executions of this instruction will have no effect, only the execution of a CLR WDT2 instruction will clear the WDT. Similarly after the CLR WDT2 instruction has been executed, only a successive CLR WDT1 instruction can clear the Watchdog Timer.
CLR CLR
W D T 1 F la g W D T 2 F la g
C le a r W D T T y p e C o n fig u r a tio n O p tio n
1 o r 2 In s tr u c tio n s fS
YS
/4
W D T O s c illa to r W D T C lo c k S o u r c e
W D T C lo c k S o u r c e C o n fig u r a tio n O p tio n
fS
C LR
1 5 - b it C o u n te r
2
2
W D T T im e - o u t 15/f S ~ 2 16/fS
Watchdog Timer
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Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later as the application software has no control over the configuration options. All options must be defined for proper system function, the details of which are shown in the table. No. 1 2 3 4 5 6 7 8 9 Options Watchdog Timer clock source: WDT oscillator or fSYS/4 Watchdog Timer function: enable or disable CLRWDT instructions: 1 or 2 instructions System oscillator: Crystal or RC PA, PB and PD: pull-high enable or disable PC: pull-high enable or disable - HT46R48AE and HT46R49E only PWM: enable or disable - Except HT46R49E PWM0, PWM1: enable or disable - HT46R49E only PA0~PA7: wake-up enable or disable - bit option PFD: normal I/O or PFD output LVR function: enable or disable
Application Circuits
V
DD
VDD Reset C ir c u it RES 0 .1 m F VSS OSC C ir c u it OSC1 OSC2
PA0~PA2 P A 3 /P F D P A 4 /T M R P A 5 /IN T PA6~PA7 P B 0 /A N 0 ~ P B 3 /A N 3 PB4~PB7 P C 0 /S D A ~ P C 1 /S C L PC2~PC4 P D 0 /P W M C2 R1 R V
DD
100kW 0 .1 m F
OSC
OSC1 fS
YS
R C S y s te m O s c illa to r 24kW 470pF C1
/4
OSC2 OSC1 Cr Sy Fo C1 Os y s ta l/C e s te m O s r d e ta ils ,C 2 and c illa to r S ra c re R e m ic illa to r g a r d in g 1 see c tio n
OSC2
OSC
C ir c u it
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Instruction Set
Introduction C e n t ra l t o t he s u c c e s s f u l oper a t i on o f a n y microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
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Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m]
Description Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory
Cycles 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note
Flag Affected Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Logic Operation
Increment & Decrement
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Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.20 Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z 53 August 15, 2007
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CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Operation
Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
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CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation
Affected flag(s)
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INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
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OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0; register INTC). If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Affected flag(s) RETI Description
Operation
Affected flag(s) RL [m] Description Operation
Affected flag(s) RLA [m] Description
Operation
Affected flag(s)
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RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation
Affected flag(s) RRA [m] Description
Operation
Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
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SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation
Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
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SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Operation Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
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SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
Affected flag(s) SZ [m] Description
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s) TABRDC [m] Description Operation
Affected flag(s) TABRDL [m] Description Operation
Affected flag(s)
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XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
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Package Information
18-pin DIP (300mil) Outline Dimensions
A 18 B 1 10 9
H C D E G F
a
I
Symbol A B C D E F G H I a
Dimensions in mil Min. 895 240 125 125 16 50 3/4 295 335 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 915 260 135 145 20 70 3/4 315 375 15
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18-pin SOP (300mil) Outline Dimensions
18 A 1
10 B 9
C C' G H D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 447 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 460 104 3/4 3/4 38 12 10
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24-pin SKDIP (300mil) Outline Dimensions
A 24 B 1 13 12
H C D E F G
a
I
Dimensions in mil Symbol Min. A B C D E F G H I a 1235 255 125 125 16 50 3/4 295 345 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 1265 265 135 145 20 70 3/4 315 360 15
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24-pin SOP (300mil) Outline Dimensions
24 A
13 B
1
12
C C' G H D E F
a
Dimensions in mil Symbol Min. A B C C D E F G H a 394 290 14 590 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 614 104 3/4 3/4 38 12 10
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28-pin SKDIP (300mil) Outline Dimensions
A 28 B 1 15 14
H C D E F G
a
I
Dimensions in mil Symbol Min. A B C D E F G H I a 1375 278 125 125 16 50 3/4 295 330 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 1395 298 135 145 20 70 3/4 315 375 15
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28-pin SOP (300mil) Outline Dimensions
28 A
15 B
1
14
C C' G H D E F
a
Dimensions in mil Symbol Min. A B C C D E F G H a 394 290 14 697 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 713 104 3/4 3/4 38 12 10
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Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 18W Symbol A B C D T1 T2 SOP 24W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301 621.5 13+0.5 -0.2 20.5 24.8+0.3 -0.2 30.20.2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.5 24.8+0.3 -0.2 30.20.2
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SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301 621.5 13+0.5 -0.2 20.5 24.8+0.3 -0.2 30.20.2
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Carrier Tape Dimensions
D
E F W C
P0
P1
t
B0
D1
P
K0 A0
SOP 18W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C SOP 24W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 240.3 120.1 1.750.1 11.50.1 1.55+0.1 1.5+0.25 40.1 20.1 10.90.1 15.90.1 3.10.1 0.350.05 21.3 Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.0+0.3 -0.1 16.00.1 1.750.1 11.50.1 1.50.1 1.5+0.25 4.00.1 2.00.1 10.90.1 12.00.1 2.80.1 0.30.05 21.3
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SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 240.3 120.1 1.750.1 11.50.1 1.5+0.1 1.5+0.25 40.1 20.1 10.850.1 18.340.1 2.970.1 0.350.01 21.3
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Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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