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GPS Down Converter IC
CXA3355AER
Description
The CXA3355AER is an IC developed as a GPS RF down converter. This IC realizes a reduction in the number of external parts by integrating an LNA, image rejection mixer, IF filter, PLL and VCO (L, C) into a small package with low current consumption. (Applications: GPS down converter IC)
Features
Includes all functions required for the GPS down converter Low voltage operation: VCC = 1.6 to 2.0V Low current consumption (active mode): 11mA (Typ. at VCC = 1.8V, IF 1MHz) Low current consumption (power save mode) < 1A Total gain 100dB Total NF 4dB On-chip VCO and PLL Supports typical TCXO frequencies (13MHz, 16.368MHz, 18.414MHz, etc.) On-chip LNA (LNA NF: 2.0dB) Image rejection mixer On-chip IF filter, and an external filter can be connected as an option for further band narrowing. 1-bit IF output Antenna sense function
Structure
SiGe BiCMOS monolithic IC
Package
44 pin VQFN (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E06702-CR
CXA3355AER
Absolute Maximum Ratings
(Ta = 25C) Supply voltage VCC1 VCC2 VCC3 Topr Tstg -0.2 to +2.5 -0.2 to +3.6 -0.2 to +3.6 -40 to +85 -65 to +150 V V V
C C
Operating temperature Storage temperature
Recommended Operating Conditions
Supply voltage VCC1 VCC2 VCC3 1.6 to 2.0 1.6 to 3.3 2.7 to 3.3 V V V
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CXA3355AER
Block Diagram and Pin Configuration
VCC1 (LNA) GND (LNA)
23 22 GND (LNA) RF_AMP VCC1 (RF) 35 Mixer TESTINP 36 1536fo [1539fo] TESTINN 37 4fo [fo] IF_AMP1 90 19 C_VCO Mixer 20 VCO_I LNA 21 GND (LNA) 18 GND DMPS TESTOUTN 39 IF Phase Shifter VCC1 (IF) 40 RC x2 16 VCC1 (PLL) MC SC PFD CP 17 LPF 15 GND (PLL) 14 TCXO IF_AMP2 ENABLE 43 LPF HPF A/D Converter 13 CLK_OUT CTL 12 LT 5 6 7 8 9 10 11
LNA_OUT
GND (RF)
GND (RF)
RF_INN
RF_INP
33 VCC1 (RF) 34
32
31
30
29
28
27
26
25
24
1540fo = 1575.42MHz
TESTOUTP 38 IF_AMP1
PLL
GND (IF) 41
R_EXT1 42
R_EXT2 44 1
BIAS 2 3
ANT SENSE 4
VCC2 (IF)
VCC3 (ANT)
DATA_OUT
GND (ANT)
GND (IF)
AILIM
DIAG
ASENS
C_EXT
DATA
LNA_IN
GND
GND
GND
fo mode: IF = 1.023MHz 4fo mode: IF = 4.092MHz
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CLK
CXA3355AER
Pin Description
Standard pin voltage [V] DC AC
Pin No.
Symbol
Equivalent circuit
Description
VCC3 (ANT)
1 ASENS
--
--
1
Antenna sense input.
GND (ANT)
VCC3 (ANT)
2 DIAG
--
--
2
Antenna sense output.
GND (ANT)
VCC3 (ANT)
3 AILIM
--
--
3
Antenna sense current limitation. Connect to the external PNP transistor base pin.
GND (ANT)
4 GND (ANT) 5 VCC3 (ANT)
0 3.0
-- --
Antenna sense GND. Antenna sense VCC. Leave open when not using the antenna sense function.
VCC1 (IF)
6 C_EXT
1.2
--
6
Capacitor connection for canceling the offset.
GND (IF)
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CXA3355AER
Pin No.
Symbol
Standard pin voltage [V] DC AC
Equivalent circuit
Description
VCC2 (IF)
7 DATA_OUT
--
1.8Vp-p
7
Data (IF) output.
GND (IF)
8 VCC2 (IF) 9 GND (IF) 10 DATA
1.8 0 --
-- -- --
VCC2 (IF) VCC1 (PLL)
IF block VCC. IF block GND. Serial data input.
11 CLK
--
--
10 11 12
Serial data clock input.
12 LT
--
--
GND (PLL)
Latch signal input.
VCC2 (IF)
13 CLK_OUT
--
1.8Vp-p
13
TCXO clock output. Leave open when not using the TCXO clock.
GND (IF)
VCC1 (PLL)
14 TCXO
--
--
14
Reference frequency input.
GND (PLL)
15 GND (PLL) 16 VCC1 (PLL)
0 1.8
-- --
PLL block GND. PLL block VCC.
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CXA3355AER
Pin No.
Symbol
Standard pin voltage [V] DC AC
Equivalent circuit
Description
VCC1 (PLL)
17 LPF
1.2
--
17
PLL loop filter connection.
GND (PLL)
18 GND
0
--
VCC1 (RF)
GND.
19 C_VCO
1.1
--
19
Capacitor connection for decoupling the VCO bias circuit.
GND (RF)
VCC1 (RF)
20 VCO_I
0.1
--
20
Capacitor connection for decoupling the VCO bias circuit.
GND (RF)
21 GND (LNA) 22 GND (LNA) 23 GND (LNA)
0 0 0
-- -- --
VCC1 (LNA)
LNA block GND. LNA block GND. LNA block GND.
24 LNA_IN
0.8
--
27
LNA input.
24
27 LNA_OUT
1.8
--
GND (LNA)
LNA output.
25 GND 26 GND 28 VCC1 (LNA)
0 0 1.8
-- -- --
GND. GND. LNA block VCC.
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CXA3355AER
Pin No.
Symbol
Standard pin voltage [V] DC 0 AC --
Equivalent circuit GND.
Description
29 GND
VCC1 (RF)
30 RF_INN
1.7
--
31 30
RF amplifier input.
31 RF_INP
1.7
--
GND (RF)
32 GND (RF) 33 GND (RF) 34 VCC1 (RF) 35 VCC1 (RF)
0 0 1.8 1.8
-- -- -- --
VCC1 (IF)
RF block GND. RF block GND. RF block VCC. RF block VCC.
36 TESTINP
1.3
--
IF signal input when using an external filter.
36 37
37 TESTINN
1.3
--
GND (IF)
IF signal input when using an external filter.
VCC1 (IF)
38 TESTOUTP
0.5
--
38 39
IF signal output when using an external filter.
39 TESTOUTN
0.5
--
GND (IF)
IF signal output when using an external filter.
40 VCC1 (IF) 41 GND (IF)
1.8 0
-- --
IF block VCC. IF block GND.
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CXA3355AER
Pin No.
Symbol
Standard pin voltage [V] DC AC
Equivalent circuit
Description
VCC1 (IF)
42 R_EXT1
0.5
--
External resistor connection. (bias)
42
GND (IF)
VCC2 (IF)
VCC1 (IF)
43 ENABLE
--
--
43
ENABLE signal input. High (V_IH: 1.2V min.): Active mode Low (V_IL: 0.2V max.): Power save mode
GND (IF)
VCC1 (IF)
44 R_EXT2
1.2
--
44
External resistor connection. (bias)
GND (IF)
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CXA3355AER
Electrical Characteristics
DC Characteristics
(VCC1 = VCC2 = 1.8V, VCC3 = OPEN, Ta = 25C) Item Supply current 1 Supply current 2 Supply current 3 Input impedance Output impedance Symbol ICC1 ICC2 ICC3 Zin Zout Conditions fo mode, excluding the antenna sense circuit 4fo mode, excluding the antenna sense circuit Power save mode Pin 36 (TESTINP), Pin 37 (TESTINN) Pin 38 (TESTOUTP), Pin 39 (TESTOUTN) Min. Typ. Max. 7 9 -- 50 50 11 13 0.1 100 100 15 17 1 200 200 Unit mA mA A
Note) fo mode and 4fo mode use the following power-on reset conditions. fo mode: TCXO = 18.414MHz, fLO = 1574.397MHz, IF = 1.023MHz 4fo mode: TCXO = 16.368MHz, fLO = 1571.328MHz, IF = 4.092MHz
AC Characteristics
(VCC1 = VCC2 = 1.8V, VCC3 = OPEN, Ta = 25C) Item Total voltage gain LNA NF1 LNA NF2 Total NF1 Total NF2 P-1dB input LPF1 (fo mode) LPF2 (fo mode) LPF3 (fo mode) BPF1 (4fo mode) BPF2 (4fo mode) BPF3 (4fo mode) BPF4 (4fo mode) C/N 100K Symbol G NF1 NF2 TNF1 TNF2 P1dB LPF1 LPF2 LPF3 BPF1 BPF2 BPF3 BPF4 C/N Conditions Excluding the A/D converter 50 matching, fo mode 50 matching, 4fo mode 50 matching, fo mode 50 matching, 4fo mode Up to before the A/D converter Detuning frequency = 1.023MHz, 4.092MHz @150kHz @2.046MHz @6MHz @1MHz @3.069MHz @5.115MHz @12MHz Normalized at the 1.023MHz level Normalized at the 1.023MHz level Normalized at the 4.092MHz level Normalized at the 4.092MHz level Normalized at the 4.092MHz level Normalized at the 4.092MHz level Min. Typ. Max. 85 -- -- -- -- -- -- -5 -- -- -9 -9 -- -- -- 100 3.0 2.0 5.0 4.0 -100 -40 -- -- -- -- -- -- -- -70 -40 -- 6 5 8.5 7.5 -- -20 4 2 -13 -6 6.5 6.5 -6 -55 -- Unit dB dB dB dB dB dBm dBc dB dB dB dB dB dB dB dBc/Hz dBc
Image rejection ratio IMRR
Normalized at the 1.023MHz level -13
4fo mode, TCXO = 16.368MHz 4fo mode, ratio of the carrier level and the reference leak level
Spurious component Sp
Note) fo mode and 4fo mode use the following power-on reset conditions. fo mode: TCXO = 18.414MHz, fLO = 1574.397MHz, IF = 1.023MHz 4fo mode: TCXO = 16.368MHz, fLO = 1571.328MHz, IF = 4.092MHz
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CXA3355AER
IF Output Signal (DATA_OUT)
(VCC1 = VCC2 = 1.8V, VCC3 = OPEN, Ta = 25C) Item DATA_OUT rise time DATA_OUT fall time Symbol DTr DTf Conditions Pin 7 (DATA_OUT) 10 to 90% Load = 1M//13pF Pin 7 (DATA_OUT) 10 to 90% Load = 1M//13pF Min. -- -- Typ. 6 4 Max. -- -- Unit ns ns
ENABLE Signal
(VCC1 = 1.8 0.2V, VCC1 VCC2 3.3V, 2.7V VCC3 3.3V, Ta = 25C) Item Input voltage high level Input voltage low level Symbol EVIH EVIL Conditions Pin 43 (ENABLE) input voltage high level threshold voltage Pin 43 (ENABLE) input voltage low level threshold voltage Min. 1.2 -0.1 Typ. -- -- Max. VCC2 + 0.2 0.2 Unit V V
Power-on Reset Function
(VCC1 = 1.8 0.2V, VCC1 VCC2 3.3V, 2.7V VCC3 3.3V, Ta = 25C) Item Allowable rise time Symbol MTr Conditions ENABLE and power supply (VCC1, VCC2) rise time for the power-on reset function to operate. Note: Use an ENABLE and power supply (VCC1, VCC2) rise time of 100ms or less. Min. -- Typ. -- Max. 100 Unit ms
TCXO
(VCC1 = VCC2 = 1.8V, VCC3 = OPEN, Ta = 25C) Item Input level CLK_OUT rise time CLK_OUT fall time Symbol Vtcxo CTr CTf Conditions Input level to Pin 14 (TCXO) Pin 13 (CLK_OUT) 10 to 90% Load = 1M//13pF Pin 13 (CLK_OUT) 10 to 90% Load = 1M//13pF Min. 0.2 -- -- Typ. 0.6 6 4 Max. 1.2 -- -- Unit Vp-p ns ns
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CXA3355AER
Threshold Voltage Value
(VCC1 = 1.8 0.2V, VCC1 VCC2 3.3V, 2.7V VCC3 3.3V, Ta = 25C) Item Logic input voltage high level Logic input voltage low level Symbol VIH Conditions Logic input pins = Pin 10 (DATA), Pin 11 (CLK), Pin 12 (LT) Logic input pins = Pin 10 (DATA), Pin 11 (CLK), Pin 12 (LT) Logic output pin = Pin 2 (DIAG) VOH Logic output pins = Pin 7 (DATA_OUT), Pin 13 (CLK_OUT) Logic output pins = Pin 7 (DATA_OUT), Pin 13 (CLK_OUT) Min. VCC2 - 0.2 -0.1 VCC3 - 0.2 VCC2 - 0.2 0 Typ. -- Max. VCC2 + 0.2 0.2 VCC3 VCC2 0.2 Unit V
VIL
-- -- -- --
V V V V
Logic output voltage high level Logic output voltage low level
VOL
Threshold Voltage Value (Antenna Sense)
(VCC1 = VCC2 = 1.8V, VCC3 = 3V, Ta = 25C) Item Threshold voltage 1 Symbol Vs1 Conditions Threshold voltage at which connection of the prescribed load is detected from the open status Threshold voltage for switching to the short status from the prescribed load connected status Min. 10 Typ. 30 Max. 60 Unit mV
Threshold voltage 2
Vs2
140
170
200
mV
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CXA3355AER
Electrical Characteristics Measurement Circuit
RF_IN 100p 12n 3.3p 12p 33 GND (RF) 32 GND (RF) 31 RF_INP 30 RF_INN 29 GND 28 VCC1 (LNA) 27 LNA_OUT 26 GND 25 GND 24 LNA_IN 23 GND (LNA) GND (LNA) 22 GND (LNA) 21 0.1 36 TESTINP TESTIN Buffer 37 TESTINN C_VCO 19 VCO_I 20 0.1 18n 3p 3.9n 1p LNA_OUT VCC1 (LNA) LNA_IN 50 matching condition 2.7p 4.7n 12p
10p VCC1 (RF) 34 VCC1 (RF)
35 VCC1 (RF)
38 TESTOUTP TESTOUT Buffer VCC1 (IF) 0.1 1n 41 GND (IF) 33k 42 R_EXT1 VCC2 (IF) 39 TESTOUTN
GND 18 24k 100p LPF 17 8p VCC1 (PLL)
40 VCC1 (IF)
VCC1 (PLL) 16
VCC1 (PLL) 10p
GND (PLL) 15 10n TCXO 14 TCXO input level: 0.2 to 1.2Vp-p
43 ENABLE VCC3 (ANT) GND (ANT) DATA_OUT 39k 44 R_EXT2 ASENS AILIM DIAG
CLK_OUT 13
CLK_OUT
VCC2 (IF)
GND (IF)
LT 12 DATA CLK 11
C_EXT
1
2
3
4
5 18n
6
7
8
9
10
ENABLE pin VCC2 (IF): Active mode GND: Power save mode
DIAG
DATA_OUT 1n VCC2 (IF)
Bus Control
ANT
* The RF block bypass capacitors should have excellent high frequency characteristics. * Use parts with a tolerance of 1% for the following resistor elements. Other parts should have a tolerance of 5%. Pin 17 (LPF) Pin 42 (R_EXT1) Pin 44 (R_EXT2)
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CXA3355AER
Measurement Methods
Note) The measurement methods in 4fo mode (TCXO = 16.368MHz, IF = 4.092MHz) are described below.
1) Total Gain
Input: LNA_IN Output: TESTOUTP (Pin 38), TESTOUTN (Pin 39) ... [Pins 38 and 39 are differential output.] Serial data setting: Test output block "4" (IF AMP2 output block) ... See page 20. Monitor method: (1) Perform differential - single conversion using an external buffer circuit and measure the output level. ... [Sony recommended method] (2) Measure Pins 38 and 39 with a differential probe. * Total Gain: Output level [dBm] - SG input level to LNA_IN [dBm]
Microwave coaxial cable
Signal Generator freq. = 1575.42MHz 50 AMP. = -120dBm
Evaluation Board
LNA_IN
OPEN
VCC1 (PLL) VCC1 (LNA) VCC1 (RF) VCC1 (IF) TCXO VCC2 (IF) IC VCC3 (ANT) TESTOUTP TESTOUTN External ENABLE
buffer
Microwave coaxial cable Signal Generator
50
freq. = 16.368MHz AMP. = 0dBm
GND VCC = 1.8V All GND pins
TESTOUT Spectrum Analyzer Center freq. = 4.092MHz SPAN = 10kHz 50 RBW = 100Hz VBW = 100Hz
Microwave coaxial cable
2) LNA NF
Input: LNA_IN Output: LNA_OUT * Compensate for the evaluation board and coaxial cable loss, and measure the NF value at the IC end. [Sony recommended measuring instruments] Noise source: Agilent 346A NF meter: Agilent N8973A
Microwave coaxial cable
NF meter freq. = 1575.42MHz BW = 2MHz
Microwave coaxial cable
LNA_OUT
Noise Source LNA_IN
Evaluation Board
VCC1 (PLL) VCC1 (LNA) VCC1 (RF) VCC1 (IF) VCC2 (IF) VCC3 (ANT) ENABLE GND VCC = 1.8V All GND pins
IC
TCXO
Microwave coaxial cable Signal Generator
OPEN
50
freq. = 16.368MHz AMP. = 0dBm
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CXA3355AER
3) Total NF
Input: LNA_IN Output: TESTOUTP (Pin 38), TESTOUTN (Pin 39) ... [Pins 38 and 39 are differential output.] Serial data setting: Test output block "3" (IF filter output block) ... See page 20. Monitor method: (1) Perform differential - single conversion using an external buffer circuit and measure the output level. ... [Sony recommended method] (2) Measure Pins 38 and 39 with a differential probe. * Total NF: Calculate NF from the noise power ratio when the DC 28V applied to the noise source is switched on and off. Use the 346A made by Agilent as the noise source for measurement.
Noise Source DC 28V ON/OFF
Evaluation Board
LNA_IN
OPEN
VCC1 (PLL) VCC1 (LNA) VCC1 (RF) Microwave coaxial cable Signal Generator VCC1 (IF) TCXO VCC2 (IF) IC freq. = 16.368MHz VCC3 (ANT) 50 AMP. = 0dBm TESTOUTP TESTOUTN External ENABLE
buffer
GND VCC = 1.8V All GND pins
TESTOUT Spectrum Analyzer Center freq. = 4.092MHz SPAN = 10kHz 50 RBW = 100Hz VBW = 100Hz
Microwave coaxial cable
NF calculation formula Y = NON/NOFF NF = 10 log (ENR/(Y - 1)) NON: Noise power when the DC 28V is on. NOFF: Noise power when the DC 28V is off. ENR: Excess Noise Ratio
4) P-1dB Input
Input: LNA_IN Output: TESTOUTP (Pin 38), TESTOUTN (Pin 39) ... [Pins 38 and 39 are differential output.] Serial data setting: Test output block "4" (IF AMP2 output block) ... See page 20. Monitor method: (1) Perform differential - single conversion using an external buffer circuit and measure the output level. ... [Sony recommended method] (2) Measure Pins 38 and 39 with a differential probe. * P-1dB Input: Input level [dBm] at the point when the response drops by 1dB from the desired signal straight line extension.
Microwave coaxial cable
Signal Generator freq. = 1575.42MHz 50 AMP. = -120 to -90dBm
Evaluation Board
LNA_IN
OPEN
VCC1 (PLL) VCC1 (LNA) VCC1 (RF) Microwave coaxial cable Signal Generator VCC1 (IF) TCXO VCC2 (IF) IC freq. = 16.368MHz VCC3 (ANT) 50 AMP. = 0dBm TESTOUTP TESTOUTN External ENABLE
buffer
GND VCC = 1.8V All GND pins
TESTOUT Spectrum Analyzer Center freq. = 4.092MHz SPAN = 10kHz 50 RBW = 100Hz VBW = 100Hz
Microwave coaxial cable
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CXA3355AER
5) Image Rejection Ratio
Input: LNA_IN Output: TESTOUTP (Pin 38), TESTOUTN (Pin 39) ... [Pins 38 and 39 are differential output.] Serial data setting: Test output block "2" (Adder output block) ... See page 20. Monitor method: (1) Perform differential - single conversion using an external buffer circuit and measure the output level. ... [Sony recommended method] (2) Measure Pins 38 and 39 with a differential probe. * IMRR (detuning frequency 4MHz): Image wave output level (at 1575.42MHz input) [dBm] - Desired wave output level (at 1567.236MHz input) [dBm]
Signal Generator freq. = 1575.42MHz (Desired wave) 1567.236MHz (Image wave) 50 AMP. = -75dBm
Microwave coaxial cable
Evaluation Board
LNA_IN
OPEN
VCC1 (PLL) VCC1 (LNA) VCC1 (RF) Microwave coaxial cable Signal Generator VCC1 (IF) TCXO VCC2 (IF) IC freq. = 16.368MHz VCC3 (ANT) 50 AMP. = 0dBm TESTOUTP TESTOUTN External ENABLE
buffer
GND VCC = 1.8V All GND pins
TESTOUT Spectrum Analyzer Center freq. = 4.092MHz SPAN = 10kHz 50 RBW = 100Hz VBW = 100Hz
Microwave coaxial cable
6) Filter Response
Input: LNA_IN Output: TESTOUTP (Pin 38), TESTOUTN (Pin 39) ... [Pins 38 and 39 are differential output.] Serial data setting: Test output block "3" (IF filter output block) ... See page 20. Monitor method: (1) Perform differential - single conversion using an external buffer circuit and measure the output level. ... [Sony recommended method] (2) Measure Pins 38 and 39 with a differential probe. * Filter Response: Vary the input frequency to LNA_IN and measure the output level. Normalize fo (4fo) to the reference (0dB).
Signal Generator freq. = 1571.388MHz to 1675.42MHz 50 AMP. = -75dBm
Microwave coaxial cable
Evaluation Board
LNA_IN
OPEN
VCC1 (PLL) VCC1 (LNA) VCC1 (RF) Microwave coaxial cable Signal Generator VCC1 (IF) TCXO VCC2 (IF) IC freq. = 16.368MHz VCC3 (ANT) 50 AMP. = 0dBm TESTOUTP TESTOUTN External ENABLE
buffer
GND VCC = 1.8V All GND pins
TESTOUT Spectrum Analyzer Center freq. = 150kHz to 100MHz SPAN = 10kHz 50 RBW = 100Hz VBW = 100Hz
Microwave coaxial cable
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CXA3355AER
7) C/N
Input: LNA_IN Output: TESTOUTP (Pin 38), TESTOUTN (Pin 39) ... [Pins 38 and 39 are differential output.] Serial data setting: Test output block "1I" (Ich mixer output block) ... See page 20. Monitor method: (1) Perform differential - single conversion using an external buffer circuit and measure the output level. ... [Sony recommended method] (2) Measure Pins 38 and 39 with a differential probe. * C/N: Carrier + 100kHz noise level - Carrier level [dBc/Hz]
Microwave coaxial cable
Signal Generator freq. = 1575.42MHz 50 AMP. = -60dBm
Evaluation Board
LNA_IN
OPEN
VCC1 (PLL) VCC1 (LNA) VCC1 (RF) Microwave coaxial cable Signal Generator VCC1 (IF) TCXO VCC2 (IF) IC freq. = 16.368MHz VCC3 (ANT) 50 AMP. = 0dBm TESTOUTP TESTOUTN External ENABLE
buffer
GND VCC = 1.8V All GND pins
TESTOUT Spectrum Analyzer Center freq. Microwave coaxial cable (Carrier) = 4.092MHz (Noise) = 4.192MHz 50 SPAN = 10kHz RBW = 100Hz VBW = 100Hz
8) Spurious
Input: LNA_IN Output: TESTOUTP (Pin 38), TESTOUTN (Pin 39) ... [Pins 38 and 39 are differential output.] Serial data setting: Test output block "4" (IF AMP2 output block) ... See page 20. Measure the spurious components separated by a certain frequency from the carrier. * Spurious: Each spurious output level - Carrier level [dBc]
Microwave coaxial cable
Signal Generator freq. = 1575.52MHz 50 AMP. = -120dBm
Evaluation Board
LNA_IN
OPEN
VCC1 (PLL) VCC1 (LNA) VCC1 (RF) VCC1 (IF) TCXO VCC2 (IF) IC VCC3 (ANT) TESTOUTP TESTOUTN External ENABLE
buffer
Microwave coaxial cable Signal Generator
50
freq. = 16.368MHz AMP. = 0dBm
GND VCC = 1.8V All GND pins
TESTOUT Spectrum Analyzer Center freq. = 4.092MHz SPAN = 10kHz 50 RBW = 100Hz VBW = 100Hz
Microwave coaxial cable
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CXA3355AER
9) Antenna Sense
Vary VS and measure the DIAG pin voltage. Vary VS and measure the inflow current Ib to AILIM.
Evaluation Board
VCC1 (PLL) VCC1 (LNA) VCC1 (RF) VCC1 (IF) VCC2 (IF) VCC3 (ANT) ENABLE GND AILIM IC DIAG ASENS Vs
A
V
All GND pins
VCC = 1.8V
VCC3 = 3.0V
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CXA3355AER
Initial Settings
The CXA3355AER is initialized by setting the ENABLE signal (Pin 43) from low level to high level. The timing, etc. should satisfy the conditions below. In addition, the TCXO frequency and IF frequency combinations in the table below can be obtained by setting Pin 10 (DATA), Pin 11 (CLK) and Pin 12 (LT) as shown in the table and then performing initialization. This eliminates the need for serial data setting. Pin 10 (DATA) GND VCC2 VCC2 Pin 11 (CLK) GND GND VCC2 Pin 12 (LT) GND GND GND TCXO frequency [MHz] 16.368 18.414 13 IF frequency [MHz] 4.092 1.023 0.976
1. During Power-on
Power supply, ENABLE VCC 0.9 x VCC
0.1 x VCC GND
100ms or less
The CXA3355AER is initialized by simultaneously raising the power supplies and the ENABLE signal (Pin 43) during power-on. The power supply and ENABLE signal (Pin 43) rise time should be 100ms or less. In addition, the power supplies (VCC1, VCC2) should rise simultaneously. The antenna sense circuit power supply (VCC3) should be left open except when using the antenna sense function.
2. Initialization After Power-on
Power supply VCC
GND ENABLE VCC 0.5 x VCC GND 10ms or more
After power-on, the CXA3355AER is initialized by setting the ENABLE signal (Pin 43) to low level for 10ms or more and then setting it to high level.
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CXA3355AER
Serial Data Settings
The CXA3355AER can make the PLL counter settings, perform TCXO_CLK output, select the internal IF filter, and use the test I/O circuit according to the serial data settings (3-wire bus control). The transfer bit length is 18 bits, and there are four addresses. The address is set by the A1 and A0 bits. The timing, etc. should satisfy the conditions below.
Serial Data Format
MSB A1 0 0 1 1 A0 0 1 0 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 0 0 0 D3 0 0 0 D2 0 0 0 D1 CLK 0 FIL 0 MC10 MC9 MC8 MC7 MC6 MC5 MC4 MC3 MC2 MC1 MC0 TI2 0 TI1 0 TI0 TO2 TO1 TO0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSB D0 0 TCL 0 0
SC4 SC3 SC2 SC1 SC0 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
MC (0 to 10): Main counter frequency division value setting 0: Logic input voltage low level SC (0 to 4): Swallow counter frequency division value setting 1: Logic input voltage high level RC (0 to 8): Reference counter CLK: TCXO CLK output (0: Not output, 1: Output) FIL: Internal filter selection (0: fo mode LPF, 1: 4fo mode BPF) TCL: IF block test I/O control (0: When not using the test I/O circuit, 1: When using the test I/O circuit) TI (0 to 2): IF block test input location setting TO (0 to 2): IF block test output location setting
18-bit Data Format
Invalid data D0 DATA D1 D2 D3 D4 D5 D6 Each data D7 D8 D9 D10 D11 D12 D13 D14 D15 Address data Invalid data A0 A1
CLK
LT Time Input data to all four addresses. Latch
Serial Data Interface Bus Timing (3-wire Bus Control)
tSD DATA tHD
CLK
tLOW
tHIGH
tSD = Data setup time tHD = Data hold time tLOW = Low period of CLK tHIGH = High period of CLK tSL = LT setup time tWHLT = High pulse width (LT) tHL tWHLT
LT
tWHLT 100ns tSD, tHD, tLOW, tHIGH, tHL, tWHLT 50ns
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CXA3355AER
Description of Functions
1. Test Circuit
The CXA3355AER has a test circuit for test signal I/O. The test circuit is connected between each IF block, and test I/O control can be performed by the serial data settings. The test circuit location, configuration and the serial data settings are as follows.
To each IF block 34
RF_AMP
33
32
31
30
1540fo = 1575.42MHz
35 Mixer Test input control 36 37 "1Q" 37
IF_AMP1 IF_AMP1
Mixer
36 "1I" 90
38 38 39 Test output control 39 IF Phase Shifter 40
Local
"1I": Ich mixer output block (Ich IF AMP1 input block) "1Q": Qch mixer output block (Qch IF AMP1 input block) "2": Adder output block (IF filter input block) "3": IF filter output block (IF AMP2 input block) "4": IF AMP2 output block (A/D converter input block)
41 From each IF block 42 Actual operation is differential, but only one side is shown. The inter-circuit connections are cut off during test input selection and test output selection. 43 "2" IF_AMP2 LPF HPF A/D Converter
"3"
"4"
44 1
BIAS 2 3
ANT SENSE 4 5 6 7
Test Circuit Location and Configuration
Serial Data Settings for Test Input Selection TI2 0 0 0 0 1 1 1 1 TI1 0 0 1 1 0 0 1 1 TI0 0 1 0 1 0 1 0 1 Test input block Normal operation Ich IF AMP1 input block Qch IF AMP1 input block Not used. Not used. IF filter input block IF AMP2 input block A/D converter input block Serial Data Settings for Test Output Selection TO2 0 0 0 0 1 1 1 1 TO1 0 0 1 1 0 0 1 1 TO0 0 1 0 1 0 1 0 1 Test output block Normal operation Ich mixer output block Qch mixer output block Not used. Not used. Adder output block IF filter output block IF AMP2 output block
0: Logic input voltage low level 1: Logic input voltage high level * Set the TCL register to "1" when using or to "0" when not using the test input circuit or the test output circuit. (See page 20.)
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CXA3355AER
2. Using an External Filter
When using the CXA3355AER in 4fo mode with the initial settings (see page 18) which do not require serial data setting, input and output are performed via the test circuit located between the internal IF filter and the IF AMP2 in the following stage, so an external filter is necessary. The external filter uses Pins 36 to 39. Differential I/O is performed with Pin 38 (TESTOUTP) and Pin 39 (TESTOUTN) as the internal IF filter output pins and Pin 36 (TESTINP) and Pin 37 (TESTINN) as the input pins to IF AMP2. Also, the impedance is 200 (differential) for both input and output. Note that the bias voltage is determined inside the IC, so Pins 36 and 37 should not be connected directly with Pins 38 and 39. When not using an external filter, eliminate the DC components using an approximately 10nF capacitor. The overall external filter block and the external filter configuration are shown below.
Secondary LPF Secondary HPF External filter I/O circuit IF AMP2
To the comparator LPF HPF
CXA3355AER 39 Pin 36: TESTINP Pin 37: TESTINN Pin 38: TESTOUTP Pin 39: TESTOUTN 38 37 36
Zout 200
Zin 200
External filter
Overall External Filter Block
L1 Pin 38 C2 C1 Pin 39 C3 L2 C6 C9 L4 C13 -10 C4 C5 C10 C7 C11 L5, L6 (2 series) Pin 36 10 0 L3 C8 C12 Pin 37 CXA3355AER IF Filter Response (Example of representative characteristics) Normalized at 4MHz
Response [dB]
Chip C C1 C2, C3 C4 C5, C6 C7 C8, C9, C12, C13 C10, C11
[pF] 91 300 240 91 130 680 1500
Chip L L1, L2 L3, L4 L5, L6
[H] 2.2 3.9 4.7
-20 -30 -40 -50 -60 -70 0 1 Internal filter Internal filter + External filter 2 3 4 5 6 7 8 9 10
Detuning frequency [MHz]
External Filter Configuration
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CXA3355AER
Description of Operation
Overview of Operation
This IC down-converts the GPS (Global Positioning System) frequency of 1.57542GHz to fo (fo: 1.023MHz) or 4fo (4fo: 4.092MHz). The internal configuration is divided into the analog block, consisting of the amplifier, mixer and filters, and the digital block (including the comparator block and the control block), which forms the PLL. The analog block converts the frequency and amplifies the signal with the amplifier and the mixer, and eliminates undesired components with the filters. The digital block can switch the PLL frequency division ratio in order to down convert the output signal to fo or 4fo.
1. LNA
The GPS signal that passes through the antenna is input to Pin 24 via a matching circuit as shown in the figure below. The input signal is amplified by the LNA, and then output from Pin 27. Always use matching circuits for the LNA input pin (Pin 24) and the LNA output pin (Pin 27), and match at 1.57542GHz.
2. RF Amplifier, RF Mixer, IF Phase Shifter and Adder
The signal amplified by the LNA passes through the SAW filter, and is then input to Pin 30 via a matching circuit. The input signal is amplified by the RF amplifier, and then down-converted by the RF mixer to the fo (1.023MHz) or 4fo (4.092MHz) I and Q components. The IF signal down-converted to the I and Q components has the image component eliminated by the phase shifter and the adder, and is then input to the IF filter. Always use a matching circuit for the RF amplifier input pin (Pin 30), and match at 1.57542GHz.
Matching Circuit
24
LNA
Matching Circuit
27 fo or 4fo
SAW
Matching Circuit
30
1540fo Phase Shifter To the IF filter Adder
31 0
90
90
fo: 1.023MHz
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CXA3355AER
3. IF Filter
The IF signal that passed through the adder has the undesired components outside the band eliminated by the IF filter. In fo mode the signal passes through only the LPF and is input to IF AMP2. In 4fo mode the signal passes through the LPF and then the HPF and is input to IF AMP2. Note that fo mode and 4fo mode can be switched by the serial data setting. Set the serial data setting register FIL to "0" for fo mode (LPF) or to "1" for 4fo mode (BPF). In addition, an external filter can also be connected to this IC using Pins 36 to 39. (See page 21.)
From the adder LPF
To IF AMP2
HPF
4. IF AMP2 and A/D Converter
The signal that passed through the IF filter is amplified by IF AMP2, converted to a binary signal by the A/D converter, and then output from the DATA output pin (Pin 7). The A/D converter performs sampling at the TCXO CLK. In addition, the A/D converter output voltage high level is VCC2 (1.6 to 3.3V), so a wide range of interfaces can be supported.
5. TCXO (Pin 14)
Input the signal from the external oscillator to Pin 14 via a capacitor as the reference signal. Input frequencies from 10MHz to 26MHz are supported. The input signal level from the external oscillator should be 1.2Vp-p or less (0.6Vp-p typ., 0.2Vp-p min.). This is also the same in power save mode. However, using the typical level of 0.6Vp-p is recommended from the viewpoint of reducing harmful waves to the receive block, etc.
6. TCXO CLK Output (Pin 13)
This IC can output TCXO CLK from Pin 13 according to the serial data setting. The output voltage high level is VCC2 (1.6 to 3.3V), so a wide range of interfaces can be supported. Set the serial data setting register CLK to "0" when not using TCXO CLK, or to "1" when using TCXO CLK. (See page 19.)
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CXA3355AER
7. PLL/VCO
The PLL is comprised by a VCO, frequency divider and phase/frequency comparator as shown in the figure below, and incorporates an inductor, varactor and all other necessary components. The loop filter is externally connected. Use components that satisfy the required characteristics. Serial data setting is unnecessary when this IC is used with the typical TCXO and IF combinations set by the initial settings shown in page 18. When making serial data settings, set counter frequency division values that satisfy the following equations. fVCO = (M x N + A) x (fTCXO x 2)/R (fTCXO x 2)/R > 800kHz N 3, R 3 fVCO: VCO oscillation frequency, fTCXO: TCXO frequency MC data = N, SC data = A, RC data = R, DMPS data = M = 24 (fixed)
To the RF phase shifter Frequency division ratio (M x N) + A
DMPS VCO 1/M, 1/(M + 1) M = 24
MC 1/N
Loop filter SC PFD 1/A CP 17
VCC1
RC x2 1/R
14
TCXO (10MHz to 26MHz)
8. ENABLE (Pin 43)
Active mode and power save mode can be switched according to the level. High (V_IH: 1.2V min.): Active mode Low (V_IL: 0.2V max.): Power save mode
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CXA3355AER
9. Antenna Sense
The power supply lines are separated internally, so antenna sense operation at the supply voltage (VCC3) of 3.0 0.3V is recommended. Note that the antenna sense function does not operate independently, so voltage should also be applied to the other power supply pins (VCC1, VCC2) for use in active mode. In addition, leave the power supply pin (VCC3) open when not using the antenna sense function. The antenna sense function checks whether an antenna is connected. Pin 2 (DIAG) outputs high voltage when an antenna is not connected, or low voltage when an antenna is connected. A current limiting circuit is provided as a countermeasure against short circuits. The DIAG pin voltage switching point is as shown in the table below. V1, V2, V3 and Ib in the table below are as follows. V1: 10 to 60mV Threshold voltage at which connection of the prescribed load is detected from the open status V2: 140 to 200mV Threshold voltage for switching to the short status from the prescribed load connected status. V3: 250mV Current limiting threshold voltage. Ib: 1.7 to 2.1mA Base current in the normal connection status.
MODE Vs < V1 V1 < Vs < V2 V2 < Vs
Connection status Open Normal connection Short
DIAG voltage High Low High
DIAG [V] V1 I1 = 1.9mA I1 (Typ.) Ib [mA] V3 Vs
V2
Vs
VCC3 (ANT) R3
VCC3 (ANT) Vs ASENS 1 A1 3 AILIM V2 V1
CXA3355AER
2 DIAG
VA A2
V3 Ib A3 VD
Antenna Sense Block Circuit
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CXA3355AER
Application Circuit
SAW Filter VCC1 VCC1 VCC1 VCC1 VCC2 (LNA) (RF) (IF) (PLL) (IF)
VCC1 (LNA) 100p 12n 3.3p 12p 33 GND (RF) 32 GND (RF) 31 RF_INP 30 RF_INN 29 GND 28 VCC1 (LNA) 27 LNA_OUT 26 GND 25 GND 24 LNA_IN 23 GND (LNA) 18n 3p 3.9n 1p 2.7p 4.7n 12p 1
0.1
VCC = 1.8V
10p VCC1 (RF) 34 VCC1 (RF)
GND (LNA) 22
35 VCC1 (RF)
GND (LNA) 21 0.1
36 TESTINP
VCO_I 20 0.1
37 TESTINN 10n 10n 38 TESTOUTP
C_VCO 19
GND 18 24k 100p
39 TESTOUTN
LPF 17 8p
VCC1 (PLL)
VCC1 (IF) 1n
40 VCC1 (IF)
VCC1 (PLL) 16
VCC1 (PLL) 10p
41 GND (IF) 33k 42 R_EXT1 VCC2 (IF)
GND (PLL) 15 10n TCXO 14 TCXO input level: 0.2 to 1.2Vp-p
43 ENABLE DATA_OUT VCC3 (ANT) GND (ANT) 39k 44 R_EXT2 ASENS AILIM DIAG
CLK_OUT 13
VCC2 (IF)
GND (IF)
LT 12 DATA CLK 11
C_EXT
1
2
3
4
5 18n
6
7
8
9
10
ENABLE pin Vcc2 (IF): Active mode GND: Power save mode
DATA_OUT 1n VCC2 (IF)
Number of parts * Resistors: 3pcs * Capacitors: 20pcs * Inductors: 5pcs * SAW filter: 1pcs (Excluding the antenna sense circuit)
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
* This diagram shows the application circuit when the initial settings are made for 4fo mode. (See page 18.) * The RF block bypass capacitors should have excellent high frequency characteristics. * Use parts with a tolerance of 1% for the following resistor elements. Other parts should have a tolerance of 5%. Pin 17 (LPF) Pin 42 (R_EXT1) Pin 44 (R_EXT2)
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CXA3355AER
Supplement Materials (Example of representative characteristics)
Graph 1. ICC
20 10 5 IF AMP2 output level [dBm] 0 -5 -10 -15 -20 -25 -30 -35 VCC1 = VCC2 = 1.8V VCC3 = Open Temp = 25C
Graph 2. Total Gain
15 Icc [mA] 10 VCC1 = VCC2 = 1.8V VCC3 = Open Temp = 25C fo 4fo 5 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 Vcc [V]
-40 -135 -130 -125 -120 -115 -110 -105 -100 -95 -90 -85 LNA_IN input level [dBm]
Graph 3. Total NF
10 -20 -25 8 -30 -35 Total NF [dB] fo mode 4fo mode 4 VCC1 = VCC2 = 1.8V VCC3 = Open Temp = 25C IMRR [dBc] 6 -40 -45 -50 2 -55 -60 4 5 -65 0.1
Graph 4. Image Rejection Ratio
VCC1 = VCC2 = 1.8V VCC3 = Open Temp = 25C
0 0 1 2 3 IF frequency [MHz]
1 Detuning frequency [MHz]
10
Graph 5. Filter Response (Normalized at 1.023MHz)
10 5 0 Filter response [dB] -5 -10 -15 -20 -25 -30 -35 0.1 1 10 100 VCC1 = VCC2 = 1.8V VCC3 = Open Temp = 25C fo Upper spec (fo) Lower spec (fo)
Graph 6. Filter Response (Normalized at 4.092MHz)
10 5 0 Filter response [dB] -5 -10 -15 -20 -25 -30 -35 0.1 1 10 100 VCC1 = VCC2 = 1.8V VCC3 = Open Temp = 25C 4fo Upper spec (4fo) Lower spec (4fo)
Detuning frequency [MHz]
Detuning frequency [MHz]
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CXA3355AER
Graph 7. Local Leak
-60 VCC1 = VCC2 = 1.8V VCC3 = Open Temp = 25C C/N [dBc/Hz] -40
Graph 8. C/N
-65 Local leak [dBm]
-50
VCC1 = VCC2 = 1.8V VCC3 = Open Temp = 25C
-60
-70
-70
-75
-80 -80
-90
-85 Evaluation board LNA_IN pin
-100 0.01
0.1
1
Frequency difference from the carrier [MHz]
Graph 9a. Antenna Sense (VS vs. DIAG)
4.0 3.5 2.0 3.0 2.5 DIAG [V] 2.0 1.5 1.0 0.5 0 0 0.1 0.2 0.3 Vs [V] 0.4 0.5 0.6 VCC1 = VCC2 = 1.8V VCC3 = 3V Temp = 25C Ib [mA] 1.5 2.5
Graph 9b. Antenna Sense (VS vs. Ib)
VCC1 = VCC2 = 1.8V VCC3 = 3V Temp = 25C
Ib 1.0
DIAG Upper Spec Lower Spec
0.5
0 0 0.1 0.2 0.3 Vs [V] 0.4 0.5 0.6
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CXA3355AER
Package Outline
(Unit: mm)
44PIN VQFN (PLASTIC)
5.1 33 34 23 22
0.8 0.1
3.5
0.
22
C
4 - R0.3
A
B
44 1 PIN 1 INDEX
12 0.4 Thermal Die Pad
X4 S
0.05 M S A - B C
0.1 S A - B C
Solder Plating 0.4
MAX0.02
S
0.135 0.14
+ 0.09 - 0.03
0.175
+ 0.09 0.31 - 0.03
0.05
TERMINAL SECTION
SONY CODE JEITA CODE JEDEC CODE AP-4000-44010S
VQFN-44P-03
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING LEAD TREATMENT LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.06g
Rev.2
- 29 -
Sony Corporation
0.55 0.1
S
0.4 0.1

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