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PRELIMINARY
Z89319 CPS5TEL0800
PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
Z89319
DIGITAL TELEVISION CONTROLLER IN-CIRCUIT EMULATOR (ICE) DEVICE
FEATURES
s Part Number
Z89319
ROM (Word)
0
RAM (Word)
0
Speed (MHz)
12
s s s s s
Direct Closed Caption Decoding TV Tuner Serial Interface Customized Character Set Character Control Mode Directly Controlled Receiver Functions
s s s s
124-Pin Grid Array (PGA) Package 4.5- to 5.5-Volt Operating Range Z89C00 RISC Processor Core 0C to +70C Temperature Range
GENERAL DESCRIPTION
The Z89319 is a ROMless ICE chip version of the Z89300 family of Zilog's Digital Television Controllers designed for use in emulators and development boards to provide complete audio and video control of television receivers, video recorders, and advanced on-screen display facilities. The powerful Z89C00 RISC processor core allows users to control on-board peripheral functions and registers using the standard processor instruction set. In closed caption mode, text can be decoded directly from the composite video signal and displayed on the screen with assistance from the processor's digital signal processing capabilities. The character representation in this mode allows for a simple attribute control through the insertion of control characters. The character control mode provides access to the full set of attribute controls. The modification of attributes is allowed on a character-by-character basis. The insertion of control characters permits direction of other character attributes. Display attributes, including underlining, italics, blinking, eight foreground/background colors, character position offset delay, and background transparency, are made possible through a fully customized 512 character set, formatted in two 256 character banks. Serial interfacing with the television tuner is provided through the tuner serial port. Digital channel tuning adjustments may be accessed through the industrystandard I2C port. Additional hardware provides the capability to display two to three times normal size characters. The smoothing logic contained in the on-screen display circuit improves the appearance of larger fonts. Special circuitry can be activated to improve the visibiity of text by adding a rightsided shadow effect to the characters. Receiver functions such as color and volume can be directly controlled by six 8-bit pulse width modulated ports.
Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
CP95TEL0800 (6/95)
1
PRELIMINARY
Z89319 CP95TEL0800
GENERAL DESCRIPTION (Continued)
Capture IRIN ADC ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 Port 0 Port 00 Port 01 Port 02 Port 03 Port 04 Port 05 Port 06 Port 07 Port 08 Port 09 Port 0A Port 0B Port 0C Port 0D Port 0E Port 0F Control XTAL1 XTAL2 LPF HSYNC HSYNC2 VSYNC /Reset CPU V3(B) RAM 1K x 16
Address ROM Addr Data
PWM PWM1 PWM2 PWM3 PWM4 PWM5 PWM6
CVI Port 17 Port 00 Port 05 Port 04
Port1 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Port 16 Port 17 Port 18
I2C SCL/MSCL2 SCD/MSCD2 MSCL1 MSCD1 OSD V1(R) V2(G)
Port 01/11 Port 02/12
PWM6
Register Addr/Data
ROM 32K x 16
ROM Data
Functional Block Diagram
2
PRELIMINARY
Z89319 CPS5TEL0800
ADDRESS13 P07/CSYNC
ADDRESS14
P0C INT_BUS15 IRIN
INT_BUS14
P16/SCLK INT_BUS13 P15/B<1>
P13/G<1> P18/G<0> VCC P08/R<1> INT_BUS12
P06/CNTR
P10/R<0> INT_BUS11 PWM6 INT_BUS10
P14/B<0> GND
P0D VCC
P03 P01 VCC GND ADDRESS12 ADDRESS11 P02 ADDRESS10 ADDRESS9 ADDRESS8 ADDRESS7 ADDRESS6 CVI/ADC0 ADDRESS5 ADDRESS4 VCC GND ADDRESS3 LPF ADDRESS2 ADDRESS1 ADDRESS0 IE R/W ANGNDF SYS_CLK EA0 EA1 EA2 ADC5 P04/ADC4
P0A P0B
P09 P19
PWM4 PWM3
PWM5
GND PWM2 VCC DATA0 DATA1 DATA2 PWM1 DATA3 DATA4 DATA5 DATA6 SINGLE_STEP ANGNDX STOPWDT DATA7 DATA8 DATA9 _ROMLESS VCC/VDD _PABUS DATA12 DATA13 DATA14 DATA10 GND DATA11 DATA15 GND INT_BUS9 XTAL2 XTAL1
Z89319 124-Pin PGA
P001/ADC2
P05/ADC3 GND
INT_BUS1 ANGND
INT_BUS5 P11/I2MSC2
INT_BUS0 P17/ADC1
124-Pin PGA Configuration
VSYNC P12/I2MSD2
INT_BUS4
INT_BUS8 /RESET
INT_BUS2
ANVCC INT_BUS3 P0F/HB V3(B) VCC
INT_BUS6 P0E
INT_BUS7 I2MSD1 VCC
I2MSC1
GND BLANK HSYNC
V2(G) V1(R)
3
PRELIMINARY
Z89319 CP95TEL0800
PIN DESCRIPTION
N M L K J H
Z89319
G F E D C B A
13 12 11 10 9
8
7
6
5
4
3
2
1
124-Pin PGA Configuration
4
PRELIMINARY
Z89319 CPS5TEL0800
V1, V2, V3 ANALOG OUTPUT Specifications VCC = 5.25 V
VCC = 5.25 V Output Voltage Condition Bit = 11 Bit = 10 Bit = 01 Bit = 00 70% of DC Level, 10pf Load Limit 4.30 V 3.10 V 1.90 V 0V < 50 ns 0.3 V 0.25 V 0.20 V 0.75 V
Setting Time
V1, V2, V3 ANALOG OUTPUT Specifications VCC = 4.75 V
VCC = 4.75 V Output Voltage Condition Bit = 11 Bit = 10 Bit = 01 Bit = 00 70% of DC Level, 10pf Load Limit 3.90 V 2.80 V 1.70 V 0V < 50 ns 0.30 V 0.25 V 0.20 V 0.65 V
Setting Time
Z893XX 10 Mohm 68pF 32.768k XTAL1
XTAL2 27k
560pF
32K Oscillator Recommended Circuit
5
PRELIMINARY
Z89319 CP95TEL0800
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VID VIA VO IOH IOH IOL IOL TA TA Parameter Power Supply Voltage Input Voltage Input Voltage Output Voltage Output Current High Output Current High Output Current Low Output Current Low Operating Temperature Storage Temperature Min 0 -0.3 -0.3 -0.3 Max 7 VCC +0.3 VCC +0.3 VCC +0.3 -10/-1a -100 20/1b 200 70 150 Units V V V V mA mA mA mA C C Conditions Digital Inputs Analog Inputs (A/D0...A/D4) All Push-Pull Digital Output One Pin All Pins One Pin All Pins
0 -65
Notes: a) 1 mA max. when output pad impedance is 600 . b) 1 mA max. when output pad impedance is 600 .
DC CHARACTERISTICS TA = 0C to + 70C; VCC = 4.5 V to + 5.5 V; FOSC = 32.768 KHz
Symbol VIL VIH VOL VOH VXL VXH VHY IIR IIL ICC ICC1 ICC2 Parameter Input Voltage Low Input Voltage High Output Voltage Low Output Voltage High Input Voltage XTAL1 Low Input Voltage XTAL1 High Schmitt Hysteresis Reset Input Current Input Leakage Supply Current Supply Current Supply Current Min 0 0.6 VCC Max 0.2 VCC VCC 0.4 VCC -0.9 0.3 VCC VCC -2.0 3.0 -3.0 0.75 150 3.0 100 300 40 Typical 0.4 3.6 0.16 4.75 1.0 3.5 0.5 90 0.01 60 100 5 Units V V V V V V V A A mA A A @ IOL = 1 mA @ IOL = 0.75 mA External Clock Generator Driven On XTAL1 Input Pin VRL = 0 V @ 0 V and VCC Sleep Mode @ 32 KHz Stop Mode Conditions
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PRELIMINARY
Z89319 CPS5TEL0800
AC CHARACTERISTICS TA = 0C to + 70C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 KHz
Symbol TPC TRC,TFC TDPOR Parameter Input Clock Period Clock Input Rise and Fall Power On Reset Delay Min 16 0.8 Max 100 Typical 32 12 1.2 Units S S s Depends on Crystal Note
AC CHARACTERISTICS* TA = 0C to + 70C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 KHz
Symbol TWRES TDHS TDVS TDES TDOS TWHVS Parameter Power-On Reset Min. Width H_Sync Incoming Signal Width V_Sync Incoming Signal Width Time Delay Between Leading Edge of V_Sync and H_Sync in Even Field Time Delay Between Leading Edge of H_Sync in Odd Field H_Sync/V_Sync Edge Width Min 5.5 0.15 -12 20 Max 5TPC 12.5 1.5 +12 44 2.0 Typical 11 1.0 0 32 0.5 Units S S mS S S S
Notes: All timing of the I2C bus interface are defined by related specifications of the I2C bus interface.
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