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| 1021BV33 WCFS1016V1C 64K x 16 Static RAM Features * 3.3V operation (3.0V-3.6V) * High speed -- tAA = 12 ns * CMOS for optimum speed/power * Automatic power-down when deselected * Independent control of upper and lower bits * Available in 400-mil SOJ through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The WCFS1016V1C is available in 400-mil-wide SOJ packages. Functional Description The WCFS1016V1C is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 Logic Block Diagram DATA IN DRIVERS Pin Configurations SOJ Top View A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A7 A6 A5 A4 A3 A2 A1 A0 64K x 16 RAM Array 512 X 2048 I/O1 - I/O8 I/O9 - I/O16 COLUMN DECODER BHE WE CE OE BLE A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC ROW DECODER Selection Guide WCFS1016V1C-12 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) 12 150 5 A8 A9 A10 A11 A12 A13 A14 A15 SENSE AMPS Revised April 19, 2002 WCFS1016V1C Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND [1] Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range Range Commercial Ambient Temperature[2] 0C to +70C VCC 3.3V 10% .... -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[1] ......................................-0.5V to VCC+0.5V DC Input Voltage[1]...................................-0.5V to VCC+0.5V Electrical Characteristics Over the Operating Range Test Conditions Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current --TTL Inputs Automatic CE Power-Down Current --CMOS Inputs GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f=0 VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.3 -1 -1 WCFS1016V1C 12ns Min. 2.4 Max. Unit V 0.4 VCC+ 0.3V 0.8 +1 +1 150 V V V A A mA ISB1 40 mA ISB2 5 mA Capacitance[3] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz Max. 6 8 Unit pF pF Note: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "instant on" case temperature. 3. Tested initially and after any design or process changes that may affect these parameters. Page 2 of 9 WCFS1016V1C AC Test Loads and Waveforms 3.3V OUTPUT 30 pF R 317 R 317 3.3V OUTPUT R2 351 5 pF INCLUDING JIG AND SCOPE R2 351 GND Rise Time: 1 V/ns 3.0V 10% ALL INPUT PULSES 90% 90% 10% INCLUDING JIG AND SCOPE (a) (b) Fall Time: 1 V/ns 167 OUTPUT Equivalent to: THEVENIN EQUIVALENT 30 pF 1.73V Page 3 of 9 WCFS1016V1C Switching Characteristics[4] Over the Operating Range WCFS1016V1C 12ns Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE CYCLE[7] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[6] WE LOW to High Z[5, 6] 8 Byte Enable to End of Write 12 9 8 0 0 8 6 0 3 6 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[5, 6] CE LOW to Low Z[6] Z[5, 6] 0 12 6 0 6 3 6 CE HIGH to High 0 6 3 12 6 12 12 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Unit CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z Data Retention Characteristics Over the Operating Range Parameter VDR tCDR[9] tR[10] Description VCC for Data Retention Chip Deselect to Data Retention Time VCC = VDR = 2.0V, CE > VCC - 0.3V, Operation Recovery Time VIN > VCC - 0.3V or VIN < 0.3V Conditions[8] Min. 2.0 0 tRC Max. Unit V ns ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. No input may exceed VCC + 0.5V. 9. Tested initially and after any design or process changes that may affect these parameters. 10. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds. Page 4 of 9 WCFS1016V1C Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR Switching Waveforms Read Cycle No. 1 [11, 12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled) ADDRESS [12, 13] tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% IISB SB IICC CC tHZOE HIGH IMPEDANCE DATA OUT Notes: 11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Page 5 of 9 WCFS1016V1C Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled) [14, 15] tWC ADDRESS CE tSA tSCE tAW tPWE WE tBW BHE, BLE tSD DATA I/O tHD tHA Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tPWE WE tSCE CE tSD DATA I/O tHD tHA Notes: 14. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Page 6 of 9 WCFS1016V1C Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, LOW) tWC ADDRESS CE tSCE tAW tSA tPWE tHA WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD Truth Table CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H I/O1-I/O8 High Z Data Out Data Out High Z Data In Data In High Z High Z High Z I/O9-I/O16 High Z Data Out High Z Data Out Data In High Z Data In High Z High Z Power-Down Read - All bits Read - Lower bits only Read - Upper bits only Write - All bits Write - Lower bits only Write - Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Page 7 of 9 WCFS1016V1C Ordering Information Speed (ns) 12 Ordering Code WCFS1016V1C-JC12 Package Name J Package Type 44-Lead (400-Mil) Molded SOJ Operating Range Commercial Package Diagrams 44-Lead (400-Mil) Molded SOJ J Page 8 of 9 WCFS1016V1C Document Title: WCFS1016V1C 64K x 16 Static RAM REV. ** Issue Date 4/19/02 Orig. of Change XFL Description of Change NEW DATASHEET Page 9 of 9 |
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