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W83L197R-16
2-CHIP 100MHZ CLOCK FOR BX NOTEBOOK
1.0 GENERAL DESCRIPTION
The W83L197R-16 is a Clock Synthesizer which provides all clocks required for high-speed RISC or CISC microprocessor. Four different frequency of CPU, and PCI clocks are externally selectable with smooth transitions. The 0.5% or 0.75% center type spread spectrum can be selected to reduce EMI. The W83L197R-16 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50O 5% duty cycle. The fixed frequency outputs as REF, 48 MHz provide better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
* * * * * * * * * * Supports PentiumTM II CPUs 4 sets of CPU frequencies selection 2 CPU clocks (one free running CPU clock) 6 PCI synchronous clocks(one free running PCI clock) Optional single or mixed supply: (Vdd3 = VddC= 3.3V5%) or (VddC = 2.5V5%) Skew form CPU to PCI clock 1.5 to 4.0 ns, CPU leads. CPU clock jitter less than 200ps PCI_F,PCI1:6 clock skew less than 500ps O0.5% or O0.75% center type spread spectrum function to reduce EMI Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) * 48 MHz for USB * 28-pin SOP package (209mil)
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Publication Release Date: Mar. 1999 Revision 0.10
W83L197R-16
PRELIMINARY 3.0 BLOCK DIAGRAM
X1 X2 CPU_STOP# SEL100/66#
XTAL OSC
Vdd3 REF2X
PLL1
Spread Spectrum O2/3/4
VddC
STOP
CPUCLK0 CPUCLK1
Vdd3 PCI clock Divder PCI_STOP# PWR_DWN# Power down control PCICLK_F
STOP
5 Vdd3
PCICLK(1:5)
Vdd3 48MHz
PLL2
4.0 PIN CONFIGURATION
Xin Xout Vss PCICLK_F PCICLK1 Vdd3 PCICLK2 PCICLK3 Vdd3 PCICLK4 PCICLK5 Vss Vdd3 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vss Vdd3 REF2X/FS0* VddC CPUCLK0 CPUCLK1 Vss Vdd3 Vss PCI_STOP# CPU_STOP# PWR_DWN# 48MHz/SPREAD* SEL100/66#
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Publication Release Date: Mar. 1999 Revision 0.10
W83L197R-16
PRELIMINARY 5.0 PIN DESCRIPTION
IN - Input OUT - Output I/O - Bi-directional Pin # - Low active * - Internal 250k pull-up
5.1 Crystal I/O
SYMBOL Xin Xout PIN 1 2 I/O IN OUT FUNCTION Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318MHz nominally.
5.2 CPU, PCI Clock Outputs
SYMBOL CPUCLK0 CPUCLK1 PCICLK [ 1:5 ] PCICLK_F PCI_STOP# CPU_STOP# 5,7,8,10,11 4 19 18 I/O I/O PCI_STOP# input used in power management mode for synchronously stopping the all CPU clocks. this pin is CPU_STOP # and used in power management mode for synchronously stopping the all PCI clocks. OUT PIN 24,23 I/O OUT FUNCTION Low skew (< 250ps) clock outputs for host frequencies such as CPU, Chipset and Cache. VddC is the supply voltage for these outputs. Low skew (< 250ps) PCI clock outputs.
5.3 Fixed Frequency Outputs
SYMBOL SEL100/66# REF2X / FS0* PIN 15 26 I/O IN I/O FUNCTION CPU clock frequency select pin. Internal 250k pull-up. Latched input for FS0* to chose frequencies at initial power up. Reference clock during normal operation. Internal 250k pull-up. 48MHz output for USB during normal operation. Latched input for SPREAD* to select the spread spectrum spend at initial power up.
48MHz/SPREAD*
16
I/O
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Publication Release Date: Mar. 1999 Revision 0.10
W83L197R-16
PRELIMINARY
5.4 Power Pins
SYMBOL VddC Vdd3 Vss PIN 25 6,9,13,21,27 3, 12,14,20,22,28 FUNCTION Power supply for core logic and PLL circuitry. Connect to 3.3V supply. Power supply for others Connect to 3.3V supply. Circuit Ground.
6.0 FREQUENCY SELECTION
FS0* 1 1 0 0 SEL100/66# 1 0 1 0 CPUCLK0, CPUCLK1 100MHz 66.8MHz 112MHz 103MHz PCI 33.3MHz 33.4MHz 37.3MHz 34.33MHz
7.0 FUNTION DESCRIPTION
7.1 SPREAD SPECTRUM FUNCTION SELECTION TABLE
SPREAD* 1 0 Spread Spectrum O0.5% O0.75% Type Center Center
7.2 POWER MANAGEMENT FUNCTIONS
The W83L197R-16 may be disabled in the low state according to the following table in order to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period on transitions from running to stop. The CPU and PCI clocks transform between running and stop by waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. CPU_STOP# 0 0 1 1 PCI_STOP# 0 1 0 1 CPUCLK1 LOW LOW RUNNING RUNNING PCICLK1:5 LOW RUNNING LOW RUNNING PCICLK_F RUNNING RUNNING RUNNING RUNNING XTAL & VCOs RUNNING RUNNING RUNNING RUNNING
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Publication Release Date: Mar. 1999 Revision 0.10
W83L197R-16
PRELIMINARY 8.0 SPECIFICATIONS
8.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd). Symbol Vdd , VIN TSTG TB TA Parameter Voltage on any pin with respect to GND Storage Temperature Ambient Temperature Operating Temperature Rating - 0.5 V to + 7.0 V - 65C to + 150C - 55C to + 125C 0C to + 70C
8.2 AC CHARACTERISTICS
Vdd3 = VddCore = 3.3V5%, VddC = 2.5V5% , TA = 0C to +70C Parameter Output Duty Cycle CPU to PCI Offset Skew PCI) (CPU-CPU), (PCItOFF tSKEW tCCJ tJA BWJ tTLH tTHL Vover VRBE 0.7 0.7 1.5 2.1 V V 0.4 Symbol Min 45 1 Typ 50 Max 55 4 250 200 500 500 1.6 Units % ns ps ps ps KHz ns 15 pF Load on CPU and PCI outputs 22 at source of 8 inch PCB run to 15 pF load Ring Back must not enter this range. Test Conditions Measured at 1.5V 15 pF Load Measured at 1.5V 15 pF Load Measured at 1.5V
Cycle to Cycle Jitter CPU Absolute Jitter Jitter Spectrum 20 dB Bandwidth from Center Output Rise (0.4V ~ 2.0V) & Fall (2.0V ~0.4V) Time Overshoot/Undershoot Beyond Power Rails Ring Back Exclusion
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Publication Release Date: Mar. 1999 Revision 0.10
W83L197R-16
PRELIMINARY
8.3 DC CHARACTERISTICS
Vdd3 = VddCore = 3.3V5%, VddC = 2.5V5% , TA = 0C to +70C Parameter Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage IOL = 1 mA Output High Voltage IOH = -1mA Output Low Current IOL 27 20.5 40 50 25 Output High Current IOH 25 31 40 54 27 57 53 85 74 37 55 55 87 88 44 97 139 140 152 76 97 189 155 188 94 mA mA mA mA mA mA mA mA mA mA CPU_F,CPI1 PCI_F,PCI1:6 IOAPIC REF2X 48,24MHz CPU_F,CPI1 PCI_F,PCI1:6 IOAPIC REF2X 48,24MHz VOH 3.1 Vdc CPU_F, CPU1 Symbol VIL VIH IIL IIH VOL 2.0 -25 10 50 Min Typ Max 0.8 Units Vdc Vdc A A mVdc CPU_F, CPU1 Test Conditions
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Publication Release Date: Mar. 1999 Revision 0.10
W83L197R-16
PRELIMINARY 8.4 BUFFER CHARACTERISTICS
8.4.1 TYPE 1 BUFFER FOR CPUCLK
Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.4 V and 2.0 V Rise/Fall Time Max Between 0.4 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.4 1.6 27 Min -27 -27 Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.0 V Vout = 2.0V Vout = 1.2 V Vout = 0.3 V 10 pF Load 20 pF Load
8.4.2 TYPE 3 BUFFER FOR REF2X, 48MHZ
Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 1.0 4.0 29 Min -29 -23 Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.0 V Vout = 3.135V Vout = 1.95 V Vout = 0.4 V 10 pF Load 20 pF Load
8.4.3 TYPE 5 BUFFER FOR PCICLK(1:5,F)
Parameter Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V Symbol IOH(min) IOH(max) IOL(min) IOL(max) TRF(min) TRF(max) 0.5 2.0 30 38 Min -33 -33 Typ Max Units mA mA mA mA ns ns Test Conditions Vout = 1.0 V Vout = 3.135 V Vout = 1.95 V Vout = 0.4 V 15 pF Load 30 pF Load
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Publication Release Date: Mar. 1999 Revision 0.10
W83L197R-16
PRELIMINARY 9.0 OPERATION OF DUAL FUCTION PINS
Pin16 and pin26 are dual function pins and are used for selecting different functions in this device (see Pin description). During power up, these pins are in input mode (see Fig1), therefore, and are considered input select pins. When Vdd reaches 2.5V, the logic level that is present on these pins are latched into their appropriate internal registers. Once the correct information are properly latched, these pins will change into output pins and will be pulled low by default. At the end of the power up timer (within 3 ms) outputs starts to toggle at the specified frequency.
2.5V
Vdd
#16 48/SPREAD* #26 REF2X/FS0*
Output tri-state
Output pull-low Within 3ms
Input All other clocks
Output tri-state
Output
Output pull-low
Each of these pins are a large pull-up resistor ( 250 k @3.3V ) inside. The default state will be logic 1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these dual function pins. Under these conditions, an external 10 k resistor is recommended to be connected to Vdd if logic 1 is expected. The same 10 k connection to ground if a logic 0 is desired. The 10 k resistor should be place before the serious terminating resistor. Note that these logic will only be latched at initial power on. If optional EMI reducing capacitor are needed, they should be placed as close to the series terminating resistor as possible and after the series terminating resistor. These capacitor has typical values ranging from 4.7pF to 22pF.
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Publication Release Date: Mar. 1999 Revision 0.10
W83L197R-16
PRELIMINARY
Vdd
10k Device Pin 10k
Series Terminating Resistor
Clock Trace EMI Reducing Cap Optional
Ground
Ground
Programming Header
Vdd Pad
Ground Pad Series Terminating Resistor
10k Device Pin
Clock Trace EMI Reducing Cap Optional Ground
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Publication Release Date: Mar. 1999 Revision 0.10
W83L197R-16
PRELIMINARY 10.0 ORDERING INFORMATION
Part Number W83L197R-16 Package Type 28 PIN SOP (209mil) Production Flow Commercial, 0C to +70C
11.0 HOW TO READ THE TOP MARKING
W83L197R-16 28051234 814OBB
1st line: Winbond logo and the type number: W83L197R-16 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; A means ASE, S means SPIL, G means GR BB: IC revision
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: Mar. 1999 Revision 0.10
W83L197R-16
PRELIMINARY 12.0 PACKAGE DRAWING AND DIMENSIONS
28-SOP
D
2
15 DIMENSION IN MM MIN. NOM MAX. DIMENSION IN INCH MIN. NOM MAX.
SYMBOL
DTEAIL A
HE E
1
14
A A1 A2 b c D E HE e L L1 Y
2.00 0.05 1.65 1.75 0.22 0.09 9.90 10.20 5.00 5.30 7.40 7.80 0.65 0.55 0.75 1.25 0 1.85 0.38 0.25 10.50 5.60 8.20 0.95 0.10 8 0.002 0.065 0.009 0.004 0.389 0.197 0.291
0.079 0.069 0.073 0.015 0.010 0.401 0.413 0.209 0.220 0.307 0.323
0.0256
0.021 0.030 0.037 0.050 0.004 0 8
A2 A
SEATING PLANE
Y
e
b
DETAIL A A1
SEATING PLANE
L L1
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.
Publication Release Date: Mar. 1999 Revision 0.10
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