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PRELIMINARY
PRM V*I Chip - PRM-AL Pre-Regulator Module
TM
P048F048T12AL
* 48 V input V*I Chip PRM * Vin range 36 - 75 Vdc * High density - 438 W/in3 * Small footprint - 110 W/in2 * Low weight - 0.5 oz (14 g)
* Adaptive Loop feedback * ZVS buck-boost regulator * 1.5 MHz switching frequency * 96% Efficiency * 125C operation Vin = 36 - 75 V Vf = 26 - 55 V Pf = 120 W If = 2.5 A
(c)
Actual size
Product Description
The V*I Chip Pre-Regulator Module (PRM) is a very efficient non-isolated regulator capable of both boosting and bucking a wide range input voltage. It is specifically designed to provide a controlled Factorized Bus distribution voltage for powering downstream V*I Chip Voltage Transformation Modules (VTMs) -- fast, efficient, isolated, low noise Point-of-Load (POL) converters. In combination, PRMs and VTMs form a complete DC-DC converter subsystem offering all of the unique benefits of Vicor's Factorized Power Architecture (FPA): high density and efficiency; low noise operation; architectural flexibility; extremely fast transient response; and elimination of bulk capacitance at the Point-of-Load (POL). In FPA systems, the POL voltage is the product of the Factorized Bus voltage delivered by the PRM and the "K-factor" (the fixed voltage transformation ratio) of a downstream VTM. The PRM controls the Factorized Bus voltage to provide regulation at the POL. Because VTMs perform true voltage division and current multiplication, the Factorized Bus voltage may be set to a value that is substantially higher than the bus voltages typically found in "intermediate bus" systems, reducing distribution losses and enabling use of narrower distribution bus traces. A PRM-VTM chip set can provide up to 100 A, or 115 W at a FPA system density of 200 A/in3, or 230 W/in3 -- and because the PRM can be located, or "factorized," remotely from the POL, these power densities can be effectively doubled. The PRM described in this data sheet features a unique "Adaptive Loop" compensation feedback: a single wire alternative to traditional remote sensing and feedback loops that enables precise control of an isolated POL voltage without the need for either a direct connection to the load or for noise sensitive, bandwidth limiting, isolation devices in the feedback path.
Absolute Maximum Ratings
Parameter
+In to -In PC to -In PR to -In IL to -In VC to -In +Out to -Out SC to -Out VH to -Out OS to -Out CD to -Out SG to -Out Continuous output current Continuous output power Operating junction temperature Storage temperature Case temperature during reflow: (M-Grade) (T-Grade) (M-Grade) (T-Grade)
Values
-1.0 to 85.0 -0.3 to 6.0 -0.3 to 9.0 -0.3 to 6.0 -0.3 to 18.0 -0.3 to 59 -0.3 to 3.0 -0.3 to 9.5 -0.3 to 9.0 -0.3 to 9.0 100 2.5 120 -55 to 125 -40 to 125 -65 to 150 -40 to 150 208
Unit
Vdc Vdc Vdc Vdc Vdc Vdc Vdc Vdc Vdc Vdc mA Adc W C C C C C
DC-DC Converter
VC PC TM IL NC PR VH SC SG OS NC CD
+In
PRM-AL
Factorized Bus (Vf)
+In
+Out
+Out
TM VC PC
VTM K Ro
-Out
Vout
+Out
Vin
-In -Out -In
-Out
The P048F048T12AL is used with any 048 input series VTM to provide a regulated and isolated output.
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Page 1 of 14
PRELIMINARY
General Specifications Part Numbering
V*I Chip Pre-Regulator Module
P
Pre-Regulator Module
048
Input Voltage Designator
F
Configuration (Fig.21)
048
Nominal Factorized Bus Voltage
T
Product Grade Temperatures (C) Grade Storage Operating T -40 to150 -40 to125 M -65 to150 -55 to125
12
Output Power Designator (=Pf /10)
AL
AL = Adaptive Loop
Overview of Adaptive Loop Compensation
Adaptive Loop compensation, illustrated in Figure 1, contributes to the bandwidth and speed advantage of Factorized Power. The PRM monitors its output current and automatically adjusts its output voltage to compensate for the voltage drop in the output resistance of the VTM. ROS sets the desired value of the VTM output voltage, Vout; RCD is set to a value that compensates for the output resistance of the VTM (which, ideally, is located at the point of load). For selection of ROS and RCD, refer to Table 1 below or Page 9.
The V*I Chip's bi-directional VC port : 1. Provides a wake up signal from the PRM to the VTM that synchronizes the rise of the VTM output voltage to that of the PRM. 2. Provides feedback from the VTM to the PRM to enable the PRM to compensate for the voltage drop in VTM output resistance, RO.
Vo = VL 1.0%
VC PC TM IL NC PR VH SC SG OS NC CD
ROS RCD
+In
PRM-AL
Factorized Bus (Vf)
Vf = VL (Io*Ro) + K K
+In
+Out
+Out
TM VC PC
VTM K Ro
-Out
+Out
Vin
-In -Out
-In
L O A D
-Out
Figure 1 -- With Adaptive Loop control, the output of the VTM is regulated over the load current range with only a single interconnect between the PRM and VTM and without the need for isolation in the feedback path. Desired Load Voltage (Vdc) 1.0 1.2 1.5 1.8 2.0 3.3 5.0 10 12 15 24 28 36 48 VTM P/N(1) V048F015T100 V048F015T100 V048F015T100 V048F020T080 V048F020T080 V040F033T060 V048F060T040 V048F120T025 V048F120T025 V048F160T019 V048F240T012 V048F320T009 V048F480T006 V048F480T006 Max VTM Output Current (A)(2) 100 100 100 80 80 60 40 25 25 18.8 12.5 9.4 6.3 6.3 ROS (k)(3) 3.57 2.94 2.37 2.61 2.37 2.89 2.87 2.86 2.37 2.49 2.37 2.74 3.16 2.37 RCD ()(3) 26.1 32.4 39.2 35.7 39.2 32.6 33.2 32.9 39.2 37.4 39.2 35.7 30.1 39.2
Note: (1) Verify the configuration option and product grade temperature before ordering as shown above. (2) See "PRM output power vs. VTM output power" on Page 10 (3) 1% precision resistors recommended Table 1 -- Configure your Chip Set using the PRM-AL
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PRELIMINARY
Electrical Specifications Input Specs (Conditions are at 48 Vin, 48 Vf, full load, and 25C ambient unless otherwise specified)
Parameter Input voltage range Input dV/dt Input undervoltage turn-on Input undervoltage turn-off Input overvoltage turn-on Input overvoltage turn-off Input quiescent current Input current Input reflected ripple current No load power dissipation Internal input capacitance Recommended external input capacitance 30.5 75.8 33.8 31.8 77.3 78.8 0.5 2.6 280 2 5 100 4 81.0 1 Min 36 Typ 48 Max 75 1 35.3 Unit Vdc V/s Vdc Vdc Vdc Vdc mA Adc mA p-p W F F Ceramic See Figure 5 for input filter circuit. Source impedance dependent See Figures 4 & 5 PC low Note
V*I Chip Pre-Regulator Module
Input Waveforms
Figure 2 -- Vf and PC response from power up
Figure 3 -- Vf turn-on waveform with inrush current - PC enabled at full load, 48 Vin
Reflected Ripple Measurement
VC PC TM IL NC PR
10 A
+IN
100 F Al-Electrolytic
+In
PRM-AL
VH SC SG OS NC CD
2.37 k
+Out
+ OUT
-IN
-In
-Out
- OUT
Figure 4 -- Input reflected ripple current at full load and 48 Vin
Figure 5 -- Input filter capacitor recommendation
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PRELIMINARY
Electrical Specifications (continued) Output Specs (Conditions are at 48 Vin, 48 Vf, full load, and 25C ambient unless otherwise specified)
Parameter Output voltage range Output power Output current DC current limit Average short circuit current Set point accuracy Line regulation Load regulation Load regulation (at VTM output) Current share accuracy Efficiency Full load Output overvoltage set point Output ripple voltage No external bypass With 10 F capacitor Switching frequency Output turn-on delay From application of power From PC pin high Internal output capacitance Factorized Bus capacitance 200 100 5 47 300 ms s F F See Figure 2 See Figure 3 Ceramic 1.35 1.0 0.5 1.45 2.0 1.0 1.55 % % MHz Factorized Bus, see Figure 13 Factorized Bus, see Figure 14 Fixed frequency 56 95.6 59.4 % Vdc See Figure 6,7 & 8 1.5 0.1 0.1 1.0 5 0.2 0.2 2.0 10 Min 26 0 0 2.6 3.0 Typ 48 Max 55 120 2.5 3.3 0.5 Unit Vdc W Adc Adc A % % % % % Low line to high line No CD resistor Adaptive Loop IL pin floating Auto recovery Note Factorized Bus voltage (Vf) set by ROS
V*I Chip Pre-Regulator Module
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PRELIMINARY
Electrical Specifications (continued) Efficiency Graphs
Efficiency vs. Output Current
100 95
V*I Chip Pre-Regulator Module
Efficiency vs. Output Current
100 95
Efficiency (%)
Efficiency (%)
Vin 90 85 80 75 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
36V 48V 75V
90 85 80 75 70 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
Vin 26V 48V 75V
Output Current (A) Figure 6 -- Efficiency vs. output current at 48 Vf
Output Current (A)
Figure 7 -- Efficiency vs. output current at 36 Vf
Efficiency vs. Output Current
100 95
Efficiency (%)
90 85 80 75 70 65 60 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 Vin 36V 48V 75V
Output Current (A) Figure 8 -- Efficiency vs. output current at 26 Vf
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PRELIMINARY
Figure 9 -- Transient response; PRM alone, 48 Vin, 0 - 2.5 - 0 A no load capacitance. Local Loop
Figure 10 -- Transient response; PRM alone, 36 Vin, 0 - 2.5 - 0 A no load capacitance. Local Loop
Figure 11 -- Transient response; PRM alone, 26 Vin, 0 - 2.5 - 0 A no load capacitance. Local Loop
Figure 12 -- PC during fault - frequency will vary as a function of line voltage.
Figure 13 -- Output ripple full load no bypass capacitance. Vf = 48 Vdc
Figure 14 -- Output ripple full load 10F bypass capacitance. Vf = 48 Vdc
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PRELIMINARY
Electrical Specifications (continued) Auxiliary Pins (Conditions are at 48 Vin, 48 Vf, full load, and 25C ambient unless otherwise specified)
Parameter VC (VTM Control) Peak voltage PC (Primary Control) DC voltage Module disable voltage Module enable voltage Disable hysteresis Current limit Enable delay time Disable delay time IL (Current Limit Adjust) Voltage Accuracy PR (Parallel Port) Voltage Source current External capacitance VH (Auxiliary Voltage) Range Regulation SC (Secondary Control) Voltage Internal capacitance External capacitance OS (Output Set) Set point accuracy Reference offset CD (Compensation Device) External resistance 20 Omit resistor for regulation at output of PRM 1.5 4 % mV Includes 1% external resistor 1.22 1.24 0.1 0.7 1.26 Vdc F F Referenced to SG 8.7 9.0 0.04 9.3 Vdc %/mA Maximum source = 5 mA, referenced to SG 0.6 1 100 7.5 V mA pF Referenced to SG 1 15 V % Based on DC current limit set point 4.8 2.3 5.0 2.4 2.5 100 1.75 100 1 1.90 2.6 5.2 Vdc Vdc Vdc mV mA s s Source only after start up; not to be used for aux. supply; 100 k minimum load impedance to assure start up. Referenced to -IN Referenced to -IN 12 14 18 V Referenced to -OUT Min Typ Max Unit Note
V*I Chip Pre-Regulator Module
General Specs
Parameter MTBF MIL-HDBK-217F Agency approvals (pending) Mechanical parameters Weight Dimensions Length Width Height 1.26 / 32 0.87 / 22 0.25 / 6,2 in / mm in / mm in / mm 0.5 / 14 oz / g 2.2 cTUVus CE Mark Mhrs 25C, GB UL/CSA 60950, EN60950 Low voltage directive See mechanical drawing, Figure 19 Min Typ Max Unit Note
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PRELIMINARY
Pin / Control Functions
+IN / -IN DC Voltage Ports The V*I Chip maximum input voltage should not be exceeded. PRMs have internal over / undervoltage lockout functions that prevent operation outside of the specified input range. PRMs will turn on when the input voltage rises above its undervoltage lockout. If the input voltage exceeds the overvoltage lockout, PRMs will shut down until the overvoltage fault clears. PC will toggle indicating an out of bounds condition. +OUT / -OUT Factorized Voltage Output Ports These ports provide the Factorized Bus voltage output. The -OUT port is connected internally to the -IN port through a current sense resistor. The PRM has a maximum power and a maximum current rating and is protected if either rating is exceeded. Do not short -OUT to -IN. VC - VTM Control The VTM Control (VC) port supplies an initial VCC voltage to downstream VTMs, enabling the VTMs and synchronizing the rise of the VTM output voltage to that of the PRM. The VC port also provides feedback to the PRM to compensate for voltage drop due to the VTM output resistance. The PRM's VC port should be connected to the VTM VC port. A PRM VC port can drive a maximum of two (2) VTM VC ports. PC - Primary Control The PRM voltage output is enabled when the PC pin is open circuit (floating). To disable the PRM output voltage, the PC pin is pulled low. Open collector optocouplers, transistors, or relays can be used to control the PC pin. When using multiple PRMs in a high power array, the PC ports should be tied together to synchronize their turn on. During an abnormal condition the PC pin will pulse (Fig.12) as the PRM initiates a restart cycle. This will continue until the abnormal condition is rectified. The PC should not be used as an auxiliary voltage supply, nor should it be switched at a rate greater than 1 Hz. TM - Factory Use Only IL - Current Limit Adjust The PRM has a preset, maximum, current limit set point. The IL port may be used to reduce the current limit set point to a lower value. See "adjusting current limit" on page 10. PR - Parallel Port The PR port signal, which is proportional to the PRM output power, supports current sharing among PRMs. To enable current sharing, PR ports should be interconnected. Bypass capacitance should be used when interconnecting PR ports and steps should be taken to minimize coupling noise into the interconnecting bus. Please consult Vicor Applications Engineering regarding additional considerations. VH - Auxiliary Voltage VH is a gated, non-isolated, nominally 9 Volt, regulated DC voltage (see "Auxiliary Pins" specifications, on Page 7) that is referenced to SG. VH may be used to power external circuitry having a total current consumption of no more than 5 mA.
-OUT
V*I Chip Pre-Regulator Module
AL Version
4 3 2 1 A B C D E F
VH SC SG OS NC CD
A B C D E F
VC PC TM IL NC PR
G
G H J K
+OUT
H J K
+IN
L M N P
L M N P
-IN
Bottom View
Signal Name +IN -IN VC PC TM IL PR VH SC SG OS CD +OUT -OUT
BGA Designation G1-K1,G2-K2 L1-P1, L2-P2 A1,A2 B1, B2 C1, C2 D1, D2 F1, F2 A3, A4 B3, B4 C3, C4 D3, D4 F3, F4 G3-K3, G4-K4 L3-P3, L4-P4
Figure 15 -- PRM pin configuration
SC - Secondary Control The load voltage may be controlled by connecting a resistor or voltage source to the SC port. The slew rate of the output voltage may be controlled by controlling the rate-of-rise of the voltage at the SC port (e.g., to limit inrush current into a capacitive load). SG - Signal Ground This port provides a low inductance Kelvin connection to -IN and should be used as reference for the OS, CD, SC,VH and IL ports. OS - Output Set The application-specific value of the Factorized Bus voltage (Vf) is set by connecting a resistor between OS and SG. Resistor value selection is shown in Table 1 on Page 2, and described on Page 9. If no resistor is connected, the PRM output will be approximately one volt. If set resistor is not colocated with the PRM a load bypass capacitor of ~200 pF may be required. CD - Compensation Device Adaptive Loop control is configured by connecting an external resistor between the CD port and SG. Selection of an appropriate resistor value (see Equation 2 on Page 9 and Table 1 on Page 2) configures the PRM to compensate for voltage drops in the equivalent output resistance of the VTM and the PRM-VTM distribution bus. If no resistor is connected to CD, the PRM will be in Local Loop mode and will regulate the +OUT / -OUT voltage to a fixed value.
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Page 8 of 14
PRELIMINARY
Application Information
V*I Chip Pre-Regulator Module
VC PC TM IL NC PR
+In
PRM-AL
VH SC SG OS NC CD
ROS RCD
Factorized Bus (Vf)
0.4 H
+In
+Out
+Out
Vin
-In -Out
Vf =
(IL*Ro) VL + K K
TM VC PC
VTM K Ro
-Out
+Out
-In
L O A D
-Out
Figure 16 -- Adaptive Loop compensation with soft start using the SC port.
Output Voltage Setting with Adaptive Loop The equations for calculating ROS and RCD to set a VTM output voltage are: 93100 ROS = ( VL * 0.8395 ) - 1 K (1) Where Vfd is the desired factorized bus and Vfs is the set factorized bus. A low voltage source can be applied to the SC port to margin the load voltage in proportion to the SC reference voltage. An external capacitor can be added to the SC port as shown in Figure 16 to control the output voltage slew rate for soft start.
RCD =
91238 ROS
+1
(2)
Nominal Vout Range (Vdc) 0.8 1.1 1.6 2.2 3.3 4.3 6.5 8.7 13.0 17.4 26.0 1.6 2.2 3.3 4.4 6.6 8.8 13.4 17.9 26.9 36.0 54.0
VTM K Factor 1/32 1/24 1/16 1/12 1/8 1/6 1/4 1/3 1/2 2/3 1
VL = Desired load voltage VOUT = VTM output voltage K = VTM transformation ratio (available from appropriate VTM data sheet) Vf = PRM output voltage, the Factorized Bus (see Figure 16) RO = VTM output resistance (available from appropriate VTM data sheet) IL = Load Current (actual current delivered to the load)
Table 2 -- 048 input series VTM K factor selection guide
Output Voltage Trimming (optional) After setting the output voltage from the procedure above the output may be margined down (26Vf min) by a resistor from SC-SG using this formula: 10000 Vfd Vfs - Vfd
Rd =
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PRELIMINARY
Application Information (continued)
OVP - Overvoltage Protection The output Overvoltage Protection set point of the P048F048T12AL is factory preset for 56 V. If this threshold is exceeded the output shuts down and a restart sequence is initiated, alos indicated by PC pulsing. If the condition that causes OVP is still present, the unit will again shut down. This cycle will be repeated until the fault condition is removed. The OVP set point may be set at the factory to meet unique high voltage requirements. PRM output power versus VTM output power As shown in Figure 17, the P048F048T12AL is rated to deliver 2.5 A maximum, when it is delivering an output voltage in the range from 26 V to 48 V, and 120 W, maximum, when delivering an output voltage in the range from 48 V to 55 V. When configuring a PRM for use with a specific VTM, refer to the appropriate VTM data sheet. The VTM input power can be calculated by dividing the VTM output power by the VTM efficiency (available from the VTM data sheet). The input power required by the VTM should not exceed the output power rating of the PRM. Adjusting current limit The current limit can be lowered by placing an external resistor between the IL and SG ports (see figure 18 for resistor values). With the IL port open-circuit, the current limit is preset to be within the range specified in the output specifications table on Page 4.
V*I Chip Pre-Regulator Module
100.00
Resistance (k)
10.00
1.00 0.5
2.55 2.50 2.45
1
1.5
2
2.5
Desired PRM Output Current Limit (A)
Figure 18 -- Calculated external resistor value for adjusting current limit, actual value may vary.
Current (A)
2.40 2.35 2.30 2.25 2.20 2.15
Safe Operating Area
Input fuse recommendations A fuse should be incorporated at the input to the PRM, in series with the +IN port. A fast acting fuse, NANO2 FUSE 451/453 Series 10 A 125 V, or equivalent, may be required to meet certain safety agency Conditions of Acceptability. Always ascertain and observe the safety, regulatory, or other agency specifications that apply to your specific application. Product safety considerations If the input of the PRM is connected to SELV or ELV circuits, the output of the PRM can be considered SELV or ELV respectively.
0
~ ~
20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
Factorized Bus Voltage (Vf)
Figure 17 -- P048F048T12AL rating based on Factorized Bus voltage
The Factorized Bus voltage should not exceed an absolute limit of 55 V, including steady state, ripple and transient conditions. Exceeding this limit may cause the internal OVP set point to be exceeded. Parallel considerations The PR port is used to connect two or more PRMs in parallel to form a higher power array. When configuring arrays, PR port interconnection bypass capacitance must be used at ~1nF per PRM. Additionally one PRM should be designated as the master while all other PRMs are set as slaves by shorting their SC pin to SG. The PC pins must be directly connected (no diodes) to assure a uniform start up sequence. The factorized bus should be connected in parallel as well.
If the input of the PRM is connected to a centralized DC power system where the working or float voltage is above SELV, but less than or equal to 75 V, the input and output voltage of the PRM should be classified as a TNV-2 circuit and spaced 1.3 mm from SELV circuitry or accessible conductive parts according to the requirements of UL60950, CSA 22.2 60950, EN60950, and IEC60950.
Applications assistance Please contact Vicor Applications Engineering for assistance, 1-800-927-9474, or email at apps@vicr.com.
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Page 10 of 14
PRELIMINARY
Mechanical Specifications (continued)
6,2 0.25 3,01 0.118 15,99 0.630
V*I Chip Pre-Regulator Module
22,0 0.87
3,01 0.118 1,10 (12) X 0.043
OUTPUT
(2) X OUTPUT INPUT 32,0 1.26
30,00 1.181 26,00 (2) X 1.024 (2) X 22,00 0.866 15,55 0.612 (2) X 10,00 0.394 0,45 0.020
(2) X 24,00 (2) X 0.945 20,00 (2) X 0.787
28,00 1.102
(4) X 8,10 0.319
INPUT C L
TOP VIEW (COMPONENT SIDE)
C L BOTTOM VIEW
NOTES: mm 1- DIMENSIONS ARE inch . 2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: .X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005] 3- PRODUCT MARKING ON TOP SURFACE
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Figure 19-- PRM J-Lead mechanical outline; Onboard mounting
3,26 0.128 1,38 TYP 0.054
VC
15,74 0.620
3,26 0.128 0,51 TYP 0.020
VH
(24) X 1,48 0.058
PC
SC
TM
SG
NC
(4) X 26,00 (4) X 1.024 22,00 (4) X 0.866 15,96 0.628 (4) X 10,00 0.394
30,00 1.181
IL
OS NC
28,00 (4) X 1.102 (4) X 24,00 0.945 20,00 (4) X 0.787 8,48 (8) X 0.334
PR
CD
+IN
+OUT -OUT
-IN
RECOMMENDED LAND PATTERN
(COMPONENT SIDE SHOW)
NOTES: mm 1- DIMENSIONS ARE inch . 2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: .X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005]
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Figure 20-- PRM J-Lead PCB land layout information; Onboard mounting
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PRELIMINARY
Configuration Options
Onboard (1) (Figure 21) 875 W/in3 2.4 C/W 1.1 C/W 6.8 C/W
V*I Chip Pre-Regulator Module
Configuration Effective power density Effective Junction-Board thermal resistanc Effective Junction-Case thermal resistance Effective Junction-Ambient thermal resistance 300LFM Note: (1) Surface mounted to a 2" x 2" FR4 board, 4 layers 2 oz Cu (2) Heat sink available as a separate item
Onboard with 0.25" Heat Sink(2) 437 W/in3 2.4 C/W N/A 5.0 C/W
22.0 0.87
32.0 1.26
6.3 0.25
STANDARD MOUNT
mm in
Figure 21--Standard mounting - package F
Figure 22--Hole location for push pin heatsink relative to VIC
Thermal
Symbol Parameter
Over temperature shutdown Thermal capacity Junction-to-case thermal impedance Junction-to-board thermal impedance Junction-to-ambient (1) Junction-to-ambient (2)
Min
125
Typ
135 0.61 1.1 2.1 6.5 5.0
Max
140
Unit
C Ws/C C/W C/W C/W C/W
Note
Junction temperature
RJC RJB RJA RJA Notes:
(1) P048F048T12AL surface mounted to a 2" x 2" FR4 board, 4 layers 2 oz Cu, 300 LFM. (2) P048F048T12AL with a 0.25"H heatsink surface mounted on FR4 board, 300 LFM.
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PRELIMINARY
Application Information
V*I Chip soldering recommendations V*I Chip modules are intended for reflow soldering processes. The following information defines the processing conditions required for successful attachment of a V*I Chip to a PCB. Failure to follow the recommendations provided can result in aesthetic or functional failure of the module. Storage V*I Chip modules are currently rated at MSL 5. Exposure to ambient conditions for more than 48 hours requires a 24 hour bake at 125C to remove moisture from the package. Solder paste stencil design Solder paste is recommended for a number of reasons, including overcoming minor solder sphere co-planarity issues as well as simpler integration into overall SMD process. 63/37 SnPb, either no-clean or water-washable, solder paste should be used. Pb-free development is underway. The recommended stencil thickness is 6 mils. The apertures should be 20 mils in diameter for the Inboard (BGA) application and 0.9-0.9:1 for the Onboard (J-Leaded). Pick and place Modules should be placed within 5 mils. to maintain placement position, the modules should not be subjected to acceleration greater than 500 in/sec2 prior to reflow. Reflow There are two temperatures critical to the reflow process; the solder joint temperature and the module's case temperature. The solder joint's temperature should reach at least 220C, with a time above liquidus (183C) of ~30 seconds. The module's case temperature must not exceed 208 C at anytime during reflow. Because of the T needed between the pin and the case, a forced-air convection oven is preferred for reflow soldering. This reflow method generally transfers heat from the PCB to the solder joint. The module's large mass also reduces its temperature rise. Care should be taken to prevent smaller devices from excessive temperatures. Reflow of modules onto a PCB using Air-Vac-type equipment is not recommended due to the high temperature the module will experience. Inspection Solder joints should conform to IPC 12.2 * Properly wetted fillet must be evident. * Heel fillet height must exceed lead thickness plus solder thickness.
Figure 23-- Properly reflowed V*I Chip J-Lead
16 Soldering Time
V*I Chip Pre-Regulator Module
Removal and rework V*I Chip modules can be removed from PCBs using special tools such as those made by Air-Vac. These tools heat a very localized region of the board with a hot gas while applying a tensile force to the component (using vacuum). Prior to component heating and removal, the entire board should be heated to 80-100C to decrease the component heating time as well as local PCB warping. If there are adjacent moisture-sensitive components, a 125C bake should be used prior to component removal to prevent popcorning. V*I Chip modules should not be expected to survive a removal operation.
239
Joint Temperature, 220C Case Temperature, 208C
183 165
degC
91
Figure 22--Thermal profile diagram
vicorpower.com
800-735-6200
V*I Chip Pre-Regulator Module
P048F048T12AL
Rev. 1.0
Page 13 of 14
Warranty
Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended to the original purchaser only. EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Vicor will repair or replace defective products in accordance with its own best judgement. For service under this warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within the terms of this warranty. Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes all risks of such use and indemnifies Vicor against all damages.
Vicor's comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. All sales are subject to Vicor's Terms and Conditions of Sale, which are available upon request.
Specifications are subject to change without notice.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the products described in this data sheet. Interested parties should contact Vicor's Intellectual Property Department.
Vicor Corporation 25 Frontage Road Andover, MA, USA 01810 Tel: 800-735-6200 Fax: 978-475-6715 email Vicor Express: vicorexp@vicr.com Technical Support: apps@vicr.com
vicorpower.com
800-735-6200
V*I Chip Pre-Regulator Module
P048F048T12AL
Rev. 1.0
11/05

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