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QCOTSTM UT7Q512 512K x 8 SRAM
Data Sheet August, 2002
FEATURES q 100ns (5 volt supply) maximum address access time q Asynchronous operation for compatibility with industrystandard 512K x 8 SRAMs q TTL compatible inputs and output levels, three-state bidirectional data bus q Typical radiation performance - Total dose: 30krad(Si) - 30krad(Si) to 300krad(Si), depending on orbit, using Aeroflex UTMC patented shielded package - SEL Immune >80 MeV-cm2 /mg - LET TH(0.25) = 5MeV-cm 2/mg - Saturated Cross Section (cm2) per bit, ~1.0E-7 - 1.5E-8 errors/bit-day, Adams 90% geosynchronous heavy ion q Packaging options: - 32-lead ceramic flatpack (weight 2.5-2.6 grams) q Standard Microcircuit Drawing 5962-99606 - QML T and Q compliant INTRODUCTION The QCOTSTM UT7Q512 Quantified Commercial Off-theShelf product is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (E), an active LOW Output Enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90% when deselected. Writing to the device is accomplished by taking the Chip Enable One ( E) input LOW and the Write Enable ( W) input LOW. Data on the eight I/O pins (DQ0 through DQ7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable One (E) and Output Enable (G) LOW while forcing Write Enable (W) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the eight I/O pins. The eight input/output pins (DQ0 through DQ 7) are placed in a high impedance state when the device is deselected (E, HIGH), the outputs are disabled (G HIGH), or during a write operation (E LOW and W LOW).
Clk. Gen.
A 0 A1 A2 A3 A4 A5 A6 A 7 A8 A 9
Pre-Charge Circuit
Row Select
Memory Array 1024 Rows 512x8 Columns
I/O Circuit Column Select Data Control CLK Gen.
A 10 A11 A 12 A 13 A 14 A 15 A 16 A 17 A 18
D 0 - DQ 7 Q
E W G Figure 1. UT7Q512 SRAM Block Diagram
PIN NAMES A(18:0) DQ(7:0) E W G V DD V SS Address Data Input/Output Chip Enable Write Enable Output Enable Power Ground
DEVICE OPERATION The UT7Q512 has three control inputs called Enable 1 ( E), Write Enable ( W), and Output Enable (G); 19 address inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). The E Device Enable controls device selection, active, and standby modes. Asserting E enables the device, causes IDD to rise to its active value, and decodes the 19 address inputs to select one of 524,288 words in the memory. W controls read and write operations. During a read cycle, G must be asserted to enable the outputs. Table 1. Device Operation Truth Table G X1 W X 0 1 1 E 1 0 0 0 I/O Mode 3-state Data in 3-state Data out Mode Standby Write Read2 Read
A18 A16 A14 A12 A7 A6 A5 A4 VD D V SS A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
NC A15 A17 W A13 A8 A9 A11 VS S VD D G A10 E DQ7 DQ6 DQ5 DQ4 NC
X 1 0
Notes: 1. "X" is defined as a "don't care" condition. 2. Device active; outputs disabled.
READ CYCLE A combination of W greater than V IH (min), G and E less than V IL (max) defines a read cycle. Read access time is measured from the latter of Device Enable, Output Enable, or valid address to valid data output. SRAM read Cycle 1, the Address Access in figure 3a, is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid data appears on data outputs DQ(7:0) after the specified t AVQV is satisfied. Outputs remain active throughout the entire cycle. As long as Device Enable and Output Enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV ). SRAM read Cycle 2, the Chip Enable-Controlled Access in figure 3b, is initiated by E going active while G remains asserted, W remains deasserted, and the addresses remain stable for the entire cycle. After the specified t ETQV is satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQ(7:0). SRAM read Cycle 3, the Output Enable-Controlled Access in figure 3c, is initiated by G going active while E is asserted, W is deasserted, and the addresses are stable. Read access time is tGLQV unless t AVQV or tETQV have not been satisfied.
Figure 2a. UT7Q512 100ns SRAM Shielded Package Pinout (36)
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 V SS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VD D A15 A17 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
Figure 2b. UT7Q512 100ns SRAM Package Pinout (32)
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WRITE CYCLE A combination of W less than VIL (max) and E less than VIL(max) defines a write cycle. The state of G is a "don't care" for a write cycle. The outputs are placed in the high-impedance state when either G is greater than V IH (min), or when W is less than VIL (max). Write Cycle 1, the Write Enable-Controlled A ccess in figure 4a, is defined by a write terminated by W going high, with E still active. The write pulse width is defined by tWLWH when the write is initiated by W, and by t ETWH when the write is initiated by E. Unless the outputs have been previously placed in the highimpedance state byG, the user must wait t WLQZ before applying data to the nine bidirectional pins DQ(7:0) to avoid bus contention. Write Cycle 2, the Chip Enable-Controlled Access in figure 4b, is defined by a write terminated by the latter of E going inactive. The write pulse width is defined by tWLEF when the write is initiated by W, and by t ETEF when the write is initiated by the E going active. For the W initiated write, unless the outputs have been previously placed in the high-impedance state
by G, the user must wait t WLQZ before applying data to the eight bidirectional pins DQ(7:0) to avoid bus contention. TYPICAL RADIATION HARDNESS Table 2. Typical Radiation Hardness Design Specifications 1 Total Dose Heavy Ion Error Rate2 30 1.5E-7 krad(Si) nominal Errors/Bit-Day
Notes: 1. The SRAM will not latchup during radiation exposure under recommended operating conditions. 2. 90% worst case particle environment, Geosynchronous orbit, 100 m ils of Aluminum.
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ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS ) SYMBOL VDD V I/O TSTG PD TJ JC II PARAMETER DC supply voltage Voltage on any pin Storage temperature Maximum power dissipation Maximum junction temperature 2 Thermal resistance, junction-to-case3 DC input current LIMITS -0.5 to 7.0V -0.5 to 7.0V -65 to +150C 1.0W +150C 10C/W
10 mA
Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Maximum junction temperature may be increased to +175C during burn-in and steady-static life. 3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS SYMBOL VDD TC VIN PARAMETER Positive supply voltage Case temperature range DC input voltage LIMITS 4.5 to 5.5V -55 to +125C 0V to V DD
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DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* (VDD = 5.0V10%) (-55C to +125C) SYMBOL VIH V IL V OL V OH CIN 1 CIO 1 I IN IOZ PARAMETER High-level input voltage Low-level input voltage Low-level output voltage High-level output voltage Input capacitance Bidirectional I/O capacitance Input leakage current Three-state output leakage current IOL = 2.1mA,V DD =4.5V IOH = -1mA,VDD =4.5V = 1MHz @ 0V = 1MHz @ 0V VSS < V IN < VDD , V DD = VDD (max) 0V < V O < V DD VDD = VDD (max) G = V DD (max) IOS 2, 3 I DD(OP) Short-circuit output current Supply current operating @ 1MHz 0V Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019 . 1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second.
CONDITION
MIN 2.2
MAX
UNIT V
.8 0.4 2.4 10 10 -2 -2 2 2
V V V pF pF A A
-80
80 50
mA mA
100
mA
-55C and 25C +125C
35 1
A mA
5
AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)* (VDD = 5.0V10%) (-55C to +125C) SYMBOL tAVAV1 tAVQV tAXQX2 tGLQX 2 tGLQV tGHQZ 2 tETQX 2,3 tETQV 3 tEFQZ1,2,4 Read cycle time Read access time Output hold time G-controlled Output Enable time G-controlled Output Enable time (Read Cycle 3) G-controlled output three-state time E-controlled Output Enable time E-controlled access time E-controlled output three-state time 10 100 30 10 5 50 30 PARAMETER MIN 100 100 MAX UNIT ns ns ns ns ns ns ns ns ns
Notes: * Post-radiation performance guaranteed at 25 C per MIL-STD-883 Method 1019. 1. Functional test. 2. Three-state is defined as a 500mV change from steady-state output voltage (see Figure 3). 3. The ET (enable true) notation refers to the falling edge of E. SEU immunity does not affect the read parameters. 4. The EF (enable false) notation refers to the rising edge of E. SEU immunity does not affect the read parameters.
High Z to Active Levels
Active to High Z Levels
VLOAD + 500mV } VLOAD VLOAD - 500mV { { }
VH - 500mV
VL + 500mV
Figure 3. 5-Volt SRAM Loading
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tAVAV A(18:0)
DQ(7:0)
Previous Valid Data
Valid Data tAVQV
Assumptions: 1 . E and G < VIL (max) and W > VIH (min)
tAXQX Figure 4a. SRAM Read Cycle 1: Address Access
A(18:0) E
tETQV tEFQZ t ETQX
DATA VALID
DQ(7:0)
Assumptions: 1. G < V IL (max) and W > V IH (min)
Figure 4b. SRAM Read Cycle 2: Chip Enable - Controlled Access
t AVQV A(18:0) G tGLQX DQ(7:0)
Assumptions: 1 . E< VIL (max) and W > VIH (min)
tGHQZ
DATA VALID
tGLQV
Figure 4c. SRAM Read Cycle 3: Output Enable - Controlled Access
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AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)* (VDD = 5.0V10%) (-55C to +125C) SYMBOL tAVAV 1 tETWH tAVET tAVWL tWLWH tWHAX tEFAX tWLQZ 2 tWHQX 2 tETEF tDVWH tWHDX tWLEF tDVEF tEFDX tAVWH tWHWL1 Write cycle time Device Enable to end of write Address setup time for write (E - controlled) Address setup time for write (W - controlled) Write pulse width Address hold time for write (W - controlled) Address hold time for Device Enable (E - controlled) W - controlled three-state time W - controlled Output Enable time Device Enable pulse width (E - controlled) Data setup time Data hold time Device Enable controlled write pulse width Data setup time Data hold time Address valid to end of write Write disable time 5 80 40 0 80 40 0 80 5 PARAMETER MIN 100 80 0 0 60 0 0 30 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 101 9 1. Functional test performed with outputs disabled (G high). 2 . Three-state is defined as 500mV change from steady-state output voltage (see Figure 3).
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A(18:0) t AVAV2 E tAVWH t ETWH W tAVWL Q(7:0) tWLQZ D(7:0)
Assumptions: 1. G < V IL (max). If G > V IH (min) then Q( 7:0) will be in three-state for the entire cycle. 2. G high for t AVAV cycle. APPLIED DATA
t WHWL tWHAX
t WLWH
tWHQX
tDVWH
tWHDX
Figure 5a. SRAM Write Cycle 1: Write Enable - Controlled Access
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tAVAV 3 A(18:0) t AVET tETEF tEFAX E
or
t AVET E tETEF tWLEF
APPLIED DATA
tEFAX
W D(7:0)
t WLQZ Q(7:0)
t DVEF
t EFDX
Assumptions & Notes: 1. G < V IL (max). If G > V IH (min) then Q(7:0) will be in three-state for the entire cycle. 2. Either E scenario above can occur. 3. G high for t AVAV cycle.
Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access
CMOS V DD-0.05V 300 ohms 10% V LOAD = 1.75V 0.5V < 5ns 50pF Input Pulses < 5ns 10% 90% 90%
Notes: 1. 50pF including scope probe and test socke t capacitance. 2. Measurement of data output occurs at the low to high or high to low transition mid-point (i.e., CMOS input = V DD/2).
Figure 6. AC Test Loads and Input Waveforms
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DATA RETENTION MODE
VDD
50% t EFR
VDR > 4.5V
50% tR
E
Figure 7. Low VDD Data Retention Waveform (100ns)
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) (TC = 25C, 1 Sec Data Retention Test) SYMBOL V DR I DDR 1 tEFR 1,2 tR1,2 PARAMETER VDD for data retention Data retention current Chip deselect to data retention time Operation recovery time MINIMUM 4.5 -0 tAVAV MAXIMUM -.4 UNIT V mA ns ns
Notes: 1. E = VSS , all other inputs = V DR or V SS . 2. Not guaranteed or tested.
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) (TC = 25C, 10 Second Data Retention Test) SYMBOL V DD 1 tEFR2, 3 tR2, 3 PARAMETER VDD for data retention Chip select to data retention time Operation recovery time MINIMUM 4.5 0 tAVAV MAXIMUM 5.5 UNIT V ns ns
Notes: 1. Performed at VDD (min) and VDD (max). 2. E = VSS , all other inputs = VDR or V SS . 3. Not guaranteed or tested.
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PACKAGING
1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to V SS . 3. Lead finishes are in accordance to MIL-PRF-38535. 4. Lead position and coplanarity are not measured. 5. ID mark is vendor option. 6. With solder increase maximum by 0.003". 7. Weight 2.5-2.6 grams. Figure 8. 32-pin Ceramic FLATPACK package
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ORDERING INFORMATION 512K x 8 SRAM:
UT7Q512K -* *
*
*
Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder)
Screening: (C) = Military Temperature Range flow (P) = Prototype flow (W) = Extended Industrial Temperature Range Flow (-40oC to +125oC)
Package Type: (U) = 32-lead ceramic flatpack package (bottom brazed)
- = 100ns access time, 5V operation
Aeroflex UTMC Core Part Number
Notes: 1 . Lead finish (A,C, or X) must be specified. 2 . If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3 . Prototype flow per UTMC Manufacturing Flows Document. Tested at 25C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4 . Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55 C, room temp, and +125C. Radiation neither tested nor guaranteed. 5 . Extended Industrial Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -40C to +125C. Radiation neither tested nor guaranteed. Gold Lead Finish Only.
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512K x 8 SRAM: SMD
5962 - 99606
** * * *
Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (U) = 32-lead ceramic flatpack package (bottom-brazed) Class Designator: (T) = QML Class T (Q) = QML Class Q
Device Type 01 = 100ns access time, 5.0 volt operation , Mil-Temp 02 = 100ns access time, 5.0 volt operation, Extended Industrial Temp (-40 oC to +125 oC) Drawing Number: 99606 Total Dose (-) = none (D) = 1E4 (10 krad(Si)) (P) = 3E4 (30krad(Si)), Contact Factory Federal Stock Class Designator: No Options
Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3.Total dose radiation must be specified when ordering.
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15
NOTES
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