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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16454A
The PD16454A is a single-chip controller/driver for dot matrix LCD, enabling the display of up to 48 alphanumerical and kana characters and symbols (24 characters x 2 lines) each of which is composed of 5 x 7 dots. On-chip charge pump-type DC/DC converter that enables the PD16454A to operate on a single 5-V power supply and the chip design aiming at tape carrier package (TCP) mounting make the PD16454A ideal for portable equipment and all kinds of data terminals for which downsizing is an important consideration.
FEATURES
* 5 x 7 dot matrix LCD display controller/driver * 24 characters x 2 lines, 1/14 duty display * Interface with CPU 4 bits wise * On-chip ROM and RAM * Display data RAM (8 x 48 bits) * Character generator RAM (8 user-defined characters; 5 x 7 x 8 bits) * Character generator ROM (160 characters; 5 x 7 x 160 bits) * On-chip LCD driver * 120 segment signals * 14 common signals * Single 5-V power supply * Doubling DC/DC booster generating 10 V for driving LCDs * Total power dissipation: 2 mA max. * On-chip temperature compensation circuit * TCP mounting enabled
ORDERING INFORMATION
Part number Available as TCP (TAB) Chip
PD16454AN-XXX PD16454AP
TPC formats are created on a custom-made basis. representative.
For additional information, contact an NEC sales
For purchases of chips only, additional documents on quality are required. Contact an NEC sales representative.
Document No. IC-3362A (2nd edition) (0. D. No. IC-8800) Date Published March 1997 P Printed in Japan
(c)
1994
2
Address counter (AC) 6 6 6 6 Timing circuit 3 8 CLK RS E DB0 to DB3 RESET TEST BF Busy flag Character generator RAM (CGRAM) 5 x 7 x 8 bits Character generator ROM (CGROM) 5 x 7 x 160 bits 12-bit latch Segment signal driver SEG1 120 SEG120 I/O buffer 8 8 Data register (DR) 8 6 8 8 3 3 8 4 8 Instruction register (IR) 8 Instruction decoder Disply data RAM (DDRAM) 8 x 48 bits 14-bit shift register 14 Common signal driver COM1 14 COM14 120 C (+) C (-) DC/DC converter 120 5 Serializer (parallel data serial data) VDD VCC1 VCC2 GND1 GND2 OP amp. 5 120-bit shift register VIN (+) VIN (-) V1 V2 V3 V4 V5
BLOCK DIAGRAM
PD16454A
PD16454A
PIN FUNCTION
Symbol RS Pin No. 138 Input/Output Input Connect to CPU Function Register selection signal `0' instruction register (IR) `1' data register (DR) Data reading signal Reads data at the falling edge. TEST 140 Input Test pin `1' = test mode `0' or open = normal operation CPU When busy flag is `1', indicates that internal part of LCD is currently operating. In test mode, functions as test output. Data input signals In test mode, function as output pin. Reset is performed with reset signal `0' LCD-driving clock Common signals Segment signal outputs LCD-driving supply voltages Power supply for logic circuits Power supply for logic circuits Boosted power supply Ground for logic circuit Ground for high-voltage circuit Reference voltage supply LCD-driving supply voltage adjustment input Capacitor Capaditor Capacitor connection pin for booster Capacitor connection pin for booster
E
139
Input
CPU
BF
145
Output
DB0 to 3
141 to 144
Input/Output
CPU
RESET CLK COM1 to 14 SEG1 to 120 V1 to 5 VCC1 VCC2 VDD GND1 GND2 VIN (+) VIN (-) C (+) C (-)
137 146 128 to 134, 7 to 1 127 to 68, 8 to 67 153 to 157 148 136 135 147 158 151 152 149 150
Input Input Output Output
CPU CPU LCD LCD Power supply Power supply Power supply Power supply Power supply Power supply Power supply
3
PD16454A
PIN CONFIGURATION (Pad Configuration)
GND2 V5 V4 V3 V2 V1 VIN + VIN - C- C+ VCC1 GND1 CLK BF DB3 DB2 DB1 DB0 TEST E RS RESET VCC2 VDD
COM14
158 1
135 134 COM7
COM8 SEG61 SEG62
COM1 SEG1 SEG2
67
68
SEG119 SEG120
4
SEG60 SEG59
PD16454A
BLOCK FUNCTIONS
(1) Registers (IR, DR) This LCD contains both an 8-bit instruction register (IR) and an 8-bit data register (DR). The IR register stores display clear instruction codes and display data RAM (DDRAM) and character generaotor RAM (CGRAM) addresses. The DR register temporarily stores data to be transferred to DDRAM and CGRAM. The IR and DR registers are selected with the register selector (RS) bit.
RS 0 1 Register selector IR DR
(2) Busy flag (BF) When BF = `1', this indicates that the LCD's internal circuit is currently operating. Therefore, after ascertaining that BF = `0', it is necessary to read the next instruction or display data. (3) Address counter (AC) The AC is a counter that sets addresses in DDRAM and CGRAM. When an address-setting instruction is written to the IR, the address value is set from the IR to the address counter. At the same time, which of DDRAM and CGRAM is selected is also determined. After display data is written in DDRAM or CGRAM, the address counter's address value is automatically incremented by 1. Nevertheless, since data in CGRAM consists of 7 bytes characters, the address value is incremented by 2 only when display data has been written to the 7th line. (4) Display data RAM (DDRAM) DDRAM is a RAM that stores display data consisting of 8-bit character codes. The capacity is 8 x 48 bits so that 48 characters can be stored. The correspondence between DDRAM addresses and display position on LCD is shown in Fig. 1.
5
PD16454A
Fig.1 Correspondence of DDRAM address and display position on LCD
1st digit 2 1st line 00 01 3 02 4 5 6 05 7 8 9 08 10 11 12 13 14 15 16 17 18 11 19 20 12 13 21 14 22 23 15 16 24 17
03 04
06 07
09 0A 0B 0C 0D 0E 0F 10 21 22 23 24 25 26 27 28
2nd line 18 19 1A 1B 1C 1D 1E 1F 20
29 2A 2B 2C 2D 2E 2F DDRAM address (hexadecimal)
(5) Character generator ROM (CGROM) CGROM is a ROM that generates 5 x 7-dot character patterns from 8-bit character codes, and can generate 160 different characters in total. The correspondence of CGROM addresses and character patterns to the ASCII code is shown in Fig.2. Fig.2 Correspondence of CGROM address data (character codes) and character patterns (00110010 "2")
CGROM address A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 Line position 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 1 A0 04 Character code (DDRAM output data) 03 02 01 00 ROM output data
Character code and character pattern correspondence is shown in Fig.3.
6
PD16454A
Fig.3. Character Code and Character Pattern Correspondence
Upper 4 bits Lower 4 bits
0000 CG RAM (1)
0010
0011
0100
0101
0110
0111
1010
1011
1100
1101
XXXX0000
XXXX0001
(2)
XXXX0010
(3)
XXXX0011
(4)
XXXX0100
(5)
XXXX0101
(6)
XXXX0110
(7)
XXXX0111
(8)
XXXX1000
(1)
XXXX1001
(2)
XXXX1010
(3)
XXXX1011
(4)
XXXX1100
(5)
XXXX1101
(6)
XXXX1110
(7)
XXXX1111
(8)
7
PD16454A
(6) Character generator RAM (CGRAM) CGRAM is a RAM that the user can use to freely define character patterns. Eight types of 5 x 7-dot character pattern definitions are possible. The CGRAM address values (character codes) of A10 to A3 in Fig.2 are 00H to 17H (8 types). Other values (line position, output data, etc.) are the same as in Fig.2. (7) Timing circuit The timing circuit generates timing signals to activate internal circuits. Retrieve timing of RAM needed for display and internal operation timing through access from the CPU are performed on a time-share basis and thus do not interfere with each other. Therefore, to change display characters on the LCD panel, even if DDRAM has been accessed, characters other than those that have been accessed do not flicker. (8) LCD-related circuit The LCD driver circuit consists of 14 common signal drivers and 120 segment signal drivers. Each driver is automatically controlled by an internal control circuit, and outputs a driving waveform corresponding to the character pattern. Serial data is always sent from the character pattern of the display data corresponding to the last DDRAM address, and the character pattern of the display data corresponding to the first DDRAM address (00H) is latched when inpout in the 120-bit shift register. LCD display positions are shown in Fig.1 of section (4) Display data RAM (DDRAM). Interface with CPU (data transfer) This LSI interfaces (transfers data) with CPU in 4-bit units (DB0 to DB3), but the internal register circuits (IR and DR) have 8-bit paths, therefore making it necessary to transfer 4-bit data twice. Assuming that the 8 bits of data are numbered D0 to D7, this data is transferred in the following sequence: first the upper 4 bits (D4 to D7), then the lower 4 bits (D0 to D3). The busy flag check is performed before the upper 4 bits are transferred, and is not necessary before transferring the 4 lower bits. If data is transferred without checking BF, taking 10 CLK cycles or more is necessary between previous 8-bit data transfer and next transfer (CLK = 1/fc).
8
PD16454A
INSTRUCTIONS
The instructions for this LSI are shown in Table 1 below. Table 1 Instruction List
Code RS Display On/Off 0 D7 0 D6 0 D5 0 D4 0 D3 1 D2 D D1 * D0 * Full display On/Off D : `1' (ON), `0' (OFF) CGRAM address set. Transfer of subsequent data is of CGRAM. DDRAM address set. Transfer of subsequent data is of DDRAM data. Data is written in CGRAM or DDRAM. The internal address counter (AC) is automatically incremented by one following data write.
Instruction
Description
CGRAM Address Set DDRAM Address Set
0
0
0
CGRAM address
0
1
*
DDRAM address
CGRAM/DDRAM Data Write
1
Write data However, because CGRAM data occupies D0 to D4, D5 to D7 are ignored.
Remark
* in the above table indicates that the value may be either 0 to 1.
Initialization using the reset signal (RESET) When the reset signal (RESET) is activated (RESET = 0) for 10 CLK cycles (CLK = 1/fc) or more, initialization is performed as follows. (1) Display ON/OFF Set to OFF (D = 0) (2) DDRAM address set Set to DDRAM address 00H When data write is performed under this condition, data is written to DDRAM address 00H.
9
PD16454A
ABSOLUTE MAXIMUM RATINGS (Ta = +25 C, GND1 = GND2 = 0 V)
Parameter Logic Supply Voltage Driver Input Voltage Logic Output Voltage Driver Supply Voltage Driver's Driver Input Voltage Driver's Driver Output Voltage Driver Output Voltage Storage Temperature Symbol VCC VI VO1 VDD V2 to V5 V1 VO2 Tstg Ratings -0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to +15 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -40 to +125 Unit V V V V V V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Logic Supply Voltage Operating Ambient Temperature Symbol VCC Topt MIN. 4.75 -30 TYP. 5 25 MAX. 5.25 85 Unit V C
10
PD16454A
DC CHARACTERISTICS (Ta = -30 to +85 C, VCC = 5 V 5 5%)
Parameter High-Level Input Voltage 1 Low-Level Input Voltage 1 High-Level Input Voltage 2 Low-Level Input Voltage 2 Hysteresis voltage High-Level Output Voltage Low-Level Output Voltage High-Level Input Leak Current High-Level Input Leak Current Low-Level Input Lead Current Common Output Impedance Segment Output Impedance Logic Supply Voltage (Total consumption) Symbol VIH1 VIL1 VIH2 VIL2 VH VOH VOL IIH1 IIH2 IIL RCOM RSEG ICC IOH = -1 mA IOL = 1 mA TEST excluded, VIN = VCC TEST, VIN = VCC VIN = 0 V IO = 50 A IO = 50 A R1 = 33 k RP = 27 k RB = 22 k fC = 250 kHz Driver Supply Voltage (Boosted voltage) VDD R1 = 33 k RP = 27 k RB = 22 k External capacitor of 1 F IOH = -1 mA VIN (+) = VDD VIN (-) = 0 V Low-Level Output Voltage (V1 pin) VOL2 IOL = 10 A VIN (+) = 0 V VIN (-) = VDD 0.1 VDD V 1.9 VCC 2 VCC V -1 1.5 1.5 1 58 76 2 0.9 VDD 0.1 VCC 1 6 0.1 E, RESET, CLK input 0.8 VCC 0.2 VCC Conditions E, RESET, CLK, input excluded MIN. 0.7 VCC 0.3 VCC TYP. MAX. Unit V V V V V V V
A
mA
A
k k mA
High-Level Output Voltage (V1 pin)
VOH2
0.9 VDD
V
TYP. is reference value at Ta = +25 C.
+ -
VIN (+)
VIN (-)
V1
V2
V3
V4
V5
RB Rt +5 V R1 Rp
RB
RB
RB
RB
Rt : Thermostat
11
PD16454A
AC CHARACTERISTICS (Ta = -30 to +85 C, VCC = 5 V 5%)
Parameter Operating Frequency Enable Cycle Time Enable Pulse Width RS * E Setup Time RS * E Hold Time Data Setup Time Data Hold Time Symbol fC tCYCE PWE tRSES tRSEH tDS tDH Conditions MIN. 160 1 000 450 100 100 100 100 TYP. 250 MAX. 500 Unit kHz ns ns ns ns ns ns
TYP. is reference value at Ta = +25 C.
AC CHARACTERISTIC WAVEFORM Write Operation
RS
tRSES
PWE
tRSEH
E
tDS
tDH
DB0 to DB3
Valid Data
tCYCE
12
PD16454A
OSCILLATION FREQUENCY and LCD FRAME FREQUENCY CORRESPONDENCE
The correspondence between the oscillation frequency of 250 kHz and the LCD frame frequency is shown in Fig.4 below. Fig.4 Oscillation Frequency and LCD Frame Frequency Correspondence
120 Clocks
1 V1 V2 V3 COM1 V4 V5 GND2
2
3
14
1
2
3
14
1
2
1 frame = 4 s x 120 x 14 = 6 720 s = 6.72 ms
Signal COM Display Mode Lit Not lit SEG Lit Not lit + GND2 V2 GND2 V4 - V1 V5 V1 V3
13
PD16454A
REFERENCE 1 : STANDARD TCP DRAWING (PD16454AN-051)
MAX. 0.9
13.475
13.475
P0.5 = 0.01 x 48 = 24.0 0.05
P0.4 0.01 x 40 = 16.0 0.035 W0.16 0.03
4.75
(0.735)
,,,,
1.42 0.03
1.42 0.03
P0.4 0.01 x 40 = 16.0 0.035 W0.16 0.03
P0.5 = 0.01 x 48 = 24.0 0.05
13.475
From center of tape
Note 1. Measurements between brackets are for referency only. 2. Non-specified tolerances are 0.05 mm. 3. This drawing is viewed from wire-patterned face.
Test Pad and Alignment Pattern Details
13.475 12.7 11.8 0.5 0.65 0.65
13.475 0.5 0.7
0.8 0.015
0.6 0.015
0.125
0.1 13.475
31.82 -0.07 11.8 12.7
From center of tape
14
+0.04
REFERENCE 2 : TCP SHIPPING RELL ( 405 mm)
W
C
B
A
E D
W1 W2
Symbol A B C D E W W W W1 W2
Size (mm)
*:Tape width
405 2.0 105 25.9 0.5 17.9 0.5
50 +1.0 -0 (35)* (48)* (70)* 37 1.5 50 1.5 72 1.5
PD16454A
3 0.5 W + 2W1
15
PD16454A
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96. 5

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