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Features
* Four Short-circuit-protected High-side Drivers with a Maximum Current Capability of
50 mA Each
* Four Short-circuit-protected Low-side Drivers with a Maximum Current Capability of * * * * * * * * *
50 mA Each ON Resistance High Side Ron < 10 Versus Total Temperature Range ON Resistance Low Side Ron < 7 Versus Total Temperature Range Short-circuit Detection of Each Driver Stage Disabling of Driver Stages in the Case of Short-circuit and Overtemperature Detection Independent Control of Each Driver Stage via an 8-bit Shift Register Status Output Reports Short-circuit Condition Status Output Reports when All Loads Are Switched Off Timing of Status Output Reset Signalizes Failure Mode Temperature Protection in Conjunction with Short-circuit Detection
Description
The U6820BM is a driver interface in BCDMOS technology with 8 independent driver stages having a maximum current capability of 50 mA each. Its partitioning into 4 high-side and 4 low-side driver stages allows an easy connection of either 4 halfbridges or 2 H-bridges on the pc board. The U6820BM communicates with a microcontroller via an 8-bit serial interface. Integrated protection against short circuit and overtemperature give added value. EMI protection and 2-kV ESD protection together with automotive qualification referring to conducted interference (ISO/TR 7637/1) make this IC ideal for both automotive and industrial applications. Figure 1. Block Diagram
V 6 CC HS4 16 HS3 9 HS2 8 HS1 1
Dual Quad BCDMOS Driver IC U6820BM
Current limiter V 14 CC
Current limiter
Current limiter
Current limiter 3 VS
STATUS
CS CLK DI
11 12
H S 4
H S 3
H S 2
H S 1
L S 4
L S 3
L S 2
L S 1
Thermal protection Control logic
V CC
V
CC
13
Input Register
Power-on reset
V
CC
5 Current limiter Current limiter Current limiter Current limiter
GND S
4 GND CC
15 LS4
10 LS3
7 LS2
2 LS1
Rev. 4527A-BCD-03/02
1
Pin Configuration
Figure 2. Pinning SO16
HS1 LS1 VS GNDCC GNDS VCC LS2 HS2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 HS4 LS4 STATUS DI CLK CS LS3 HS3
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol HS1 LS1 VS GNDCC GNDS VCC LS2 HS2 HS3 LS3 CS CLK DI STATUS LS4 HS4 Function Output high side 1 Output low side 1 Supply voltage 6 V to 18 V Digital ground Power ground Supply voltage 5 V (external) Output low side 2 Output high side 2 Output high side 3 Output low side 3 Set supply status (chip select) Clock line for 8-bit control shift register Data line for 8-bit control shift register Status output (H = fault, diagnostic "H" if all driver stages are switched off) Output low side 4 Output high side 4
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U6820BM
4527A-BCD-03/02
U6820BM
Description of the Control Interface to the Microcontroller
The serial-parallel interface basically includes an 8-bit shift register (SR), an 8-bit command register (CR) and a 4-bit counter. The data input takes place with commands at Pins DI (data input), CS (chip select) and CLK (clock). With a falling edge at CLK, the information at DI is transferred into the SR. The first information written into the SR is the least significant bit (LSB). The Pin STATUS is used for diagnostic purposes and reports any fault condition to the microcontroller. The input CS in accordance with the CR controls the serial interface. A high level at CS disables the SR. With a falling edge at CS, the SR is enabled. The CR control allows only the first 8 bits to be transferred into the SR, and further clocks at CLK are ineffective. If a rising edge occurs at CS after 8 clocks precisely, the information from the SR is transferred into the CR. If the number of clock cycles during the low phase of CS was less or more than eight transitions, no transfer will take place. A new command switches the output stages on or off immediately. Each output stage is controlled by one specific bit of the CR. Low level means "supply off" or inactive, and high level means "supply on" or active. If all 8 bits are at a low level, the output stages will be set into standby mode. If one of the output stages detects a short circuit and additionally overtemperature condition, the corresponding control bit in the CR is set to low. This reset has priority over an external command to CR, thus, this does not affect the 1st control bit. The priority protects the IC against overtemperature by activating the temperature shut down immediately.
The STATUS Output
The STATUS output is at low level during normal operation. If one or more output stages detect short circuit or if overtemperature is indicated, the STATUS output changes to high level (OR-connection). For diagnostic purposes (self test of the status output), the status output can also be brought into high level during standby mode.
Timing of the Status Output Reset Signalizes the Failure Mode
The use of different reset conditions at the STATUS output simplifies the failure analysis during normal operation, and is also beneficial during testing. The storage content can be used for STATUS output. It is indicated and latched immediately with the rising edge of CS at STATUS output if less than 8 clocks were received during the low phase of CS. The reset is initiated by the falling edge of the 8th clock (bit 7) of the next data input. Also, the appearance of more than 8 clocks is latched and indicated at STATUS by the rising edge of the 9th clock. The reset is initiated by the falling edge of the 2nd clock (bit 1) of the next data input. The detection of overtemperature is latched internally. It is reset by the falling edge of the 4th clock (bit 3) of a data transfer if overtemperature is no longer present.
Power-on Reset
After switching on the supply voltage, all data latches are reset and the outputs are switched off. The typical power-on reset threshold is VCC = 3.7 V. The outputs are activated after the first data transfer.
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4527A-BCD-03/02
Short-circuit Protection
The current of the output stages is limited by an active feedback control. Short circuit at one output stage sets the diagnostic Pin 14 (STATUS) to high. In case of both conditions, short circuit at one of the outputs and temperature detection, the affected output is switched off selectively. It will be activated again after the first new data transfer. Clamping diodes and FETs are integrated to protect the IC against too high or too low voltages at the outputs. They prevent the IC from latch up and parasitic currents which may exceed power dissipation. The IC is protected by an overtemperature detection. As soon as the junction temperature Tj = 155C typically is exceeded, the diagnostic Pin 14 (STATUS) is set "high". General overtemperature detection along with short-circuit condition at a specific output result in temperature shut down at that specific output. After temperature shut down, the data input register has to be set again with a hysteresis of typically T = 15 K (Tj = 140C). All output stages are protected against electrostatic discharge up to 5 kV (HBM) with external components (see Figure 5), all other pins are protected up to 2 kV (HBM).
Inductance Protection
Temperature Protection
ESD Protection
Table 1. Timing of the STATUS Output
Shift Register Command Register Low-side Switch Condition LS1 All out = OK All on = OK E.g. one on = OK Short at LS3 Temp & short at HS4 VVCC < 3.7 V = P-ON CS with less 8 CLK CS with more 8 CLK off on off off on off x x LS2 off on off on on off x x LS3 off on off on on off x x LS4 off on off on off off x x HS1 off on off on on off x x HS2 off on off on on off x x HS3 off on off on on off x x HS4 off on on on on off x x Set H L L H H H H H No short New CS4 P-ON, CS New CS 8 New CS 2 Reset New CS High-side Switch Status
0000000000000000 1111111111111111 0000000100000001 0111111101111111 1111111111101111 1100001100000000 11100011xxxxxxxx 00011100xxxxxxxx
4
U6820BM
4527A-BCD-03/02
U6820BM
Figure 3. Data Transfer Timing Diagram
t t CLKP t
CSCLK
CLKH 90 %
CLK
LSB
tr
tf
90 % 10% MSB 50%
t CLKCS
t
CLKL
50%
DI
t DICLK t DIH/L
t CS
CS
50%
t
CLKCSH
Table 2. AC Characteristics for Testing
Specification tr (rise) tf (fall) tCLKP tCLKH tCLKL tCLKCS tCSCLK tDICLK tDIH/L tCLKCSH tCS Conditions 10% to 90% VCC on CLK, DI and CS 10% to 90% VCC on CLK, DI and CS 1/2 VCC 1/2 VCC 1/2 VCC 1/2 VCC 1/2 VCC 1/2 VCC 1/2 VCC 1/2 VCC 1/2 VCC 250 100 100 150 100 80 100 100 250 Minimum Maximum 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns
5
4527A-BCD-03/02
Figure 4. Block Diagram of the Control Interface
Serial-Parallel Interface
EN
D
DFF
Q
D
DFF
Q
NQ
D
DFF
Q
CS
11
CL
1
2
4
8
R
CL
R
R
R Q0
Counter
CL NQ CL NQ
Q1
Q2
h if 4
Q3
h if 8
8CLK
DFF
D Q
CLK
h if 2
POR
norm=0
R
CL NQ
CLK
12 13
EN
CL
DIN
H4
H3
H2
H1
L4
L3
L2
L1
LSB
Shift register SR
DI
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
Load CR
CL
Command register BR
NR NQ NR NQ NR NQ NR NQ NR NQ NR NQ NR NQ
NR NQ
DFF
D Q
P-ON-Reset
CL
R
NQ
Th-protection
14
All norm = 0
STATUS norm = 0
ISC_HS4
ISC_HS2
ISC_HS1
ISC_HS3
ISC_LS2
ISC_LS4
ISC_LS3
ISC_LS1
HS3_ON
HS2_ON
HS1_ON
HS4_ON
LS4_ON
LS3_ON
LS2_ON
LS1_ON
6
U6820BM
4527A-BCD-03/02
STD_BY
norm = 0
U6820BM
Absolute Maximum Ratings
Parameters Supply voltage Logic supply voltage Logic input voltage Logic output voltage Input current Output current (internally limitted) Junction temperature range Storage temperature range Pin 3 6 11, 12 13 14 3 6 1-2, 8-11, 15-16 Symbol VVS VVCC CS, CLK, DI STATUS IVS IVCC I 1H-4H and I 1L-4L Tj Tstg 30 -40 -55 Minimum -0.3 -0.3 -0.3 -0.3 Maximum +40 +7 VVCC + 0.5 VVCC + 0.3 0.2 5 65 +150 +150 Unit V V V V mA mA mA C C
Thermal Resistance
Parameters Junction ambient Junction case Symbol RthJA RthJC Value 110 26 Unit K/W K/W
Operating Range
Parameters Supply voltage Logic supply voltage Logic input voltage low Logic input voltage high Logic output voltage (1 mA load) Clock frequency Junction temperature range Pin 3 6 11, 12, 13 11, 12, 13 14 Symbol VVS VVCC CS, CLK, DI CS, CLK, DI STATUS fCLK Tj Value 6 to 18 4.5 to 5.5 -0.2 to (0.2 x VVCC) (0.7 x VVCC) to (VVCC + 0.3) 0.5 to (VVCC - 1) 5 -40 to +150 Unit V V V V V MHz C
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4527A-BCD-03/02
Electrical Characteristics
7 V < VVS < 40 V; 4.5 V < VVCC > 5.5 V; -40C < Tj < 150C; unless otherwise specified
No. 1 1.1 1.2 1.3 1.4 2 2.1 2.2 2.3 3 3.1 3.2 3.3 3.4 3.5 Parameters Current Consumption Supply current VS Supply current VCC Power-on reset threshold Power-on reset delay time Thermal Shutdown Thermal shutdown set Thermal shutdown reset Thermal hysteresis Output Specifications (1L - 4L, 1H - 4H) On-resistance low On-resistance high Output leakage current lowside Output leakage current highside Output leakage steepness Iout = 26 mA, Tj = 125C Iout = 26 mA, Tj = 125C VLSIDE 1-4 = 17.5 V VHSIDE 1-4 = 0.5 V 2, 7, 10, 15 1, 8, 9, 16 2, 7, 10, 15 1, 8, 9, 16 1-2, 7-10, 15-16 1, 8, 9, 16 2, 7, 10, 15 11-13 11-13 11-13 (internal pull-up resistor: 30 k to 140 k) I = 1 mA I = 1 mA 11-13 Ii 300 A A RDSONLOW RDSONHIGH ILOWSIDE IHIGHSIDE dVOUT/ dt IHIGHSIDE ILOWSIDE 50 200 3 4 4 6.25 7 10 5 -5 A A A A A A t j PW set t j PW reset Dt 140 130 155 135 20 165 155 C C K A A A After switching on VCC No external load No external load 3 6 6 6 IVS IVCC VCC POR Td POR 3.4 60 3.7 95 0.2 5 4.0 130 mA mA V s A A A D Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
400
mV/s
D
3.6 3.7 4 4.1 4.2 4.3 4.4
Over current limitation highside Over current limitation lowside Serial Interface - Inputs: CS, CLK and DATA Input voltage low level threshold Input voltage high level threshold Hysteresis of input voltage Pull-down current
27 27
45 45
95 80
mA mA
A A
VILOW VIHIGH Vi 0.7x VVCC 300
0.2x VVCC
V V mV
A A A
5 5.1 5.2
Serial Interface - Output: STATUS Output voltage low level Output voltage high level VOLOW VOHIGH VVCC-1 0.5 VVCC V V A A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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U6820BM
4527A-BCD-03/02
U6820BM
Figure 5. Application Circuit
VCC
5V
Typical application with 4 Hall-ICs for rotational speed detection +
33F 100nF 4.7nF R* HS4
RR LR RF LF 4.7nF R* HS3 4.7nF HS2 R* 4.7nF R* HS1
VBATT
12 V
VCC 6
16
9
8
1
U6820BM
VCC
STATUS
&XUUHQW OLPLWHU
&XUUHQW OLPLWHU
&XUUHQW OLPLWHU
&XUUHQW OLPLWHU
3
VS
+
100nF 47F
14
C
CS CLK DI
11 12
H S 4
H S 3
H S 2
H S 1
L S 4
L S 3
L S 2
L S 1
Thermal protection Control logic
VCC
VCC
13
Input register
Power-on reset
VCC 5
GNDS
&XUUHQW OLPLWHU
&XUUHQW OLPLWHU
&XUUHQW OLPLWHU
&XUUHQW OLPLWHU
4
GNDCC 4.7nF
15
LS4
10
LS3
7
LS2
2
LS1
4.7nF 100 100
4.7nF 100
4.7nF 100 27k R * = ca. 4 Ohm (I Lim for inv. supply)
Sensor control 27k
27k 27k
Note:
It is strongly recommended to connect the blocking capacitors at VS and VCC as close as possible to the power supply and GND pins. Recommended value for VS is less than 100 F electrolytic in parallel with 100 nF ceramic. Value for electrolytic capacitor depends on external loads, noise and surge immunity efforts. Recommended value for VCC is 33 F electrolytic in parallel with 100 nF ceramic. The 4- resistors connected to the Pins HS1 - HS4 support the protection in case of a short circuit of these pins to VBatt.
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4527A-BCD-03/02
Ordering Information
Extended Type Number U6820BM-FP Package SO16 Remarks
Package Information
Package SO16
Dimensions in mm
10.0 9.85 5.2 4.8 3.7 1.4 0.4 1.27 8.89 16 9 0.25 0.10 0.2 3.8 6.15 5.85
technical drawings according to DIN specifications
13036
1
8
10
U6820BM
4527A-BCD-03/02
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4527A-BCD-03/02 xM

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