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TC7135
4-1/2 Digit A/D Converter
Features
* * * * * * * * * * * * * Low Rollover Error: 1 Count Max Nonlinearity Error: 1 Count Max Reading for 0V Input True Polarity Indication at Zero for Null Detection Multiplexed BCD Data Output TTL-Compatible Outputs Differential Input Control Signals Permit Interface to UARTs and Microprocessors Blinking Display Visually Indicates Overrange Condition Low Input Current: 1 pA Low Zero Reading Drift: 2 V/C Auto-Ranging Supported with Overrange and Underrange Signals Available in PDIP and Surface-Mount Packages
General Description
The TC7135 4-1/2 digit A/D Converter (ADC) offers 50 ppm (1 part in 20,000) resolution with a maximum nonlinearity error of 1 count. An auto-zero cycle reduces zero error to below 10 V and zero drift to 0.5 V/C. Source impedance errors are minimized by a 10 pA maximum input current. Rollover error is limited to 1 count. Microprocessor-based measurement systems are supported by the BUSY, STROBE and RUN/HOLD control signals. Remote data acquisition systems with data transfer via UARTs are also possible. The additional control pins and multiplexed BCD outputs make the TC7135 the ideal converter for display or microprocessor-based measurement systems.
Applications
* Precision Analog Signal Processor * Precision Sensor Interface * High Accuracy DC Measurements
Functional Block Diagram
Set VREF = 1V VREF IN 5V 1 2 V-
TC7135
28 UNDERRANGE REF IN 27 OVERRANGE 3 ANALOG 26 STROBE COMMON Analog GND 4 25 RUN/HOLD INT OUT 1 F 24 0.47 F 5 DIGTAL GND AZ IN 23 6 BUFF OUT POLARITY 22 100 k 7 CLOCK IN CREF- Signal 21 1 F 8 100 k BUSY Input CREF+ 9 20 (LSD) D1 -INPUT 19 0.1 F 10 D2 +INPUT 18 11 D3 +5V V+ 12 17 D4 D5 (MSD) 13 16 (MSB) B8 B1 (LSB) 14 15 B4 B2 100 k
Clock Input 120 kHz
2004 Microchip Technology Inc.
DS21460C-page 1
TC7135
Package Types
28-Pin PLCC
INT OUT ANALOG COM REF IN STROBE
44-Pin MQFP
DIGITAL GND RUN/HOLD POLARITY CLOCK IN
V-
OR
UR
NC
NC
NC
AZ IN 5 BUFF OUT 6 REF CAP- 7 REF CAP+ 8 -INPUT 9 +INPUT 10 V+ 11 12 13 14 15 16 17 18 D4 (MSD) D5 (MSB) B8 (LSB) B1 D3 B2 B4
25 RUN/HOLD 24 DIGTAL GND 23 POLARITY NC 34 NC 35 STROBE 36 OVERRANGE 37 UNDERRANGE 38 V- 39 REF IN 40 COMMON ANALOG 41 NC 42 NC 43 NC 44
33 32 31 30 29 28 27 26 25 24 23 22 NC 21 NC 20 D3 19 D4 18 B8
TC7135
22 CLOCK IN 21 BUSY 20 D1 (LSD) 19 D2
TC7135
NC 17 B4 16 B2 15 B1 14 D5 13 NC 12 NC NC NC NC NC NC 48 NC 47 NC 46 NC 45 D3 44 D4 43 B8 42 B4 41 B2 40 NC 39 B1 38 D5 37 NC 36 NC 35 NC 34 NC 33 NC V+
D1
1 NC
2
INT OUT
3
4 BUFF OUT
D2
8
4
3
2
1 28 27 26
BUSY
5 CREF-
6 CREF+
7
-INPUT
9 10 11 V+ NC D2
28-Pin PDIP
RUN/HOLD STROBE V- REF IN ANALOG COM INT OUT AZ IN BUFF OUT CREF- CREF+ -INPUT 1 2 3 4 5 6 7 8 9 28 UNDERRANGE 27 OVERRANGE NC NC NC NC 26 STROBE 25 RUN/HOLD 24 DIGiTAL GND 23 POLARITY NC 1 NC 2 NC 3 NC 4 NC 5 NC 6 OVERRANGE 7 UNDERRANGE 8 NC 9 V- 10 REF IN 11 ANALOG COM 12 NC 13 NC 14 NC 15 NC 16
64-Pin MQFP
CLOCK IN
DGND
POL
BUSY
+INPUT -INPUT D1
AZ IN
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 l
TC7135
22 CLOCK IN 21 BUSY 20 D1 (LSD) 19 D2 18 D3 17 D4 16 B8 (MSB) 15 B4
+INPUT 10 V+ 11 (MSD) D5 12 (LSB) B1 13 B2 14
TC7135
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CREF- NC NC NC NC AZ IN NC CREF+ NC INT OUT BUFF OUT +INPUT
NOTE: NC = No internal connection.
DS21460C-page 2
NC
2004 Microchip Technology Inc.
NC
TC7135
1.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Positive Supply Voltage.....................................................+6V Negative Supply Voltage ...................................................- 9V Analog Input Voltage (Pin 9 or 10) ...............V+ to V- (Note 2) Reference Input Voltage (Pin 2) ................................. V+ to VClock Input Voltage ................................................... 0V to V+ Operating Temperature Range .......................... 0C to +70C Storage Temperature Range ........................ -65C to +150C Package Power Dissipation; (TA 70C) 28-Pin PDIP .......................................................... 1.14 28-Pin PLCC ......................................................... 1.00 44-Pin MQFP.......................................................................... 64-Pin MQFP ........................................................ 1.14 Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25C, FCLOCK = 120 kHz, V+ = +5V, V- = -5V. (see Functional Block Diagram). Parameters Analog Display Reading with Zero Volt Input Zero Reading Temperature Coefficient Full Scale Temperature Coefficient Nonlinearity Error Differential Linearity Error Display Reading in Ratiometric Operation Full Scale Symmetry Error (Rollover Error) Input Leakage Current Noise Digital Input Low Current Input High Current Output Low Voltage Output High Voltage; B1, B2, B4, B8, D1 -D5 Busy, Polarity, Overrange, Underrange, Strobe Clock Frequency Note 1: 2: 3: 4: 5: 6: 7: 8: FCLK IIL IIH VOL VOH -- -- -- 2.4 4.9 10 0.08 0.2 4.4 4.99 100 10 0.4 5 5 A A V V V VIN = 0V VIN = +5V IOL = 1.6 mA IOH = 1 mA IOH = 10 A FSE IIN eN TCZ TCFS NL DNL -0.0000 -- -- -- -- +0.9996 -- -- -- 0.0000 0.5 -- 0.5 0.01 +0.0000 2 5 1 -- Display Reading V/C ppm/C Count LSB Display Reading Count pA VP-P Note 2, Note 3 VIN = 0V, (Note 4) VIN = 2V, (Note 4, Note 5) Note 6 Note 6 VIN = VREF, (Note 2) -VIN = +VIN, (Note 7) Note 3 Peak-to-Peak Value not Exceeded 95% of Time Sym Min. Typ. Max. Units Conditions
+0.9999 +1.0000 0.5 1 15 1 10 --
0
200
1200
kHz
Note 8
Limit input current to under 100 A if input voltages exceed supply voltage. Full-scale voltage = 2V VIN = 0V 30C TA +70C External reference temperature coefficient less than 0.01 ppm/C. -2V VIN +2V. Error of reading from best fit straight line. IVIN| = 1.9959 Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased errors result at higher operating frequencies.
2004 Microchip Technology Inc.
DS21460C-page 3
TC7135
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, TA = +25C, FCLOCK = 120 kHz, V+ = +5V, V- = -5V. (see Functional Block Diagram). Parameters Power Supply Positive Supply Voltage Negative Supply Voltage Positive Supply Current Negative Supply Current Power Dissipation Note 1: 2: 3: 4: 5: 6: 7: 8: V+ VI+ IPD 4 -3 -- -- -- 5 -5 1 0.7 8.5 6 -8 3 3 30 V V mA mA mW FCLK = 0 Hz FCLK = 0 Hz FCLK = 0 Hz Sym Min. Typ. Max. Units Conditions
Limit input current to under 100 A if input voltages exceed supply voltage. Full-scale voltage = 2V VIN = 0V 30C TA +70C External reference temperature coefficient less than 0.01 ppm/C. -2V VIN +2V. Error of reading from best fit straight line. IVIN| = 1.9959 Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased errors result at higher operating frequencies.
DS21460C-page 4
2004 Microchip Technology Inc.
TC7135
2.0 PIN DESCRIPTIONS
The description of the pins are listed in Table 2-1.
TABLE 2-1:
Pin Number 28-Pin PDIP, 28-Pin PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
PIN FUNCTION TABLE
Pin Number 44-Pin MQFP* 39 40 41 2 3 4 5 6 7 8 9 14 15 16 17 18 19 20 25 26 27 Pin Number 64-Pin MQFP* 10 11 12 18 20 22 23 26 28 30 32 38 39 41 42 43 44 45 52 53 54 Symbol V- REF IN ANALOG COMMON INT OUT AZ IN BUFF OUT CREF- CREF+ -INPUT +INPUT V+ D5 B1 B2 B4 B8 D4 D3 D2 D1 BUSY Description Negative power supply input. External reference input. Reference point for REF IN. Integrator output. Integrator capacitor connection. Auto-zero inpt. Auto-zero capacitor connection. Analog input buffer output. Integrator resistor connection. Reference capacitor input. Reference capacitor negative connection. Reference capacitor input. Reference capacitor positive connection. Analog input. Analog input negative connection. Analog input. Analog input positive connection. Positive power supply input. Digit drive output. Most Significant Digit (MSD) Binary Coded Decimal (BCD) output. Least Significant bit (LSb). BCD output. BCD output. BCD output. Most Significant bit (MSb). Digit drive output. Digit drive output. Digit drive output. Digit drive output. Least Significant Digit (LSD). Busy output. At the beginning of the signal-integration phase, BUSY goes high and remains high until the first clock pulse after the integrator zero crossing. Clock input. Conversion clock connection. Polarity output. A positive input is indicated by a logic high output. The polarity output is valid at the beginning of the reference integrate phase and remains valid until determined during the next conversion. Digital logic reference input. Run/Hold input. When at a logic high, conversions are performed continuously. A logic low holds the current data as long as the low condition exists. Strobe output. The STROBE output pulses low in the center of the digit drive outputs. Overrange output. A logic high indicates that the analog input exceeds the full-scale input range. Underrange output. A logic high indicates that the analog input is less than 9% of the full-scale input range.
22 23
28 29
55 57
CLOCK IN POLARITY
24 25
30 31
58 59
DGND RUN/HOLD
26 27 28
36 37 38
60 7 8
STROBE OVERRANGE UNDERRANGE
* Pins not identified or documented are NC (no connects).
2004 Microchip Technology Inc.
DS21460C-page 5
TC7135
3.0 DETAILED DESCRIPTION
All pin designations refer to the 28-pin PDIP package. The dual-slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. An inherent benefit is noise immunity. Noise spikes are integrated, or averaged, to zero during the integration periods. Integrated ADCs are immune to the large conversion errors that plague successive approximation converters in high-noise environments (see Figure 3-1).
Analog Input Signal
3.1
Dual-Slope Conversion Principles
The TC7135 is a dual-slope, integrating A/D converter. An understanding of the dual-slope conversion technique will aid in following the detailed TC7135 operational theory. The conventional dual-slope converter measurement cycle has two distinct phases: 1. 2. Input signal integration. Reference voltage integration (de-integration).
Integrator + Switch Drive Comparator +
The input signal being converted is integrated for a fixed time period. Time is measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal. In a simple dual-slope converter, a complete conversion requires the integrator output to "ramp-up" and "ramp-down". A simple mathematical equation relates the input signal, reference voltage and integration time:
REF Voltage
Phase Control Polarity Control
Clock Control Logic
Display Integrator Output VIN VIN Variable Reference Integrate Time
Counter
VREF 1/2 VREF
EQUATION 3-1:
VREF T DEINT 1 -T ----------------------- INT V IN ( T )DT = ------------------------------0 RINT C INT RINT C INT Where: VREF TINT TDEINT = = = Reference voltage Signal integration time (fixed) Reference voltage integration time (variable)
Fixed Signal Integrate Time
FIGURE 3-1:
Basic Dual-Slope Converter.
3.2
TC7135 Operational Theory
The TC7135 incorporates a system zero phase and integrator output voltage zero phase to the normal twophase dual-slope measurement cycle. Reduced system errors, fewer calibration steps and a shorter overrange recovery time result. The TC7135 measurement cycle contains four phases: 1. 2. 3. 4. System zero. Analog input signal integration. Reference voltage integration. Integrator output zero.
For a constant VIN:
EQUATION 3-2:
V REF T DEINT V IN = ------------------------------T INT
Internal analog gate status for each phase is shown in Figure 3-1.
TABLE 3-1:
System Zero
INTERNAL ANALOG GATE STATUS
SWI -- Closed -- -- SWRI+ -- -- Closed* -- SWRI-- -- -- -- SWZ Closed -- -- -- SWR Closed -- -- -- SW1 Closed -- Closed Closed SWIZ -- -- -- Closed Reference Figures Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5
Conversion Cycle Phase
Input Signal Integration Reference Voltage Integration Integrator Output Zero
* Assumes a positive polarity input signal. SWRI would be closed for a negative input signal.
DS21460C-page 6
2004 Microchip Technology Inc.
TC7135
3.2.1 SYSTEM ZERO 3.2.3
During this phase, errors due to buffer, integrator and comparator offset voltages are compensated for by charging CAZ (auto-zero capacitor) with a compensating error voltage. With a zero input voltage, the integrator output will remain at zero. The external input signal is disconnected from the internal circuitry by opening the two SWI switches. The internal input points connect to the ANALOG COMMON pin. The reference capacitor charges to the reference voltage potential through SWR. A feedback loop, closed around the integrator and comparator, charges the CAZ capacitor with a voltage to compensate for buffer amplifier, integrator and comparator offset voltages (see Figure 3-2).
SWI +IN SWRISWRI+ Analog Input Buffer RINT + - SWIZ SWZ - + SWZ
Integrator
REFERENCE VOLTAGE INTEGRATION
The previously charged reference capacitor is connected with the proper polarity to ramp the integrator output back to zero (see Figure 3-4). The digital reading displayed is:
EQUATION 3-3:
[ Differential Input ] Reading = 10, 000 ---------------------------------------------VREF
Analog Input Buffer RINT + - SWIZ SWZ
SWI +IN SWRISWRI+
CINT CSZ Comparator - + + To Integrator - Digital Section
CINT CSZ Comparator + - To Digital Section
SWRI+
SWZ Analog Common SWI IN
SWRI-
REF IN
SWR
CREF
SWZ
SWRI+
SWZ Analog Common SWI IN
SWRI-
REF IN
SWR
CREF
SW1
Switch Open Switch Closed
SW1
Switch Open Switch Closed
FIGURE 3-4: Integration Cycle. 3.2.4
Reference Voltage
FIGURE 3-2: 3.2.2
System Zero Phase.
INTEGRATOR OUTPUT ZERO
ANALOG INPUT SIGNAL INTEGRATION
The TC7135 integrates the differential voltage between the +INPUT and -INPUT pins. The differential voltage must be within the device Common mode range; -1V from either supply rail, typically. The input signal polarity is determined at the end of this phase.
SWI +IN SWRI+ SWRIAnalog Input Buffer RINT + - SWIZ SWZ
This phase ensures the integrator output is at 0V when the system zero phase is entered. It also ensures that the true system offset voltages are compensated for. This phase normally lasts 100 to 200 clock cycles. If an overrange condition exists, the phase is extended to 6200 clock cycles (see Figure 3-5).
Analog Input Buffer RINT + - SWIZ SWZ
SWI +IN SWRI+ SWRI-
CINT CSZ Comparator - + + - To Integrator Digital Section
CINT CSZ Comparator + + - To Integrator Digital Section - REF IN SWR
CREF SWRI+ SWRI-
SWRI+
SWRI-
REF IN
SWR
CREF
SWZ Analog Common SWI IN
SWZ
SWZ Analog Common SWI IN
SWZ
SW1
Switch Open Switch Closed
SW1
Switch Open Switch Closed
FIGURE 3-5: Phase.
Integrator Output Zero
FIGURE 3-3: Phase.
Input Signal Integration
2004 Microchip Technology Inc.
DS21460C-page 7
TC7135
4.0
4.1
ANALOG SECTION FUNCTIONAL DESCRIPTION
Differential Inputs
4.3
Reference Voltage Input
The reference voltage input (REF IN) must be a positive voltage with respect to ANALOG COMMON. A reference voltage circuit is shown in Figure 4-1.
V+ V+
The TC7135 operates with differential voltages (+INPUT, pin 10 and -INPUT, pin 9) within the input amplifier Common mode range, which extends from 1V below the positive supply to 1V above the negative supply. Within this Common mode voltage range, an 86 dB Common mode rejection ratio is typical. The integrator output also follows the Common mode voltage and must not be allowed to saturate. A worstcase condition exists, for example, when a large positive Common mode voltage with a near full scale negative differential input voltage is applied. The negative input signal drives the integrator positive when most of its swing has been used up by the positive Common mode voltage. For these critical applications, the integrator swing can be reduced to less than the recommended 4V full scale swing, resulting in some loss of accuracy. The integrator output can swing within 0.3V of either supply without loss of linearity.
TC7135
REF IN ANALOG COMMON
10 k
MCP1525 2.5 VREF 1 F
10 k
Analog Ground
FIGURE 4-1: Reference.
Using An External
4.2
Analog Common Input
The ANALOG COMMON pin is used as the -INPUT return during auto-zero and de-integrate. If -INPUT is different from ANALOG COMMON, a Common mode voltage exists in the system. However, this signal is rejected by the excellent CMRR of the converter. In most applications, -INPUT will be set at a fixed, known voltage (power supply common, for instance). In this application, ANALOG COMMON should be tied to the same point, thus removing the Common mode voltage from the converter. The reference voltage is referenced to ANALOG COMMON.
DS21460C-page 8
2004 Microchip Technology Inc.
TC7135
5.0 DIGITAL SECTION FUNCTIONAL DESCRIPTION
The major digital subsystems within the TC7135 are illustrated in Figure 5-1, with timing relationships shown in Figure 5-2. The multiplexed BCD output data can be displayed on LCD or LED displays. The digital section is best described through a discussion of the control signals and data outputs. Polarity D5 MSB D4 Digit D3 Drive Multiplexer From Analog Section Polarity FF Zero Cross Detect Latch Latch Latch Latch Latch D2 Signal D1 LSB Data Output 13 B1 14 B2 15 B4 16 B8
Counters
Control Logic 24 DGND 22 Clock In 25 RUN/ HOLD 27 Overrange 28 Underrange 26 STROBE 21 Busy
FIGURE 5-1:
Digital Section Functional Diagram.
2004 Microchip Technology Inc.
DS21460C-page 9
TC7135
5.2
Integrator Output Signal System Integrate Reference Integrate Zero 10,000 20,001 10,001 Counts Counts (Fixed) Counts (Max) Full Measurement Cycle 40,002 Counts
STROBE Output
During the measurement cycle, the STROBE control line is pulsed low five times. The five low pulses occur in the center of the digit drive signals (D1, D2, D3, D5) (see Figure 5-3). D5 (MSD) goes high for 201 counts when the measurement cycles end. In the center of the D5 pulse, 101 clock pulses after the end of the measurement cycle, the first STROBE occurs for one half clock pulse. After the D5 digit strobe, D4 goes high for 200 clock pulses. The STROBE then goes low 100 clock pulses after D4 goes high. This continues through the D1 digit drive pulse. The digit drive signals will continue to permit display scanning. STROBE pulses are not repeated until a new measurement is completed. The digit drive signals will not continue if the previous signal resulted in an overrange condition. The active-low STROBE pulses aid BCD data transfer to UARTs, processors and external latches. For more information, please refer to Application Note 784 (DS00784).
TC835 Outputs Busy
*
Busy Overrange when Applicable Underrange when Applicable Expanded Scale Below Digit Scan D5 D4 D3 D2 100 Counts STROBE D1 * First D5 of System Zero and Reference Integrate One Count Longer Signal Integrate * Reference Integrate
Auto-Zero Digit Scan * D5 for Overrange D4 D3 D2 D1
End of Conversion D5 (MSD) Data D1 (LSD) Data
B1 B8
D4 Data
D3 Data
D2 Data
D5 Data
FIGURE 5-2: Outputs.
Timing Diagrams For
STROBE 200 Counts D5 201 Counts 200 Counts 200 Counts 200 Counts
Note Absence of STROBE 200 Counts
5.1
RUN/HOLD Input
When left open, this pin assumes a logic `1' level. With a RUN/HOLD = 1, the TC7135 performs conversions continuously, with a new measurement cycle beginning every 40,002 clock pulses. When RUN/HOLD changes to a logic `0', the measurement cycle in progress will be completed, with the data held and displayed as long as the logic `0' condition exists. A positive pulse (>300 nsec) at RUN/HOLD initiates a new measurement cycle. The measurement cycle in progress when RUN/HOLD initially assumed the logic `0' state must be completed before the positive pulse can be recognized as a single conversion run command. The new measurement cycle begins with a 10,001 count auto-zero phase. At the end of this phase, the busy signal goes high.
D4
D3
D2
D1
200 Counts
*Delay between Busy going Low and First STROBE pulse is dependent on Analog Input.
FIGURE 5-3: Strobe Signal Low Five Times Per Conversion.
DS21460C-page 10
2004 Microchip Technology Inc.
TC7135
5.3 BUSY Output 5.6 POLARITY Output
At the beginning of the signal integration phase, BUSY goes high and remains high until the first clock pulse after the integrator zero crossing. BUSY returns to the logic `0' state once the measurement cycle ends in an overrange condition. The internal display latches are loaded during the first clock pulse after BUSY and are latched at the clock pulse end. The BUSY signal does not go high at the beginning of the measurement cycle, which starts with the auto-zero cycle. A positive input is registered by a logic `1' polarity signal. The polarity bit is valid at the beginning of reference integrate and remains valid until determined during the next conversion. The polarity bit is valid even for a zero reading. Signals less than the converter's LSB will have the signal polarity determined correctly. This is useful in null applications.
5.4
OVERRANGE Output
5.7
Digit Drive Outputs
If the input signal causes the reference voltage integration time to exceed 20,000 clock pulses, the OVERRANGE output is set to a logic `1'. The OVERRANGE output register is set when BUSY goes low and is reset at the beginning of the next reference integration phase.
Digit drive signals are positive-going signals. The scan sequence is D5 to D1. All positive pulses are 200 clock pulses wide, with the exception D5, which is 201 clock pulses wide. All five digits are scanned continuously, unless an overrange condition occurs. In an overrange condition, all digit drives are held low from the final STROBE pulse until the beginning of the next reference integrate phase. The scanning sequence is then repeated. This provides a blinking visual display indication.
5.5
UNDERRANGE Output
If the output count is 9% of full scale or less (-1800 counts), the UNDERRANGE register bit is set at the end of BUSY. The bit is set low at the next signal integration phase.
5.8
BCD Data Outputs
The binary coded decimal (BCD) bits B8, B4, B2 and B1 are positive-true logic signals. The data bits become active at the same time as the digit drive signals. In an overrange condition, all data bits are at a logic `0' state.
2004 Microchip Technology Inc.
DS21460C-page 11
TC7135
6.0
6.1
6.1.1
TYPICAL APPLICATIONS
Component Value Selection
INTEGRATING RESISTOR
6.1.3
AUTO-ZERO AND REFERENCE CAPACITORS
The integrating resistor RINT is determined by the fullscale input voltage and the output current of the buffer used to charge the integrator capacitor (CINT). Both the buffer amplifier and the integrator have a class A output stage, with 100 A of quiescent current. A 20 A drive current gives negligible linearity errors. Values of 5 A to 40 A give good results. The exact value of an integrating resistor for a 20 A current is easily calculated.
The size of the auto-zero capacitor has some influence on the noise of the system, with a larger capacitor reducing the noise. The reference capacitor should be large enough such that stray capacitance to ground from its nodes is negligible. The dielectric absorption of the reference and autozero capacitors are only important at power-on or when the circuit is recovering from an overload. Smaller or cheaper capacitors can be used if accurate readings are not required for the first few seconds of recovery.
6.1.4
REFERENCE VOLTAGE
EQUATION 6-1:
Full Scale Voltage RINT = ------------------------------------------20A
The analog input required to generate a full-scale output is VIN = 2 VREF. The stability of the reference voltage is a major factor in the overall absolute accuracy of the converter. For this reason, it is recommended that a high-quality reference be used where high-accuracy absolute measurements are being made.
6.1.2
INTEGRATING CAPACITOR (CINT)
The product of integrating resistor and capacitor should be selected to give the maximum voltage swing that ensures the tolerance build-up will not saturate the integrator swing (approximately 0.3V from either supply). For 5V supplies and ANALOG COMMON tied to supply ground, a 3.5V to 4V full scale integrator swing is adequate. A 0.10 F to 0.47 F is recommended. In general, the value of CINT is given by:
6.2
6.2.1
Conversion Timing
LINE FREQUENCY REJECTION
A signal integration period at a multiple of the 60 Hz line frequency will maximize 60 Hz "line noise" rejection. A 100 kHz clock frequency will reject 50 Hz, 60 Hz and 400 Hz noise. This corresponds to five readings per second (see Table 6-1 and Table 6-2).
EQUATION 6-2:
C INT [ 10, 000 x clock period ] x I INT = --------------------------------------------------------------------------integrator output voltage swing ( 10, 000 ) ( clock period ) x 20A = ----------------------------------------------------------------------------integrator output voltage swing A very important characteristic of the integrating capacitor CINT is that it has low dielectric absorption to prevent rollover or ratiometric errors. A good test for dielectric absorption is to use the capacitor with the input tied to the reference. This ratiometric condition should read half scale 0.9999, with any deviation probably due to dielectric absorption. Polypropylene capacitors give undetectable errors at reasonable cost. Polystyrene and polycarbonate capacitors may also be used in less critical applications.
TABLE 6-1:
CONVERSION RATE VS. CLOCK FREQUENCY
Conversion Rate (Conv./Sec.) 2.5 3 5 7.5 10 20 30
Oscillator Frequency (kHz) 100 120 200 300 400 800 1200
DS21460C-page 12
2004 Microchip Technology Inc.
TC7135
TABLE 6-2: LINE FREQUENCY REJECTION VS. CLOCK FREQUENCY
Line Frequency Rejection (Hz) 60 the ratio between this resistor and the integrating resistor (a few tens of ohms in the recommended circuit), the comparator delay can be compensated and the maximum clock frequency extended by approximately a factor of 3. At higher frequencies, ringing and second-order breaks will cause significant nonlinearities in the first few counts of the instrument. The minimum clock frequency is established by leakage on the auto-zero and reference capacitors. With most devices, measurement cycles as long as 10 seconds give no measurable leakage error. The clock used should be free from significant phase or frequency jitter. Several suitable low-cost oscillators are shown in Section 6.0 "Typical Applications". The multiplexed output means that if the display takes significant current from the logic supply, the clock should have good PSRR.
Oscillator Frequency (kHz) 300 200 150 120 100 40 33-1/3 250 166-2/3 125 100 100
50
6.4
50, 60,400
Zero Crossing Flip Flop
The conversion rate is easily calculated:
EQUATION 6-3:
Clock Frequency (Hz) Reading 1/sec = ---------------------------------------------------4000
6.3
High Speed Operation
The maximum conversion rate of most dual-slope A/D converters is limited by the frequency response of the comparator. The comparator in this circuit follows the integrator ramp with a 3 sec delay, at a clock frequency of 160 kHz (6 sec period). Half of the first reference integrate clock period is lost in delay. This means that the meter reading will change from 0 to 1 with a 50 V input, 1 to 2 with 150 V, 2 to 3 at 250 V, etc. This transition at midpoint is considered desirable by most users. However, if the clock frequency is increased appreciably above 200 kHz, the instrument will flash "1" on noise peaks, even when the input is shorted. For many dedicated applications where the input signal is always of one polarity, the delay of the comparator need not be a limitation. Since the nonlinearity and noise do not increase substantially with frequency, clock rates of up to ~1 MHz may be used. For a fixed clock frequency, the extra count (or counts) caused by comparator delay will be a constant and can be subtracted out digitally. The clock frequency may be extended above 160 kHz without this error, however, by using a low value resistor in series with the integrating capacitor. The effect of the resistor is to introduce a small pedestal voltage on to the integrator output at the beginning of the reference integrate phase. By careful selection of
The flip flop interrogates the data once every clock pulse after the transients of the previous clock pulse and half clock pulse have died down. False zero crossings caused by clock pulses are not recognized. Of course, the flip flop delays the true zero crossing by up to one count in every instance. If a correction were not made, the display would always be one count too high. Therefore, the counter is disabled for one clock pulse at the beginning of the reference integrate (de-integrate) phase. This one-count delay compensates for the delay of the zero crossing flip flop and allows the correct number to be latched into the display. Similarly, a onecount delay at the beginning of auto-zero gives an overload display of 0000 instead of 0001. No delay occurs during signal integrate so that true ratiometric readings result.
6.5
Generating a Negative Supply
A negative voltage can be generated from the positive supply by using a TC7135 (see Figure 6-1). +5V V+ 11 8 (-5V) 10 F 24 + 4 + 10 F 2 3 5 TC7660
TC7135 1 V-
FIGURE 6-1: Generator.
Negative Supply Voltage
2004 Microchip Technology Inc.
DS21460C-page 13
TC7135
+5V
20 19 18 17 12 D1 D2 D3 D4 D5 4 INT OUT 0.33 F 1 F 5 23 POL 6 BUFF OUT CREF - 7 100 k 22 F TC7135 200 kHz IN CREF+ 8 100 k 10 + +INPUT Analog 16 1 F B8 9 Input 15 -INPUT - B4 14 B2 3 ANALOG B1 13 COMMON REF V- IN V+ 12 11 5V 100 k MCP1525 1 F AZ IN 4.7 k b 1 F c 7 7 X7 5 RBI DM7447A 16 +5V 9 15 7 7
Blank MSD On Zero 6 D 2 C 1 B 7 A
V+
FIGURE 6-2:
R2
4-1/2 Digit ADC With Multiplexed Common Anode Led Display.
R1 C FO
+5V
16 k
56 k 2 8 7 1 4
1 k
1.
Gates are 74C04 R 1 R2 1 F O = ------------------------------------------------- , R P = -----------------R1 + R 2 2C ( 0.41RP + 0.7R 1 ) a. If R1 = R2 = R1, F 0.55/RC b. If R2 >> R1, F 0.45/R1C c. If R2 << R1, F 0.72/R1C
0.22 F
+
VOUT
LM311 3- 16 k
30 k 390 pF
2. Examples: a. F = 120 kHz, C = 420 pF R1 = R2 10.9 k b. F = 120 kHz, C = 420pF, R2 = 50 k R1 = 8.93 k c. F = 120 kHz, C = 220 pF, R2 = 5 k R1 = 27.3 k
R2 100 k
+5V
R4 2 k
2 R2 100 k C1 0.1 F
6 + LM311 3 4 - 1
C2 10 pF 7 VOUT R3 50 k
FIGURE 6-3:
RC Oscillator Circuit.
FIGURE 6-4:
Comparator Clock Circuits.
DS21460C-page 14
2004 Microchip Technology Inc.
TC7135
+5V +5V SET VREF = 1V 5V 1 MCP1525 1 F 100 k 2 V-
27 OR REF IN 26 3 ANALOG STROBE GND 4 INT OUT 1 F 5 AZ IN 6 BUFF OUT 100 k 7 CREF+ 1 F 8C -
REF
TC7135 UR
28
150 47 k 10 150 11 12 9 8 7
Analog GND 0.33 F
RUN/HOLD DGND POLARITY CLK IN BUSY
25 24 23 22 21 20
13 MC14513 6 14 15 16 17 18 5 4 3 2 1 +5V
100 k + SIG IN 0.1 F
+5V
(LSD) D1 -INPUT 10 +INPUT 19 D2 11 18 D3 V+ 12 17 D4 D5 (MSD) 13 16 B1 (LSB) (MSB) B8 14 B4 15 B2
9
FOSC = 200 kHz
FIGURE 6-5:
4-1/2 Digit ADC With Multiplexed Common Cathode LED Display.
2004 Microchip Technology Inc.
DS21460C-page 15
TC7135
7.0
7.1
PACKAGING INFORMATION
Package Marking Information
28-Pin PLCC
1
Example:
1
M
XXXXXXXXXX XXXXXXXXXX YYWWNNN
M
TC7135CLI 0444256
28-Pin PDIP (Wide)
Example:
XXXXXXXXXXXXXXX XXXXXXXXXXXXXXX XXXXXXXXXXXXXXX YYWWNNN
TC7135CPI 0444256
*h
*h
44-Pin MQFP
Example:
M
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
M
TC7135CKW 0444256
64-Pin MQFP
Example:
M
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
M
TC7135CBU 0444256
Legend:
XX...X YY WW NNN
Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
DS21460C-page 16
2004 Microchip Technology Inc.
TC7135
28-Lead Plastic Leaded Chip Carrier (LI) - Square (PLCC)
E E1 #leads=n1
D1
D
n12 CH2 x 45 CH1 x 45 A3
A2
32
A B1
c E2 Units Dimension Limits n p INCHES* NOM 28 .050 7 .165 .173 .145 .153 .020 .028 .021 .026 .035 .045 .000 .005 .485 .490 .485 .490 .450 .453 .450 .453 .410 .420 .410 .420 .008 .011 .026 .029 .013 .020 0 5 0 5
B p D2
A1
MIN
MAX
MIN
Number of Pins Pitch Pins per Side n1 Overall Height A .180 Molded Package Thickness .160 A2 Standoff A1 .035 A3 Side 1 Chamfer Height .031 Corner Chamfer 1 CH1 .055 Corner Chamfer (others) CH2 .010 Overall Width E .495 Overall Length D .495 Molded Package Width E1 .456 Molded Package Length D1 .456 Footprint Width E2 .430 Footprint Length D2 .430 c Lead Thickness .013 Upper Lead Width B1 .032 Lower Lead Width B .021 Mold Draft Angle Top 10 Mold Draft Angle Bottom 10 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-026
MILLIMETERS NOM 28 1.27 7 4.19 4.39 3.68 3.87 0.51 0.71 0.53 0.66 0.89 1.14 0.00 0.13 12.32 12.45 12.32 12.45 11.43 11.51 11.43 11.51 10.41 10.67 10.41 10.67 0.20 0.27 0.66 0.74 0.33 0.51 0 5 0 5
MAX
4.57 4.06 0.89 0.79 1.40 0.25 12.57 12.57 11.58 11.58 10.92 10.92 0.33 0.81 0.53 10 10
2004 Microchip Technology Inc.
DS21460C-page 17
TC7135
28-Lead Plastic Dual In-line (PI) - 600 mil (PDIP)
E1
D
2 n E A c eB Units Dimension Limits n p INCHES* NOM 28 .100 .175 .150 A1 B1 B p MILLIMETERS NOM 28 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 12.83 13.84 35.43 36.32 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.51 5 10 5 10 A2 L 1
MIN
MAX
MIN
MAX
Number of Pins Pitch Top to Seating Plane A .160 .190 Molded Package Thickness .140 .160 A2 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .595 .600 .625 Molded Package Width E1 .505 .545 .560 Overall Length D 1.395 1.430 1.465 Tip to Seating Plane L .120 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .030 .050 .070 Lower Lead Width B .014 .018 .022 eB Overall Row Spacing .620 .650 .680 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-079
4.83 4.06 15.88 14.22 37.21 3.43 0.38 1.78 0.56 17.27 15 15
DS21460C-page 18
2004 Microchip Technology Inc.
TC7135
44-Lead Plastic Metric Quad Flatpack (KW) 10x10x2 mm Body, Lead Form (MQFP)
E E1 #leads=n1 p
D1 D
B n
2 1
CH x 45
A1
c
A
L
(F)
A2
Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p n1 A A2 A1 L (F) E D E1 D1 c B CH
MIN
.079 .077 .002 .029 0 .510 .510 .390 .390 .005 .012 .025 5 5
INCHES NOM 44 .031 11 .086 .080 .006 .035 .063 3.5 .520 .520 .394 .394 .007 .015 .035 10 10
MAX
MIN
.093 .083 .010 .041 7 .530 .530 .398 .398 .009 .018 .045 15 15
MILLIMETERS* NOM 44 0.80 11 2.00 2.18 1.95 2.03 0.05 0.15 0.73 0.88 1.60 0 3.5 12.95 13.20 12.95 13.20 9.90 10.00 9.90 10.00 0.13 0.18 0.30 0.38 0.64 0.89 5 10 5 10
MAX
2.35 2.10 0.25 1.03 7 13.45 13.45 10.10 10.10 0.23 0.45 1.14 15 15
Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-022 Drawing No. C04-071
2004 Microchip Technology Inc.
DS21460C-page 19
TC7135
64 Lead Metric Plastic Quad Flat (BU) (MQFP)
E E1
e
D1 B
D
2 1
n
A c
a
A2
b
L
f
A1
(F)
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Molded Package Length Foot Length Footprint (Reference) Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom
Units Dimension Limits n e A A2 A1 E E1 D D1 L (F) f c B a b
MIN
.098 .098 .000
.029 0 .004 .011 5 5
INCHES NOM 64 .031 BSC -.106 -.677 BSC .551 BSC .677 BSC .551 BSC .035 .063 REF ------
MAX
MIN
.124 .114 .010
2.50 2.50 0.00
.041 6 .009 .018 16 16
0.73 0 0.11 0.29 5 5
MILLIMETERS* NOM 64 0.80 BSC -2.70 -17.20 BSC 14.00 BSC 17.20 BSC 14.00 BSC 0.88 1.60 REF ------
MAX
3.15 2.90 0.25
1.03 7 0.23 0.45 16 16
*Controlling Parameter Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: MS-022 BE. Formerly TelCom PQFP package.
Drawing No. C04-022
DS21460C-page 20
2004 Microchip Technology Inc.
TC7135
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package Examples:
a) b) Device TC7135: 4-1/2 Digit A/D, BCD Output c) 4-1/2 Digit A/D, BCD Output, PLCC package. TC7135CPI: 4-1/2 Digit A/D, BCD Output, PDIP package. TC7135CLI713: 4-1/2 Digit A/D, BCD Output, PLCC package, Tape and Reel. TC7135CBU: 4-1/2 Digit A/D, BCD Output, MQFP package. TC7135CLI:
Temperature Range
C
= 0C to +70C
d)
Package
LI = Plastic Leaded Chip Carrier (PLCC), 28-lead LI713 = Plastic Leaded Chip Carrier (PLCC), 28-lead, Tape and Reel PI = Plastic DIP, (600 mil Body), 28-lead KW = Plastic Metric Quad Flatpack, (MQFP), 44-lead BU = Plastic Metric Quad Flatpack, (MQFP), 64-lead
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2004 Microchip Technology Inc.
DS21460C-page 21
TC7135
NOTES:
DS21460C-page 22
2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc.
DS21460C-page 23
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: www.microchip.com
China - Beijing
Unit 706B Wan Tai Bei Hai Bldg. No. 6 Chaoyangmen Bei Str. Beijing, 100027, China Tel: 86-10-85282100 Fax: 86-10-85282104
Korea
168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934
Singapore
200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850
China - Chengdu
Rm. 2401-2402, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599
Atlanta
3780 Mansell Road, Suite 130 Alpharetta, GA 30022 Tel: 770-640-0034 Fax: 770-640-0307
Taiwan
Kaohsiung Branch 30F - 1 No. 8 Min Chuan 2nd Road Kaohsiung 806, Taiwan Tel: 886-7-536-4818 Fax: 886-7-536-4803
Boston
2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821
China - Fuzhou
Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521
Taiwan
Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Chicago
333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
China - Hong Kong SAR
Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431
Dallas
4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924
EUROPE
Austria
Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393
China - Shanghai
Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Detroit
Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
Denmark
Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45-4420-9895 Fax: 45-4420-9910
China - Shenzhen
Rm. 1812, 18/F, Building A, United Plaza No. 5022 Binhe Road, Futian District Shenzhen 518033, China Tel: 86-755-82901380 Fax: 86-755-8295-1393
Kokomo
2767 S. Albright Road Kokomo, IN 46902 Tel: 765-864-8360 Fax: 765-864-8387
France
Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
China - Shunde
Room 401, Hongjian Building, No. 2 Fengxiangnan Road, Ronggui Town, Shunde District, Foshan City, Guangdong 528303, China Tel: 86-757-28395507 Fax: 86-757-28395571
Los Angeles
18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338
China - Qingdao
Rm. B505A, Fullhope Plaza, No. 12 Hong Kong Central Rd. Qingdao 266071, China Tel: 86-532-5027355 Fax: 86-532-5027205
Germany
Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-89-627-144-0 Fax: 49-89-627-144-44
San Jose
1300 Terra Bella Avenue Mountain View, CA 94043 Tel: 650-215-1444 Fax: 650-961-0286
India
Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-22290061 Fax: 91-80-22290062
Italy
Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781
Toronto
6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509
Japan
Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Netherlands
Waegenburghtplein 4 NL-5152 JR, Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340
ASIA/PACIFIC
Australia
Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
United Kingdom
505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820
05/28/04
DS21460C-page 24
2004 Microchip Technology Inc.

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