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STw5095
Low Power Asynchronous Stereo Audio Codec with Integrated Power Amplifiers
PRELIMINARY DATA
Features

20 bit audio resolution, 8kHz to 96kHz independent rate ADC and DAC Asynchronous sampling ADC and DAC: they do not require oversampled clock and information on the audio data sampling frequency (fs). Jitter tolerant fs Wide master clock range: from 4MHz to 32MHz I2C/SPI compatible control I/F Stereo headphones drivers, handsfree loudspeaker driver, line out drivers Mixable analog line inputs Voice filters: 8/16kHz with voice channel filters Automatic gain control for microphone and linein inputs Two programmable master/slave serial audio data interfaces (I2S, SPI, PCM compatible and other formats) Frequency programmable clock outputs Multibit modulators with data weighted averaging ADC and DAC DSP functions for bass-treble-volume control, mute, mono/stereo selection, voice channel filters, de-emphasis filter and dynamic compression. 93 dB dynamic range ADC, 0.001% THD with full scale output @ 2.7V 95 dB dynamic range DAC, 0.02% THD performance @ 2.7V over 16 load
STw5095

TFBGA64 5x5 (64 pins)
Selectable stereo differential or single-ended line inputs with 38 dB range programmable gain
Analog output drivers
Stereo headphones outputs driving capability: 40 mW (0.1% THD) over 16 with 40 dB range programmable gain Common mode voltage headphones driver (phantom ground) Balanced loudspeaker output driving capability: up to 500mW (VCCLS>3.5V; 1% THD) over 8 with 30dB range programmable gain Transient supression filter during power up and power down Balanced/unbalanced stereo line outputs driving capability 1k

Applications
Analog inputs
Selectable stereo differential or single-ended microphone amplifier inputs with 51dB range programmable gain One microphone biasing output Microphone plug-in and push-button detection input
Digital cellular telephones with mp3 player, stereo recorder, fm radio stereo listening and recording functions, live music recording Portable digital players and recorders

November 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Rev 1.0 1/69
www.st.com
2
STw5095
Description
STw5095 is a low power asynchronous stereo audio CODEC device with headphones amplifiers for high quality audio listening and recording. The STw5095 control registers are accessed through a selectable I2C-bus compatible or SPI compatible interface. The STw5095 asynchronous stereo audio CODEC is designed to easily fit in most audio systems because it supports an extended master clock range (any value between 4 MHz and 32 MHz) and at the same time it supports any audio data rate (independent in AD and DA paths) from 8 kHz to 48 kHz and from 88 kHz to 96 kHz, moreover it can tolerate jitter on audio data without degrading performance. The audio data serial interfaces (for AD and DA) can be Master or Slave, are I2S compatible and they support other formats that can easily interface to standard serial ports. The two audio interfaces can be used as a single bidirectional interface. Two frequency programmable clock sources are available to generate the master clock for the audio sub-system of other devices. The internal D to A and A to D converters work with up to 24 bit resolution.
The supply voltage can be the same for the whole device, in the range 2.4 V to 2.7 V, or it can be differentiated for digital (VCC: 1.8 V to 2.7 V), analog (VCCA: 2.4 V to 3.3 V) and loudspeaker driver (VCCLS: VCCA to 5.5 V) to obtain best performance and maximum power to the loudspeaker (up to 500 mW). STw5095 has multiple analog mixable inputs and outputs. It can directly drive Stereo Headphones without external capacitors and it has a Loudspeaker driver that can also be used for monophonic group listening. Stereo differential and single ended microphones, auxiliary line in stereo and mono signals can be mixed and connected to the ADC or directly to the drivers, mixed also with DAC audio signals. STw5095 stereo audio Codec main applications include multimedia handheld devices such as cellular phones with added low-power highquality MP3 and or FM radio listening/recording features, or any battery powered equipment such as PDAs, Camcorders, etc. that require Stereo Audio Codec with Headphones drivers.
Ordering codes
Part Number STw5095 STW5095T Details TFBGA 64 Tray TFBGA 64 Tape and Reel
Pin configuration (top view)
GND SCLK AD_OCK DA_OCK AD_CK AMCK AD_SYNC DA_DATA
A
HDET VCCA VCC SDA/SDIN DA_CK AD_DATA DA_SYNC IRQ
B
AUX1L MICLN VCCA CMOD AS/CSB VCC GND MBIAS
C
CAPMIC MICLP AUX3L GNDA VCCIO VCCA MICRN AUX1R
D
AUX2LN AUX2LP LINEINL CAPLS AUX3R GNDA CAPLINEIN MICRP
E
OLN GNDCM VCMHPS LSPS LSNS LINEINR AUX2RP AUX2RN
F
OLP GNDP VCMHP LSP LSN VCCP GNDP ORN
G
VCCP HPL VCCLS GNDP GNDP VCCLS HPR ORP
H
1
2
3
4
5
6
7
8
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STw5095
Contents
1 2 3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock generators and master mode function . . . . . . . . . . . . . . . . . . . . . . . . 13 Audio digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Analog output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Analog mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AD path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DA path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Analog-only operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Automatic Gain Control (AGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Interrupt request: IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Headset plug-in and push-button detection . . . . . . . . . . . . . . . . . . . . . . . . . 19 Microphone biasing circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Supply and power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DSP control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Analog functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Digital audio interfaces master mode and clock generators . . . . . . . . . . . . . 32 Digital audio interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Digital filters, software reset and master clock control . . . . . . . . . . . . . . . . . 36
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STw5095 4.9 4.10 Interrupt control and control interface SPI out mode . . . . . . . . . . . . . . . . . . 37 AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5
Control Interface and Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1 5.2 5.3 Control interface I2C mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Control interface SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Master clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6 7 8
Audio Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Operative Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.1 8.2 8.3 8.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Operative supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Typical power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.1 9.2 9.3 9.4 9.5 9.6 9.7 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 AMCK with sinusoidal input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Analog interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Headset plug-in and push-button detector . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Microphone bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Power supply rejection ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 LS gain limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10
Analog Input/output Operative Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1 10.2 10.3 10.4 10.5 10.6 Analog levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Microphone input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Line input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Line output levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Power output levels HP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Power output levels LS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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STw5095
11 12 13 14 15 16 17 18 19
Stereo Audio ADC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Stereo Audio DAC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 AD to DA Mixing (Sidetone) Specifications . . . . . . . . . . . . . . . . . . . . . . . . 61 Stereo Analog-only Path Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ADC (TX) & DAC (RX) Specifications With Voice Filters Selected . . . . . 62 Typical Performance Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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1
LINEINR AD Sample Rate Converter ADC
LINEINL
Stereo Sing.E.
MIC AUX1 AUX2 AUX3 MUTE R ADLIN MIC L-R PreAmps L
ADMIC
HPLG DA_SYNC
MIXMIC
MIXLIN
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VCCA GNDA VCCP VCCLS GNDP GNDCM VCC GND VCCIO IRQ Gen IRQ AGC (from DSP) LINLG LINRG -20:+18 dB Step 2 L Stereo Path R Headset Detection HDET LIN L-R Amps
Note:
Figure 1.
MICLP
MICLN
LINSEL
MICRP
Stereo Diff.
MICRN
AUX1L
1 Functional Block Diagram
AUX1R
Stereo Sing.E.
LINEIN AUX1 AUX2 AUX3 MUTE
STw5095
AGC (from DSP) Power-On Reset Registers Control Logic Control I/F
AUX2PL
SDA/SDIN SCLK AS/CSB CMOD
AUX2NL
AUX2PR MICLG MICRG 0/39 dB Step 1.5 MICLA MICRA -12/0 dB Step 1.5
Stereo Diff.
MICSEL
AUX2NR
AUX3L
STw5095 block diagram
AUX3R
Stereo Sing.E.
Stereo ADC
AD_DATA
CAPMIC
CAPLINEIN ADRTOL
Comm. Mode
DSP
ADMONO Digital AD-PLL Filter Audio/Voice
Audio AD-I/F
AD_CK AD_SYNC
AD_SYNC
MBIAS ADC Digital Gain
Mic. Bias
2.1V Reference
AGC (Mic&Lin)
CK Gen/ Master Mode
AD_OCK
Functional Block Diagram
LOG: -18:0 dB Step 3 Oscillator
OLP
OLN Bandgap
Left LineOut
MICLO
MCK DA to AD Mixing Gain
(Audio Only)
PLL
AMCK
ORP
ORN CurrentBias
Right LineOut
AD to DA Mixing Gain (sidetone)
Bass Treble
(Audio only)
DA_OCK Filter Audio/Voice DAC Digital Gain Dyn.Comp. CK Gen/ Master Mode
HPL R L
Left Driver
-40:0 dB Step 2 Transient Suppr. Filter Digital DA-PLL
VCMHP Analog Filter DAC MIXDAC
CM Driver
Voltage Reference Modulator
DAMONO Audio DA-I/F
DA_SYNC DA_CK DA_DATA DA Sample Rate Converter
VCMHPS
-40:0 dB Step 2
HPR
Right Driver
Transient Suppr. Filter
HPRG
LSPS LSSEL L (L+R)/2 R
LSP
LSG -24:6 dB Step 2
Stereo DAC
CAPLS
Mono Driver
LSN
Transient Suppr. Filter
This diagram shows the functionality of the device and of some control registers bits but it does not necessarily reflect the exact hardware implementation.
STw5095
LSNS
STw5095
2 Pin Description
2
Table 1.
Pin N D2 C2 E8 D7 C8 D1 C1 D8 E2 E1 F7 F8 D3 E5 E3 F6 E7 G4 G5
Pin Description
Pin description
Name MICLP MICLN MICRP MICRN MBIAS CAPMIC AUX1L AUX1R AUX2LP AUX2LN AUX2RP AUX2RN AUX3L AUX3R LINEINL LINEINR CAPLINEIN LSP, LSN Type Description
AI
Left and Right channel differential pins for microphone input.
AO AI AI
Microphone Biasing Pin. Fixed voltage reference. A capacitor must be connected between CAPMIC and Ground. Left and Right channel single ended pins for microphone or line input.
AI
Left and Right channel differential pins for microphone or line input.
AI AI AI
Left and Right channel single ended pins for microphone or line input. Left and Right channel single ended pins for line input. A capacitor must be connected between CAPLINEIN and Ground. Analog differential loudspeaker amplifier output for Left channel or Right channel or the sum of both. This output can drive 50nF (with series resistor) or directly an earpiece transductor of 8 ; It can deliver up to 500mW. LSPS, LSNS (sense) pins must be connected on the application board to LSP, LSN pins respectively (see application note). The connection must be as close as possible to the pins. A capacitor can be connected between this node and Ground. See application notes Audio single ended headphones amplifier outputs for Left and Right channels. The outputs can drive 50nF (with series resistor) or directly an earpiece transductor of 16 . Common mode voltage headphones output. The negative pins of headphones left and right speakers can be connected to this pin to avoid decoupling capacitors. VCMHPS (sense) pin must be connected on the application board to VCMHP pin (see application note). The connection must be as close as possible to the pins. Audio differential line out amplifier for Left and Right channels. This outputs can drive up to 1k resistive load. Can be used as single ended outputs.
AO
F4 F5 E4 H2 H7
LSPS, LSNS CAPLS HPL HPR
AO
AI
AO
G3
VCMHP
AO
F3 G1 F1 H8 G8
VCMHPS OLP OLN ORP ORN
AO
AO
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2 Pin Description
STw5095
Table 1.
Pin N C4 A2 B4
Pin description
Name CMOD SCLK SDA/SDIN Type DI DI DIOD Description Control interface type selector: I2C-bus mode or SPI mode. Control interface serial clock input. Control interface serial data input-output in I2C mode (SDA), Control interface serial data input in SPI mode (SDIN). Control interface address select in I2C mode (AS). Interface enable signal in SPI mode (CSB). Frame Sync for stereo A/D converter. Frame Sync for stereo D/A converter. Serial Data Clock for stereo A/D converter. Serial Data Clock for stereo D/A converter. Serial Data Out for stereo A/D converter. Serial Data In for stereo D/A converter. Headset detection input (Microphone Plug-in and Push-Button detection). Programmable Interrupt output. Active low signal. Oversampled Clock Out from AD clock generator. Oversampled Clock Out from DA clock generator. Master Clock Input. Accepted range 4 MHz to 32 MHz. AMCK is a Digital square wave AMCK is an Analog sinewave (see AMCKSIN Section 4.8 on page 36) Power Supply pins for the analog section. Standard Operating range: from 2.7 V to 3.3 V Low Voltage (LV) Range: from 2.4 V to 2.7 V Ground pins for the analog section. Ground pin for analog reference. GNDCM can be connected to GNDA. Power Supply pins for the left and right output drivers (headphones and line-out). Operating range: from VCCA to 3.3V Power Supply pins for the mono differential output driver. Operating range: from VCCA to 5.5V Ground pins for the left, right and mono-differential output drivers. GNDP and GNDA must be connected together. Power Supply pins for the digital section. Operating range: from 1.71 V to 2.7 V
C5 A7 B7 A5 B5 B6 A8 B1 B8 A3 A4 A6 B2 C3 D6 D4 E6 F2 G6 H1 H3 H6 G2 G7 H4 H5 B3 C6
AS/CSB AD_SYNC DA_SYNC AD_CK DA_CK AD_DATA DA_DATA HDET IRQ AD_OCK DA_OCK AMCK
DI DIO DIO DIO DIO DO DI AI DO DO DO DI AI P
VCCA
GNDA GNDCM
P P
VCCP
P
VCCLS
P
GNDP
P
VCC
P
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STw5095
Table 1.
Pin N A1 C7 D5
2 Pin Description
Pin description
Name GND Type P Description Ground pins for the digital section. Power Supply pin for the Digital I/O buffers. Operating ranges: from 1.2 V to 1.8 V and from 1.71 V to VCC
VCCIO
P
Note:
VCC, VCCA, VCCP, VCCLS can be connected together for low cost applications: Operating range: 2.4 V-2.7 V.
Type definitions
AI AO AIO DI DO DIO DIOD P Analog input Analog Output Analog Input Output Digital Input Digital output Digital Input Output Digital Input Output Open Drain Power Supply or Ground
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3 Functional Description
STw5095
3
3.1
Functional Description
Power supply
STw5095 can have different supply voltages for different blocks, to optimize performance, power consumption and connectivity. See Operative supply voltage on page 50 for voltage definition. The correct sequence to apply supply voltage is to set first (and unset last) the digital I/O supply (VCCIO). The other supply voltages can be set in any order and can be disconnected individually, if needed. Disconnection does not cause any harm to the device and no extra current is pulled from any supply during this operation. Moreover if a voltage conflict is detected, like VCCA < VCC (not allowed), simply all blocks connected to VCCA are set to power down and no extra current is pulled from supply. When VCCIO is set and VCC (digital supply) is not set, all the digital output pins are in high impedance state, while the digital inputs are disconnected to avoid power consumption for any input voltage value between GND and VCCIO. Before VCC is disconnected the device has to be reset (SWRES bit in CR30). When the analog supply (VCCA) is set and VCC is not set, all the analog inputs are in high impedance state. The control registers are powered by VCC pin (digital supply) so if this pin is disconnected all the information stored in control registers is lost. When the digital supply voltage is set, a power-on-reset (POR) circuit sets all the registers content to the default value and then generates an IRQ signal writing 1 in bits PORMSK and POREV in CR31 and CR32 respectively. All supplies must be on during operation.
3.2
Device programming
STw5095 can be programmed by writing Control Registers with SPI or I2C compatible control interface (both slave). The interface is always active, there is no need to have the master clock running to program the device registers. The choice between the two interfaces is done via an input pin (CMOD): 1. CMOD connected to GND: I2C compatible mode selected The device address is selected with AS pin:
AS connected to GND: chip address 00110101(35hex) for reading, 00110100 (34hex) for writing AS connected to VCCIO: chip address 00110111(37hex) for reading, 00110110 (36hex) for writing
When this mode is selected control registers are accessed through pins: SCLK (clock) SDA (serial data out/in, open drain) 2. CMOD connected to VCCIO: SPI compatible mode selected When this mode is selected control registers are accessed through: CSB (chip select, active low) SCLK (clock) SDIN (serial data in) AD_OCK or DA_OCK or IRQ (serial data out, if selected)
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STw5095
3 Functional Description
Device Programming: I2C. The I2C Control Interface timing is shown in Section 5.1 on page 41. The interface has an internal counter that keeps the current address of the control register to be read or written. At each write access of the interface the address counter is loaded with the data of the register address field. The value in the address counter is increased after each data byte read or write. It is possible to access the interface in 2 modes: single-byte mode in which the address and data of a single register are specified, and multi-byte mode in which the address of the first register to be written or read is specified and all the following bytes exchanged are the data of successive registers starting from the one specified (in multi-byte mode the internal address counter restart from register 0 after the last register 36). Using the multi-byte mode it is possible to write or read all the registers with a single access to the device on the I2C bus. Device Programming: SPI. The SPI Control Interface timing is shown in Section 5.2 on page 42. Bits SPIOSEL (SPI Output Select) in CR33 control the out pin selection for serial data out (none, AD_OCK, DA_OCK or IRQ), while bit SPIOHIZ=1 in CR33 selects the high impedance state of serial data out pin when idle. The first bit sent on SDIN, after CSB falling edge, sets the interface for writing (SDIN=1) or reading (SDIN=0), then a 7-bit Control Register address follows. If the interface is set for writing then the last 8 bits on SDIN are written in the control register. If the interface is set for reading then after the 7 bit address STw5095 sends out 8 bits data on the pin selected with bits SPIOSEL in CR33, while bits present at SDIN pin are ignored. If SPIOSEL=00 (no out pin selected) the reading access on SPI interface can still be useful to clear the IRQ event bits in CR32.
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3 Functional Description
STw5095
3.3
Power up
STw5095 internal blocks can individually be switched on and off according to the user needs. A general Power Up bit is present at bit 7 of CR0. See the following drawing to select the needed block for the desired function. A fast-settling function is activated to quickly charge external capacitors when the device is switched on (CAPLS, CAPLINEIN and CAPMIC). Figure 2. Power up block diagram
ENANA ENMICL ENHSD MBIAS
POWERUP
ENMICR
ENADCL
STw5095
ENLINL
ENADCR
ENADCKGEN
ENLINR ADMAST ENADOCK
ENLOL
AUDIO I/F
DAMAST ENHPL ENMIXL
ENDAOCK
ENLS ENMIXL
ENDACL
ENDACKGEN
ENHPR
ENDACR
ENPLL
ENLOR ENOSC=0 ENAMCK
ENOSC=1 ENHPVCM
ENOSC
3.4
Master clock
The master clock pin (AMCK) accepts any frequency from 4 MHz to 32 MHz. The 4-32 MHz range is divided in sub-ranges that have to be programmed in bits CKRANGE in CR30. The jitter and spectral properties of this clock have a direct impact on the DAC and ADC performance because it is used to directly or by integer division drive the continuous-time to sampled-time interfaces. Note that AMCK clock des not need to have any relation to any other digital or analog input or output.
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STw5095
3 Functional Description
AMCK can be either a squarewave or a sinewave, bit AMCKSIN in CR30 selects the proper input mode. When a sinewave is used as input, AMCK pin must be decoupled with a capacitor. Specification for sinusoidal input can be found in Section 9.2: AMCK with sinusoidal input on page 53. The AMCK clock is not needed when only analog functions are used. For this purpose an internal oscillator with no external components can be used to operate the device (see Analog-only operation on page 17).
3.5
Data rates
STw5095 supports any data rate in 2 ranges: 8 kHz to 48 kHz and 88 kHz to 96 kHz. The range is selected with bits DA96K and AD96K in CR29 for AD and DA paths respectively.
Note:
When AD96K=1 it is required to have DA96K=1.
The rates are fully independent in A/D and D/A paths. Moreover the rates do not have to be specified to the device and they can change on the fly, within one range, while data is flowing. The 2 audio data interfaces (for A/D and D/A) can independently operate in master or slave mode.
3.6
Clock generators and master mode function
STw5095 provides 2 internal clock generators that can drive, if needed, the audio interfaces (master mode), and/or two independent master clocks. The AMCK clock input frequency is internally raised via a PLL to obtain a clock (MCK) in the range 32 MHz to 48 MHz. The ratio MCK/AMCK is defined in CR30 (see MCKCOEFF in Section 4.6 on page 32). MCK is used to obtain, by fractional division, the oversampled clock (OCK), word clock (SYNC) and bit clock (CK), that will therefore have edges aligned with MCK (the OCK period can have jitter of 1 MCK period). The frequency of OCK, SYNC and CK is set with DAOCKF in CR21/20 for DA interface, and ADOCKF in CR24/23 for AD interface. The ratio between OCK and SYNC clocks is selected with bit DAOCK512 in CR22 for DA interface and bit ADOCK512 in CR25 for AD interface. The ratio between CK and SYNC clocks depends on the selected interface format (see Audio digital interfaces paragraph below). Note that SPI format can only be slave. The ADOCK and DAOCK output clocks are activated by bits ENADOCK and ENDAOCK respectively, while master mode generation is activated with two bits: first ADMAST (DAMAST) sets ADSYNC and ADCK (DASYNC and DACK) pins as outputs, then ADMASTGEN (DAMASTGEN) generates the SYNC and CK clocks. The logical value at SYNC and CK pins before data generation depends on the interface selected format. See description of CR20 to CR25 for further details.
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3 Functional Description
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3.7
Audio digital interfaces
Two separate audio data interfaces are provided for AD and DA paths to have maximum flexibility in communicating with other devices. The 2 interfaces can have different rates and can work in different formats and modes (i.e AD interface can be 8 kHz PCM slave while DA is 44.1 kHz I2S master). The pins used by the interfaces are: AD_SYNC, AD_CK and AD_DATA for AD path word clock, bit clock and data, respectively, and DA_SYNC, DA_CK and DA_DATA for DA path word clock, bit clock and data, respectively. Data is exchanged with MSB first and left channel data first in all formats. Data word-length is selected with bits DAWL in CR26 and ADWL in CR27. AD_DATA pin, outside the selected time slot, is in the impedance condition selected by bit ADHIZ in CR28 in all data formats except Right-Aligned-Format. In the following paragraphs SYNC, CK and DATA will be used when the distinction between AD and DA is not relevant. When Master Mode is selected (bits DAMAST and ADMAST in CR22 and CR25 respectively) the SYNC and CK clocks are generated internally. In addition, an oversampled clock can be generated for each interface (AD_OCK and DA_OCK). The OCK clock is available in Slave Mode also, if needed. The AD and DA interfaces can also be used as a single bidirectional interface when they are configured with the same format (Delayed, DSP, etc.) and AD_SYNC is connected to DA_SYNC and DA_CK to AD_CK. Master Mode is still available selecting ADMAST or DAMAST (not both). The interfaces features are controlled with control registers CR26, CR27 and CR28. Supported operating formats:
Delayed-Format (I2S compatible) (DAFORM or ADFORM =000): the Audio Interface is I2S compatible (Figure 8 on page 45). The number of CK periods within one SYNC period is not relevant, as long as enough CK periods are used to transfer the data and the maximum frequency limit specified for bit clock is not exceeded. CK can be either a continuous clock or a sequence of bursts. In master mode there are 32 CK periods per SYNC period (that means 16 CK periods per channel) when the word length is 16 bit, while there are 64 CK periods per SYNC period (or 32 CK periods per channel) when word length is 18bit or higher. Bits ADSYNCP, DASYNCP and ADCKP, DACKP affect the interface format inverting the polarity of SYNC and CK pins respectively. Left-Aligned-Format (DAFORM or ADFORM =001): this format is equivalent to Delayed-Format without the 1 bit clock delay at the beginning of each frame (Figure 8 on page 45). Right-Aligned-Format (DAFORM or ADFORM =010): this format is equivalent to Delayed-Format, except that the Audio Data is right aligned and that the number of CK periods is fixed to 64 for each SYNC period (Figure 8 on page 45). DSP-Format (DAFORM or ADFORM =011) in this format the Audio Interface starting from a frame sync pulse on SYNC receives (DA) or sends (AD) the Left and Right data one after the other (Figure 9 on page 46). The number of CK periods within one SYNC period is not relevant, as long as enough CK periods are used to transfer the data and the maximum frequency limit specified for bit clock is not exceeded. CK can be either a continuous clock or a sequence of bursts. In Master Mode there are 32 CK periods per SYNC period when the word length is 16 bit, while there are 64 CK periods per SYNC period when word length is 18bit or higher. Bit CKP (ADCKP and DACKP) affects the interface format inverting the polarity of CK pin. Bit SYNCP (ADSYNCP and DASYNCP) switches between
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delayed (SYNCP=0) and non delayed (SYNCP=1) formats. DSP-Format is suited to interface with a Multi-Channel Serial Port.
3 Functional Description
SPI-Format (DAFORM or ADFORM =100) in this format Left and Right data is received with separate data burst. Every burst is identified with a low level on SYNC signal (Figure 9 on page 46). There is no timing difference between the Left and Right data burst: the two channels are identified by the startup order: the first burst after AD path or DA path power-up identifies the Left channel data, the second one is the Right channel data, then Left and Right data repeat one after the other. CK must have 16 periods per channel in case of 16 bit data word and 32 periods per channel in case of 18 bit to 32 bit data word. The SPI interface can be configured as a single-channel (mono) interface with bit SPIM (ADSPIM and DASPIM). The mono interface always exchanges the left channel sample. SPI-Format can only be Slave: if Master Mode is selected the CK and SYNC pins are set to 0. Bit CKP (ADCKP and DACKP) affects the interface format inverting the polarity of CK pin. PCM-Format (DAFORM or ADFORM =111): this format is monophonic, as it can only receive (DA) and transmit (AD) single channel data (Figure 9 on page 46). It is mainly used when voice filters are selected. If audio filters are used then the same sample is sent from DA-PCM interface to both channel of DA path, and the left channel sample from AD path is sent to AD-PCM interface. If in the AD path the right channel has to be sent to the PCM interface then the following must be set: ADRTOL=1 (CR27) and ENADCL=0 (CR1). In Master Mode the number of CK periods per SYNC period is between 16 and 512 (see DAPCMF in CR22 and ADPCMF in CR25, Section 4.6 on page 32 for details). Bit CKP (ADCKP and DACKP) affects the interface format inverting the polarity of CK pin. Bit SYNCP (ADSYNCP and DASYNCP) switches between delayed (SYNCP=0) and non delayed (SYNCP=1) formats.
3.8
Analog inputs
STw5095 has a stereo Microphone preamplifier and a stereo Line In amplifier, with inputs selectable among 5: MIC (for Microphone preamplifier only), LINEIN (for Line In amplifier only) and 3 different AUX inputs (for Microphone and Line In amplifiers). The AUX inputs can be used simultaneously for Line In amplifiers and Microphone preamplifiers.
Microphone preamplifier: it has a very low noise input, specifically designed for low amplitude signals. For this reason it has a high input gain (up to 39 dB) keeping a constant 50 k input impedance for the whole gain range. However it can also be used as a line in preamplifier because it can accept a high dynamic input signal (up to 4 Vpp). There are two separate gain and attenuation stages in order to improve the S/N ratio when the preamplifier output range is below full scale (volume control).The gain and attenuation controls are separate for left and right channel (CR3 and CR4 respectively). The Preamplifier input is selected with bits MICSEL in CR18, and it is disconnected when MICMUTE=1. If a single ended input is selected then the preamplifier uses the selected pin as the positive input and connects the negative input (for both left and right channels) to CAPMIC pin, which has to be connected through a capacitor to a low noise ground (typically the same reference ground of the input). The stereo Microphone preamplifier is powered up with bits ENMICL and ENMICR in CR1. Line In amplifier: it is designed for high level input signal. The input gain is in the range -20 dB up to 18 dB. The Line In amplifier input is selected with bits LINSEL in CR18, and it is disconnected when LINMUTE=1. If a single ended input is selected then the amplifier uses the selected pin as the positive input and connects the negative input (for both left and right channels) to CAPLINEIN pin, which has to be connected through a capacitor to a
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3 Functional Description
STw5095
low noise ground (typically the same reference ground of the input). The stereo Line In amplifier is powered up with bits ENLINL and ENLINR in CR1.
3.9
Analog output drivers
STw5095 provides 3 different analog signal outputs and 1 common mode reference output:
Line Out Drivers: it is a stereo differential output, it can be used as single-ended output just by using the positive or negative pin. It can drive 1 k resistive load. The load can be connected between the positive and negative pins or between one pin and ground through a decoupling capacitor. The output gain is regulated with LOG bits in CR7, in the range 0 to -18 dB, simultaneously for left and right channels. When used as a single ended output the effective gain is 6 dB lower. It is muted with bit MUTELO in CR19. The input signal of this stereo output can come from the analog mixer or directly from MIC preamplifiers. The output Common Mode Voltage level is controlled with bits VCML in CR19. The supply voltage of line out drivers is VCCP . The Line Out Drivers are powered up with bits ENLOL and ENLOR in CR1. The output pins are in high impedance state with a 180k pull-down resistor when the Line Out Drivers are powered down. Headphones Drivers: it is a stereo single ended output. It can drive 16 Ohm resistive load and deliver up to 40 mW. The output gain is regulated with HPLG and HPRG bits in CR8 and CR9 respectively, with a range of -40 to 6 dB. It is muted with bit MUTEHP in CR19. The input signal of this stereo output comes from the analog mixer.The output Common Mode Voltage is controlled with bits VCML in CR19. The supply voltage of headphones drivers is VCCP . The Headphones Drivers are powered up with bits ENHPL and ENHPR in CR2.The output pins are in high impedance state when the Headphones Drivers are powered down. Common Mode Voltage Driver: it is a single ended output with output voltage value selectable with bits VCML in CR19, from 1.2 V to 1.65 V in steps of 150 mV. The output voltage should be set to the value closest to VCCP/2 to optimize output drivers performance. The Common Mode Voltage Driver is designed to be connected to the common pin of stereo headphones, so that decoupling capacitors are not needed at HPL and HPR outputs. The supply voltage of the common mode voltage driver is VCCP . The Common Mode Voltage Driver is powered up with bit ENHPVCM in CR2.The output pin is in high impedance state when the Common Mode Voltage Driver is powered down. Loudspeaker Driver: it is a monophonic differential output. It can drive 8 resistive load and deliver up to 500 mW to the load. The output gain is regulated with LSG bits in CR7, in the range -24 to +6 dB. The input signal of the loudspeaker driver comes from the analog mixers: bits LSSEL in CR29 select left channel, right channel, (L+R)/2 (mono) or mute. The output Common Mode Voltage is obtained with an internal voltage divider from VCCLS and it is connected to CAPLS pin. The supply voltage of the loudspeaker driver is VCCLS. The Loudspeaker Driver is powered up with bit ENLS in CR2.The output pin is in high impedance state when the Loudspeaker Driver is powered down.
Note:
Note on direct connection of VCCLS To the battery: The voltage of batteries of handheld devices during charging is usually below 5.5 V, making VCCLS supply pin suitable for a direct connection to the battery. In this case if STw5095 is delivering the maximum power to the load and the ambient temperature is above 70 C then the simultaneous charging of the battery can overheat the device. A basic protection scheme is implemented in STw5095 (activated with bit LSLIM in CR19): it limits the maximum gain of the
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STw5095
3 Functional Description
loudspeaker to -6 dB when VCCLS is above 4.2 V, and it removes the limit for VCCLS below 4.0 V. The loudspeaker gain is left unchanged if it is set below -6 dB with bits LSG. This event (VCCLS > 4.2 V) can generate, if enabled (bit VLSMSK in CR31), an IRQ signal.
3.10
Analog mixer
STw5095 can send to the output drivers the sum of stereo audio signals from 3 different sources, DA path (bit MIXDAC in CR17), Microphone Preamplifiers (bit MIXMIC in CR17) and Line In Amplifiers (bit MIXLIN in CR17). The mixer does not have a gain control on the inputs, therefore the user should reduce the levels of the input signals within the analog signal range. The stereo Analog Mixer is powered up with bits ENMIXL and ENMIXR in CR2.
3.11
AD path
The AD path converts audio signals from Microphone Preamplifiers (selected with bit ADMIC in CR17) and Line In Amplifiers (bit ADLIN in CR17) inputs to digital domain. If both inputs are selected then the sum of the two is converted. After AD conversion the audio data is resampled with a sample rate converter and then processed with the internal DSP. Two different filters are selectable in the DSP (bit ADVOICE in CR29): stereo Audio Filter, with DC offset removal and FIR image filtering; and a standard mono Voice-channel filter (uses left channel input and feeds both channel output). The AD path includes a digital gain control (ADCLG, ADCRG in CR12 and CR13 respectively) in the range -57 to +8 dB. The maximum gain from Mic Preamplifier to AD interface is then 47 dB. When Audio filter is selected in both AD and DA paths then DA audio data can be summed to AD data and sent to the AD Audio Interface (see DA2ADG in CR15). Left and Right channels can be independently switched on and off to save power, if needed (bits ENADCL and ENADCR in CR1)
3.12
DA path
The DA path converts digital data from the digital audio interface to analog domain and feeds it to the analog mixer. Incoming audio data is processed with a DSP where different filters are selectable (bit DAVOICE in CR29): Audio Filter, stereo, with FIR image filtering, bass and treble controls (bits BASS and TREBLE in CR14), de-emphasis filter; and a standard Voice-channel filter, mono (uses left channel input and feeds both channel output). A dynamic compression function is available for both audio and voice filters (bit DYNC in CR14). The DA path includes a digital gain control (DACLG, DACRG in CR10 and CR11 respectively) in the range -65 to 0 dB. AD to DA mixing (sidetone) can be enabled: see CR16 for details. Left and Right channel can be independently switched on and off to save power, if needed (bits ENDACL and ENDACR in CR1)
3.13
Analog-only operation
STw5095 can operate without AMCK master clock if analog-only functions are used. It is possible to mix Microphone and Line In preamplifiers signals and listen through headphones, loudspeaker or send them to line-out. The analog-only operation is enabled with bit ENOSC in CR0. When ENOSC=1 the AD and DA paths cannot be used.
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3 Functional Description
STw5095
In Analog Mode STw5095 can handle two different stereo audio signals, so it can be used as a front end for an external voice codec that does not include microphone preamplifiers and power drivers: mic signal is sent through Microphone preamplifiers directly to line out drivers (Transmit path), while Receive signal is sent through Line In amplifiers to the selected power drivers.
3.14
Automatic Gain Control (AGC)
STw5095 provides a digital Automatic Gain Control in AD path. The circuit can control the input gain at MIC preamplifier, Line In amplifier or both (bits ENAGCMIC and ENAGCLIN in CR35). When one input is selected, the center gain value used for the input is fixed with bits MICLG, MICRG, LINLG and LINRG in CR3 to CR6 (like in normal operation), then the AGC circuit adds to all the gains a value in the range -10.5 dB to +10.5 dB (or, extended with bit AGCRANGE in CR35, -21 dB to 21 dB), in order to obtain an average level at the digital interface output in the range -6 dB to -30 dB (selected with bits AGCLEV in CR35). The AGC added gain acts directly in the input gain, to avoid input saturation and improve S/N ratio, so it cannot exceed the input gain range. When MIC and Line-In inputs are selected simultaneously the control is performed on the sum of the two, preserving the balance fixed with input gains. Different values for Attack and Decay constants can be selected, depending on the kind of signal the AGC has to control (i.e. voice, music). The Attack and Decay time constants are related to the AD data rate (see bits AGCATT and AGCDEL in CR34).
3.15
Interrupt request: IRQ pin
STw5095 interrupt request feature can signal to a control device the occurrence of particular events. Two control registers are used to choose the behavior of IRQ pin: the first is a Status/ Event Register (CR32), where bits can represent the status of an internal function (i.e. a voltage is above or below a threshold) or an event (i.e. a voltage changed crossing a threshold); the second is a Mask Register (CR31) where if a bit in the mask is set to 1 then the corresponding bit in the Status/Event Register can affect IRQ pin status. The IRQ pin is always active low. At VCC power up an interrupt request is generated by the Power-On-Reset circuit that sets to 1 bits PORMSK in CR31 and POREV in CR32. After this event the PORMSK bit should be cleared by the user and bit IRQCMOS in CR33 should be set according to the application (open drain or CMOS). When an IRQ event occurs and SPI control interface is selected with no serial output pin it is still possible to identify the event (and relative status) that generated the interrupt request. This can be done by setting the IRQ mask/enable bits (in CR31) one at the time (with successive writings) and reading the IRQ pin status. A simple example of this is the headset plug-in detection: at first we set bit HSDETMSK=1 in CR31 (with all the other bits set to 0). If there is an interrupt request then we set HSDETMSK=0 and HSDETEN=1, so we can read the HSDET status at IRQ pin. Then we read CR32 to clear its content (even if no data is sent out).
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3 Functional Description
3.16
Headset plug-in and push-button detection
STw5095 can detect the plug-in of a microphone connector and the press/release event of a call/answer push-button. An application example can be found below, while specifications can be found in Section 9.4 on page 54. Figure 3. Plug-in and push-button detection application note
HDET 200nF VCCA 3k 1.5k Call/Answer Button 10F 200nF CAPMIC AUX1L AUX1R
STw5095
From Driver Generic Connector
3.17
Microphone biasing circuit
The Microphone Biasing Circuit can drive mono or stereo microphones and can switch them off when not needed in order to save the current used by the microphone biasing network. Two bits control the behavior of the microphone bias circuit: MBIAS in CR17 enables the circuit (fixed voltage at MBIAS pin), while bit MBIASPD in CR17 affects the behavior of MBIAS pin when the function is not enabled. In particular when MBIASPD=1 the MBIAS pin is pulled down, otherwise it is left in tristate mode. The specification for the microphone biasing circuit can be found in Section 9.6 on page 55, and an application note is shown in Section 17 on page 66.
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4 Control Registers
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4
4.1
CR# (hex)
CR0 (00h) CR1 (01h) CR2 (02h) CR3 (03h) CR4 (04h) CR5 (05h) CR6 (06h) CR7 (07h) CR8 (08h) CR9 (09h) CR10 (0Ah) CR11 (0Bh) CR12 (0Ch) CR13 (0Dh) CR14 (0Eh) CR15 (0Fh) CR16 (10h) CR17 (11h) CR18 (12h) CR19 (13h) CR20 (14h) CR21 (15h) CR22 (16h) CR23 (17h) CR24 (18h) CR25 (19h)
Control Registers
Summary
Description
Supply & Power Control #1 Power Control #2 Power Control #3 Mic Gain Left Mic Gain Right Line in Gain Left Line in Gain Right LO gain & LS gain HPL Gain HPR Gain DAC Digital Gain Left DAC Digital Gain Right ADC Digital Gain Left ADC Digital Gain Right Bass/Treble/De-emphasis DA to AD mixing gain AD to DA mix/sidetone gain Mixer Switches & Mic Bias Input Switches Drivers Control DAOCK Frequency Ls byte DAOCK Frequency Ms byte DA Clock Generator Control ADOCK Frequency Ls byte ADOCK Frequency Ms byte AD Clock Generator Control DAC Data IF Control ADC Data IF Control DAC&ADC Data IF Control Digital Filters Control Soft Reset & AMCK Range interrupt Mask Interrupt Status Misc. Control AGC Attack/Decay coeff. AGC Control RESERVED X X X X ADMAST X X DAMAST X X X X X X X X X DYNC X X MBIAS X X X MBIASPD IN2VCM VCML(1:0) ADMIC LINMUTE X ADLIN X X X X X X TREBLE(2:0) X
D7
POWERUP ENADCL ENLOL
D6
ENANA ENADCR ENLOR MICLA(2:0) MICRA(2:0) X X
D5
ENAMCK ENDACL ENHPL
D4
ENOSC ENDACR ENHPR
D3
ENPLL ENMICL ENHPVCM
D2
ENHSD ENMICR ENLS MICLG(4:0) MICRG(4:0)
D1
A24V ENLINL ENMIXL
D0
D12V ENLINR ENMIXR
Def.
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1001 0000 1001 0000 0011 0000 0011 0000 0011 0000 0000 0000 0000 0000 1000 0000 1000
X X LOG(2:0) X X
LINLG(4:0) LINRG(4:0) LSG(3:0) HPLG(4:0) HPRG(4:0) DACLG(5:0) DACRG(5:0) ADCLG(5:0) ADCRG(5:0) BASS(3:0) DA2ADG(4:0) AD2DAG(5:0) MIXMIC MIXLIN MICMUTE LSLIM MIXDAC MICLO
0000 0000 0000 0000 0000 0000 0000 0000 0010 0100 0101 1000 0000 0000 0000 0000
LINSEL(1:0) MUTELO MUTEHP
MICSEL(1:0) LSSEL(1:0)
DAOCKF(7:0) DAOCKF(15:8) DAMASTGEN ENDAOCK DAOCK512 DAPCMF(1:0)
0000 0000 0000 0000 0000 0000
ADOCKF(7:0) ADOCKF(15:8) ADMASTGEN ENADOCK ADOCK512 ADPCMF(1:0)
0000 0000
CR26 (1Ah) CR27 (1Bh) CR28 (1Ch) CR29 (1Dh) CR30 (1Eh) CR31 (1Fh) CR32 (20h) CR33 (21h) CR34 (22h) CR35 (23h) CR36 (24h)
X ADRTOL AMCKINV X SWRES VLSHEN VLSH X DACKP DAVOICE X PUSHBEN PUSHB X
DAFORM(2:0) ADFORM2:0) DASYNCP DA96K X HSDETEN HSDET SPIOHIZ AGCATT(3:0) ENAGCLIN X ENAGCMIC X AGCRANGE X DAMONO RXNH X VLSHMSK VLSHEV
DASPIM ADSPIM ADCKP ADVOICE AMCKSIN PUSHBMSK PUSHBEV HSDETMSK HSDETEV IRQCMOS ADSYNCP AD96K
DAWL(2:0) ADWL(2:0) ADMONO ADNH CKRANGE(2:0) OVFMSK OVFEV OVFDA PORMSK POREV OVFAD ADHIZ TXNH
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
SPIOSEL(1:0)
AGCDEC(3:0) AGCLEV(3:0) X X X X
0000 0000
Note: X reserved, write zero
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4.2
CR# (hex)
CR0 (00h) CR1 (01h) CR2 (02h)
Supply and power control
Description
Supply & Power Control #1 Power Control #2 Power Control #3
D7
POWERUP ENADCL ENLOL
D6
ENANA ENADCR ENLOR
D5
ENAMCK ENDACL ENHPL
D4
ENOSC ENDACR ENHPR
D3
ENPLL ENMICL ENHPVCM
D2
ENHSD ENMICR ENLS
D1
A24V ENLINL ENMIXL
D0
D12V ENLINR ENMIXR
Def.
0000 0000 0000 0000 0000 0000
Bits 7 6 5
Name POWERUP ENANA ENAMCK
Val. 1 0 1 0 1 0 1
CR0 Description All the enabled analog and digital blocks are in power up All the device is in power down The analog blocks can be enabled All the analog blocks are in power down AMCK clock input pin is enabled AMCK clock input pin is disabled The Internal Oscillator is enabled. The analog blocks use Oscillator clock The Internal Oscillator is in power down The PLL is enabled The PLL is in power down The Headset Plug-in Detector is enabled The Headset Plug-in Detector is disabled Analog Supply Pins voltage range is 2.4VDef. 0 0 0
4
ENOSC 0 1 0 1 0 1 0 1 0
0
3 2
ENPLL ENHSD
0 0
1
A24V
0
0
D12V
0
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4 Control Registers
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Bits 7 6 5 4 3 2 1 0
Name ENADCL ENADCR ENDACL ENDACR ENMICL ENMICR ENLINL ENLINR
Value 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Value 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
CR1 Description The left channel A/D converter is enabled The left channel A/D converter is in power down The right channel A/D converter is enabled The right channel A/D converter is in power down The left channel D/A converter is enabled The left channel D/A converter is in power down The right channel D/A converter is enabled The right channel D/A converter is in power down The left channel microphone preamplifier is enabled The left channel microphone preamplifier is in power down The right channel microphone preamplifier is enabled The right channel microphone preamplifier is in power down The left channel line-in preamplifier is enabled The left channel line-in preamplifier is in power down The right channel line-in preamplifier is enabled The right channel line-in preamplifier is in power down CR2 Description The left channel line out driver is enabled The left channel line out driver is in power down (default) The right channel line out driver is enabled The right channel line out driver is in power down (default) The left channel headphones driver is enabled The left channel headphones driver is in power down (default) The right channel headphones driver is enabled The right channel headphones driver is in power down (default) The headphones reference voltage generator is enabled The headphones reference voltage generator is in power down (def) The 8 loudspeaker amplifier is enabled The 8 loudspeaker amplifier is in power down (default) The left channel analog output mixer is enabled The left channel analog output mixer is in power down (default) The right channel analog output mixer is enabled The right channel analog output mixer is in power down (default)
Def. 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Name ENLOL ENLOR ENHPL ENHPR ENHPVCM ENLS ENMIXL ENMIXR
Def. 0 0 0 0 0 0 0 0
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4 Control Registers
4.3
CR# (hex)
CR3 (03h) CR4 (04h) CR5 (05h) CR6 (06h) CR7 (07h) CR8 (08h) CR9 (09h) CR10 (0Ah) CR11 (0Bh) CR12 (0Ch) CR13 (0Dh)
Gains
Description
Mic Gain Left Mic Gain Right Line in Gain Left Line in Gain Right LO gain & LS gain HPL Gain HPR Gain DAC Digital Gain Left DAC Digital Gain Right ADC Digital Gain Left ADC Digital Gain Right X X X X X X X X X X X X X X X
D7
D6
MICLA(2:0) MICRA(2:0) X X
D5
D4
D3
D2
MICLG(4:0) MICRG(4:0)
D1
D0
Def.
0000 0000 0000 0000 0000 1001 0000 1001 0000 0011 0000 0011 0000 0011 0000 0000 0000 0000 0000 1000 0000 1000
X X LOG(2:0) X X
LINLG(4:0) LINRG(4:0) LSG(3:0) HPLG(4:0) HPRG(4:0) DACLG(5:0) DACRG(5:0) ADCLG(5:0) ADCRG(5:0)
Bits
Name CR3 Name CR4
Value
CR3 and CR4 Description Left (CR3) and Right (CR4) Channels Microphone Attenuation 0.0 dB Gain (default) -1.5 dB Gain -3.0 dB Gain ...step 1.5 dB -9.0 dB Gain -12.0 dB Gain Left (CR3) and Right (CR4) Channels Microphone Gain 0.0 dB Gain (default) 1.5 dB Gain 3.0 dB Gain ...step 1.5 dB 39.0 dB Gain
Def.
7-5
MICLA(2:0) MICRA(2:0)
000 001 010 ... 110 111 00000 00001 00010 ... 11010
000
4-0
MICLG(4:0) MICRG(4:0)
00000
Bits
Name CR5 Name CR6
Value
CR5 and CR6 Description Left (CR5) and Right (CR6) Channels Line In Gain 18.0 dB Gain 16.0 dB Gain 14.0 dB Gain ...step 2.0 dB 0.0 dB Gain (default) ...step 2.0 dB -20.0 dB Gain
Def.
4-0
LINLG(4:0) LINRG(4:0)
00000 00001 00010 ... 01001 ... 10011
01001
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Bits
Name
Value
CR7 Description Left and Right Channel Line Out Drivers Gain
Def.
6-4
LOG(2:0)
000 001 010 ... 110
Gain to Differential Output -18.0 dB Gain (default) -15.0 dB Gain -12.0 dB Gain ...step 3 dB 00 dB Gain 8 Loudspeaker Gain 6.0 dB Gain 4.0 dB Gain 2.0 dB Gain 0.0 dB Gain (default) ...step 2.0 dB -24.0 dB Gain
Equivalent Single-Ended Gain -24.0 dB Gain (default) -21.0 dB Gain -18.0 dB Gain ...step 3 dB -6.0 dB Gain
000
3-0
LSG(3:0)
0000 0001 0010 0011 ... 1111
0011
Bits
Name CR8 Name CR9
Value
CR8 and CR9 Description Left (CR8) and Right (CR9) Channels Headphones Driver Gain 0.0 dB Gain -2.0 dB Gain -4.0 dB Gain -6.0 dB Gain (default) ...step 2.0 dB -40.0 dB Gain
Def.
4-0
HPLG(4:0) HPRG(4:0)
00000 00001 00010 00011 ... 10100
00011
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4 Control Registers
Bits
Name CR10 Name CR11
Value
CR10 and CR11 Description Left (CR10) and Right (CR11) Channels DAC Digital Gain 0.0 dB Gain (default) -1.0 dB Gain -2.0 dB Gain -3.0 dB Gain -4.0 dB Gain -5.0 dB Gain -6.0 dB Gain -7.0 dB Gain -8.0 dB Gain -9.0 dB Gain -10.0 dB Gain -11.0 dB Gain -12.0 dB Gain -13.0 dB Gain -14.0 dB Gain -15.0 dB Gain -16.0 dB Gain -17.0 dB Gain -18.0 dB Gain -20.0 dB Gain -22.0 dB Gain -24.0 dB Gain -26.0 dB Gain -28.0 dB Gain -30.0 dB Gain -32.0 dB Gain -34.0 dB Gain -36.0 dB Gain -38.0 dB Gain -41.0 dB Gain -44.0 dB Gain -47.0 dB Gain -50.0 dB Gain -53.0 dB Gain -56.0 dB Gain -59.0 dB Gain -65.0 dB Gain - dB Gain
Def.
5-0
DACLG(5:0) DACRG(5:0)
000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101
000000
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4 Control Registers
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Bits
Name CR12 Name CR13
Value
CR12 and CR13 Description Left (CR12) and Right (CR13) Channels ADC Digital Gain 8.0 dB Gain 7.0 dB Gain 6.0 dB Gain 5.0 dB Gain 4.0 dB Gain 3.0 dB Gain 2.0 dB Gain 1.0 dB Gain 0.0 dB Gain (default) -1.0 dB Gain -2.0 dB Gain -3.0 dB Gain -4.0 dB Gain -5.0 dB Gain -6.0 dB Gain -7.0 dB Gain -8.0 dB Gain -9.0 dB Gain -10.0 dB Gain -11.0 dB Gain -12.0 dB Gain -14.0 dB Gain -16.0 dB Gain -18.0 dB Gain -20.0 dB Gain -22.0 dB Gain -24.0 dB Gain -26.0 dB Gain -28.0 dB Gain -30.0 dB Gain -33.0 dB Gain -36.0 dB Gain -39.0 dB Gain -42.0 dB Gain -45.0 dB Gain -48.0 dB Gain -51.0 dB Gain -57.0 dB Gain - dB Gain
Def.
5-0
ADCLG(5:0) ACDRG(5:0)
000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110
001000
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4 Control Registers
4.4
CR# (hex)
CR14 (0Eh) CR15 (0Fh) CR16 (10h)
DSP control
Description
Bass/Treble/De-emphasis DA to AD mixing gain AD to DA mix/sidetone gain
D7
DYNC X X
D6
D5
TREBLE(2:0)
D4
D3
D2
BASS(3:0) DA2ADG(4:0)
D1
D0
Def.
0000 0000 0000 0000 0000 0000
X X
X
AD2DAG(5:0)
Bits 7
Name DYNC 1 0
Value
CR14 Description Audio Dynamic Compression in D/A path is enabled Audio Dynamic Compression in D/A path is disabled Treble Control in D/A path +6.0 dB Treble Gain +4.0 dB Treble Gain +2.0 dB Treble Gain 0.0 dB Treble Gain -2.0 dB Treble Gain -4.0 dB Treble Gain -6.0 dB Treble Gain De-emphasis filter enabled Bass Control in D/A path +12.5 dB Bass Gain +10.0 dB Bass Gain +7.5 dB Bass Gain +5.0 dB Bass Gain +2.5 dB Bass Gain 0.0 dB Bass Gain -2.5 dB Bass Gain -5.0 dB Bass Gain -7.5 dB Bass Gain -10.0 dB Bass Gain -12.5 dB Bass Gain
Def. 0
6-4
TREBLE(2:0)
011 010 001 000 111 110 101 100 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011
000
3-0
BASS(3:0)
0000
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4 Control Registers
STw5095
Bits
Name
Value
CR15 Description DA to AD mixing (Audio filter in D/A and A/D path selected) DA to AD mixing Disabled (default) +2.0 dB Gain 0.0 dB Gain -2.0 dB Gain -4.0 dB Gain -6.0 dB Gain -8.0 dB Gain -10.0 dB Gain -12.0 dB Gain -14.0 dB Gain -16.0 dB Gain -18.0 dB Gain -20.0 dB Gain -22.0 dB Gain -24.0 dB Gain -26.0 dB Gain -28.0 dB Gain -30.0 dB Gain -32.0 dB Gain -34.0 dB Gain -36.0 dB Gain -38.0 dB Gain -40.0 dB Gain
Def.
4-0
DA2ADG(4:0)*
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110
00000
* When Voice filter in D/A or A/D path is selected this function is disabled Note: D/A to A/D mixing is performed at AD data rate, so if A/D and D/A rates are different then asynchronous sampling artifacts may occur.
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4 Control Registers
Bits
Name
Value
CR16 Description AD to DA mixing (sidetone) AD to DA mixing Disabled (default) -1.0 dB Gain -2.0 dB Gain -3.0 dB Gain -4.0 dB Gain -5.0 dB Gain -6.0 dB Gain -7.0 dB Gain -8.0 dB Gain -9.0 dB Gain -10.0 dB Gain -11.0 dB Gain -12.0 dB Gain -13.0 dB Gain -14.0 dB Gain -15.0 dB Gain -16.0 dB Gain -17.0 dB Gain -18.0 dB Gain -19.0 dB Gain -20.0 dB Gain -21.0 dB Gain -22.0 dB Gain -23.0 dB Gain -24.0 dB Gain -25.0 dB Gain -26.0 dB Gain -27.0 dB Gain -28.0 dB Gain -29.0 dB Gain -30.0 dB Gain -31.0 dB Gain -32.0 dB Gain -33.0 dB Gain -34.0 dB Gain -35.0 dB Gain -36.0 dB Gain -37.0 dB Gain -38.0 dB Gain -39.0 dB Gain -40.0 dB Gain -41.0 dB Gain -42.0 dB Gain
Def.
5-0
AD2DAG(5:0)
000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010
000000
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4 Control Registers
STw5095
4.5
CR# (hex)
CR17 (11h) CR18 (12h) CR19 (13h)
Analog functions
Description
Mixer Switches & Mic Bias Input Switches Drivers Control
D7
MBIAS X
D6
MBIASPD IN2VCM VCML(1:0)
D5
ADMIC LINMUTE X
D4
ADLIN
D3
MIXMIC
D2
MIXLIN MICMUTE LSLIM
D1
MIXDAC
D0
MICLO
Def.
0000 0000 0010 0100 0101 1000
LINSEL(1:0) MUTELO MUTEHP
MICSEL(1:0) LSSEL(1:0)
Bits 7
Name MBIAS
Value 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
CR17 Description Microphone Bias Enabled (2.1V typ at MBIAS Pin) Microphone Bias Disabled MBIAS Pin is pulled down when Microphone Bias is disabled MBIAS Pin is in High Impedance state when Microphone Bias is disabled Microphone Preamplifiers are connected to AD path Microphone Preamplifiers are not connected to AD path Line In Preamplifiers are connected to AD path Line In Preamplifiers are not connected to AD path Microphone Preamplifiers are connected to Mixers Microphone Preamplifiers are not connected to Mixers Line In Preamplifiers are connected to Mixers Line In Preamplifiers are not connected to Mixers Stereo DAC path is connected to Mixers Stereo DAC path is not connected to Mixers Microphone Preamplifiers are connected to Line Out Drivers Mixers are connected to Line Out Drivers
Def. 0
6
MBIASPD
0
5 4 3 2 1 0
ADMIC ADLIN MIXMIC MIXLIN MIXDAC MICLO
0 0 0 0 0 0
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4 Control Registers
Bits 6 5
Name IN2VCM LINMUTE 1 0 1 0
Value
CR18 Description Unused Analog input pins are biased to Common Mode voltage Unused Analog input pins are in high impedance state Line In Preamplifiers are muted Line In Preamplifiers are not muted Input Pins connected to Line In Preamplifiers (if LINMUTE=0)
Def. 0 1
4-3
LINSEL(1:0)
00 01 10 11 1 0
LINEIN AUX1 AUX2 AUX3
(LINEINL, LINEINR) (AUX1L, AUX1R) (AUX2LP-AUX2LN, AUX2RP-AUX2RN) 00
(AUX3L, AUX3R)
1
2
MICMUTE
Microphone Preamplifiers are muted Microphone Preamplifiers are not muted Input Pins connected to Microphone Preamplifiers (if MICMUTE=0)
1-0
MICSEL(1:0)
00 01 10 11
MIC AUX1 AUX2 AUX3
(MICLP-MICLN, MICRP-MICRN) (AUX1L, AUX1R) (AUX2LP-AUX2LN, AUX2RP-AUX2RN) 00
(AUX3L, AUX3R)
Bits
Name
Value
CR19 Description Common Mode Voltage Level for Line Out and Headphones drivers 1.20 V 1.35 V (default) 1.50 V 1.65 V Line Out Drivers are muted Line Out Drivers are not muted Headphones Drivers (HP) are muted Headphones Drivers (HP) are not muted Loudspeaker Driver (LS) gain is limited when VCCLS is above 4.2V typ Loudspeaker Driver (LS) gain is not limited Mute Right Left Mono Loudspeaker Driver (LS) is muted Right Channel Mixer only connected to Loudspeaker driver Left Channel Mixer only connected to Loudspeaker driver (Left + Right)/2 Channel Mixers connected to Loudspeaker driver
Def.
7-6
VCML(1:0)
00 01 10 11 1 0 1 0 1
01
4 3
MUTELO MUTEHP
1 1
2
LSLIM 0 00 01
0
1-0
LSSEL(1:0)
10 11
00
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4 Control Registers
STw5095
4.6
CR# (hex)
CR20 (14h) CR21 (15h) CR22 (16h) CR23 (17h) CR24 (18h) CR25 (19h)
Digital audio interfaces master mode and clock generators
Description
DAOCK Frequency Ls byte DAOCK Frequency Ms byte DA Clock Generator Control ADOCK Frequency Ls byte ADOCK Frequency Ms byte AD Clock Generator Control X X ADMAST X X DAMAST
D7
D6
D5
D4
D3
D2
D1
D0
Def.
0000 0000 0000 0000
DAOCKF(7:0) DAOCKF(15:8) DAMASTGEN ENDAOCK DAOCK512 DAPCMF(1:0)
0000 0000 0000 0000 0000 0000
ADOCKF(7:0) ADOCKF(15:8) ADMASTGEN ENADOCK ADOCK512 ADPCMF(1:0)
0000 0000
Bits
Name CR21-20 Name CR24-23
Value
CR21-20 and CR24-23 Description The following formulas can be used to obtain the value of K for the desired FS or OCK respectively in the clock generator
K ( FS ) = round 2
25
Def.
FS -------------------------------------------------------------- AMCK MCKCOEFF
K ( OCK ) = round 2
25
OCK ----------------------------------------------------------------------------------- AMCK MCKCOEFF OSR
15-0
DAOCKF(15:0) ADOCKF(15:0)
K FS: OCK: AMCK: MCKCOEFF: OSR: Data Rate (DA_SYNC or AD_SYNC frequency in Master Mode) Oversampled Clock Frequency (DA_OCK or AD_OCK) Input Master Clock Frequency See CR30 for definition See bit 2 in CR22 and CR25
0000h
Note: CR21-20 and CR24-23 are meaningful in Master Mode Only.
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4 Control Registers
Bits
Name CR22 (Name CR25) DAMAST (ADMAST) DAMASTGEN (ADMASTGEN) ENDAOCK (ENADOCK)
Value 1 0 1 0 1 0 1 0
CR22 and CR25 Description DA (AD) Audio interface is in Master Mode (low impedance output) DA (AD) Audio interface is in Slave Mode (high impedance input) DA (AD) Master Generator is enabled DA (AD) Master Generator is disabled DA_OCK (AD_OCK) Output Clock is enabled DA_OCK (AD_OCK) Output Clock is disabled Definition of DA_OSR (AD_OSR) DA_OCK/DA_SYNC (AD_OCK/AD_SYNC) Ratio In Master Mode is 512 DA_OCK/DA_SYNC (AD_OCK/AD_SYNC) Ratio In Master Mode is 256 DA_CK/DA_SYNC (AD_CK/AD_SYNC) Ratio in PCM Master Mode - 16 when CR26 DAWL=000 (CR27 ADWL=000) - 32 when CR26 DAWL000 (CR27 ADWL000) - 64 - 128 - 256 when CR22 DAOCK512=0 (CR25 ADOCK512=0) - 512 when CR22 DAOCK512=1 (CR25 ADOCK512=1)
Def.
5 4 3
0 0 0
2
DAOCK512 (ADOCK512)
0
1-0
DAPCMF(1:0) (ADPCMF(1:0))
00 00 01 10 11 11
00
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4 Control Registers
STw5095
4.7
CR# (hex)
CR26 (1Ah) CR27 (1Bh) CR28 (1Ch)
Digital audio interfaces
Description
DAC Data IF Control ADC Data IF Control DAC&ADC Data IF Control
D7
X ADRTOL AMCKINV
D6
D5
DAFORM(2:0) ADFORM2:0)
D4
D3
DASPIM ADSPIM
D2
D1
DAWL(2:0) ADWL(2:0)
D0
Def.
0000 0000 0000 0000
DACKP
DASYNCP
DAMONO
ADCKP
ADSYNCP
ADMONO
ADHIZ
0000 0000
Bits
Name
Value
CR26 Description DA Audio Interface Format Selection
Def.
6-4
DAFORM(2:0)
000 001 010 011 100 111 1 0
Delayed Format (I2S Compatible) Left Aligned Format Right Aligned Format DSP Format SPI Format PCM Format (uses left channel) DA interface in SPI mode receives one word for both channels DA interface in SPI mode receives two words (alternated, left channel first) DA interface word length 16 bit 18 bit 20 bit 24 bit 32 bit CR27 Description AD Right Channel sent to PCM I/F (must set ENADCR=0 in CR1) Normal Operation AD Audio Interface Format Selection Delayed Format (I2S compatible) Left Aligned Format Right Aligned Format DSP Format SPI Format PCM Format (sends out left channel) AD interface in SPI mode sends one channel (left) AD interface in SPI mode sends two channels (alternated, left first) AD interface word length 16 bit 18 bit 20 bit 24 bit 32 bit
000
3
DASPIM
0
2-0
DAWL(2:0)
000 001 010 011 100 Value 1 0
000
Bits 7
Name ADRTOL
Def. 0
6-4
ADFORM(2:0)
000 001 010 011 100 111 1 0 000 001 010 011 100
000
3
ADSPIM
0
2-0
ADWL(2:0)
000
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4 Control Registers
Bits 7 6
Name AMCKINV DACKP
Value 1 0 1 0 1 0 AMCK is inverted AMCK is not inverted
CR28 Description
Def. 0 0
DA Bit Clock Pin (DA_CK) polarity is inverted DA Bit Clock Pin (DA_CK) polarity is not inverted DSP and PCM Formats in DA Interface Non Delayed format Delayed Format
5
DASYNCP 1 0 1 Delayed, Left-aligned, Right-aligned and SPI Formats in DA Interface DA Sync Pin (DA_SYNC) polarity is inverted DA Sync Pin (DA_SYNC) polarity is not inverted Mono Mode: (L+R)/2 from Audio Interface is used on both DAC channels Stereo Mode AD Bit Clock Pin (AD_CK) polarity is inverted AD Bit Clock Pin (AD_CK) polarity is not inverted DSP and PCM Formats in AD Interface Non Delayed format Delayed Format Delayed, Left-aligned, Right-aligned and SPI Formats in AD Interface DA Sync Pin (DA_SYNC) polarity is inverted DA Sync Pin (DA_SYNC) polarity is not inverted Mono Mode: (L+R)/2 from ADC is sent to both channels in the Audio Interface Stereo Mode AD data pin (AD_DATA) is in high impedance state when no data is available AD data pin (AD_DATA) is forced to 0 when no data is available
0
4
DAMONO 0 1 0 1 0
0
3
ADCKP
0
2
ADSYNCP 1 0 1
0
1
ADMONO 0 1
0
0
ADHIZ 0
0
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4 Control Registers
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4.8
CR# (hex)
CR29 (1Dh) CR30 (1Eh)
Digital filters, software reset and master clock control
Description
Digital Filters Control Soft Reset & AMCK Range
D7
X SWRES
D6
DAVOICE X
D5
DA96K X
D4
RXNH X
D3
ADVOICE AMCKSIN
D2
AD96K
D1
ADNH CKRANGE(2:0)
D0
TXNH
Def.
0000 0000 0000 0000
Bits 6 5 4 3 2 1 0
Name DAVOICE DA96K RXNH ADVOICE AD96K ADNH TXNH
Value 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Value 1 0 1 0
CR29 Description DA path Voice RX filter is enabled (single channel, left used) DA path Audio filters are enabled DA path data rate is in the range 88 kHz to 96 kHz DA path data rate is in the range 8 kHz to 48 kHz DA path High pass Voice RX filter is disabled DA path High pass Voice RX filter is enabled (300Hz @ 8kHz rate) AD path Voice TX filter is enabled (single channel, left used) AD path Audio filters are enabled AD path data rate is in the range 88 kHz to 96 kHz AD path data rate is in the range 8 kHz to 48 kHz AD path Audio DC filter is disabled AD path Audio DC filter is enabled AD path High pass Voice TX filter is disabled AD path High pass Voice TX filter is enabled (300Hz @ 8kHz rate) CR30 Description Software reset: All registers content is reset to the default value Control Register content is left unchanged Signal at AMCK pin is a sinusoid Signal at AMCK pin is a square wave AMCK range MHz to 6.0 MHz MHz to 8.0 MHz MHz to 12.0 MHz MHz to 16.0 MHz MHz to 24.0 MHz MHz to 32.0 MHz MCKCOEFF 8.0 6.0 4.0 3.0 2.0 1.5
Def. 0 0 0 0 0 0 0
Bits 7 3
Name SWRES AMCKSIN
Def. 0 0
2-0
CKRANGE(2:0)
000 001 010 011 100 101
4.0 6.0 8.0 12.0 16.0 24.0
000
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4 Control Registers
4.9
CR# (hex)
CR31 (1Fh) CR32 (20h) CR33 (21h)
Interrupt control and control interface SPI out mode
Description
interrupt Mask Interrupt Status Misc. Control
D7
VLSHEN VLSH X
D6
PUSHBEN PUSHB X
D5
HSDETEN HSDET SPIOHIZ
D4
VLSHMSK VLSHEV
D3
PUSHBMSK PUSHBEV
D2
HSDETMSK HSDETEV IRQCMOS
D1
OVFMSK OVFEV OVFDA
D0
PORMSK POREV OVFAD
Def.
0000 0000 0000 0000 0000 0000
SPIOSEL(1:0)
Bits 7 6 5 4 3 2 1 0
Name VLSHEN PUSHBEN HSDETEN VLSHMSK PUSHBMSK HSDETMSK OVFMSK PORMSK
Value 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
CR31 Description VLSH status can be seen at IRQ output VLSH status is masked PUSHB status can be seen at IRQ output PUSHB status is masked HSDET status can be seen at IRQ output HSDET status is masked VLSH event can be seen at IRQ output VLSH event is masked PUSHB event can be seen at IRQ output PUSHB event is masked HSDET event can be seen at IRQ output HSDET event is masked OVF event can be seen at IRQ output OVF event is masked POR event can be seen at IRQ output POR event is masked
Def. 0 0 0 0 0 0 0 0
Note:
Value at IRQ pin is:
IRQ = (1 or Z) when (CR31 & CR32) = 00 hex 0 when (CR31 & CR32) 00 hex
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4 Control Registers
STw5095
Bits
Name
Read only 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VCCLS is above 4.2 V VCCLS is below 4.0 V
CR32 Description
Def.
7
VLSH*
0
6 5 4 3 2 1 0
PUSHB* HSDET* VLSHEV PUSHBEV HSDETEV OVFEV POREV
Headset Button is pressed Headset Button is released Headset Connector is inserted Headset Connector is not inserted VLSH bit has changed VLSH bit has not changed Headset Button Status has changed Headset Button Status has not changed Headset Connector Status has changed Headset Connector Status has not changed An Audio Data overflow has occurred in DSP No Audio Data overflow has occurred in DSP Device was reset by Power-On-Reset Device was not reset by Power-On-Reset
0 0 0 0 0 0 0
Note: content of bits 4 to 0 in CR32 is cleared after reading, while it is left unchanged if accessed for writing. *Bits 7 to 5 represent the status when the Control register is read, not when the event occurred.
Bits
Name
Val. 1
CR33 Description SPI Control Interface Out Pin is set to high impedance state when inactive SPI Control Interface Out Pin is set to zero when inactive Out Pin Selection for SPI Control Interface No output. Control registers cannot be read in SPI mode SPI Output sent to IRQ pin SPI Output sent to DA_OCK pin SPI Output sent to AD_OCK pin IRQ Interrupt Request Pin is set to CMOS (active low) IRQ Interrupt Request Pin is set to Pull Down An overflow (saturation) occurred in DA path No overflow occurred in DA channel An overflow (saturation) occurred in AD path No overflow occurred in AD channel
Def.
5
SPIOHIZ 0 00 01 10 11 1 0 1 0 1 0
0
4-3
SPIOSEL(1:0)
00
2 1 0
IRQCMOS OVFDA OVFAD
0 0 0
Note: content of bits 1 to 0 in CR33 is cleared after reading, while it is left unchanged if accessed for writing.
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4 Control Registers
4.10
CR# (hex)
CR34 (22h) CR35 (23h)
AGC
Description
AGC Attack/Decay coeff. AGC Control X
D7
D6
D5
D4
D3
D2
D1
D0
Def.
0000 0000 0000 0000
AGCATT(3:0) ENAGCLIN ENAGCMIC AGCRANGE
AGCDEC(3:0) AGCLEV(3:0)
Bits
Name
Value
CR34 Description AGC Attack Time Constant; FS=AD data rate
Def.
7-4
AGCATT(3:0)
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101
Audio filter in AD path 4096 / FS 2048 / FS 1365 / FS 1024 / FS 683 / FS 512 / FS 341 / FS 256 / FS 171 / FS 128 / FS 85 / FS 64 / FS 43 / FS 32 / FS
Voice filter in AD path 8192 / FS 4096 / FS 2731 / FS 2048 / FS 1365 / FS 1024 / FS 683 / FS 512 / FS 341 / FS 256 / FS 171 / FS 128 / FS 85 / FS 64 / FS
0000
AGC Decay Time Constant; FS=AD data rate 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Audio filter in AD path 65536 / FS 32768 / FS 21845 / FS 16384 / FS 10923 / FS 8192 / FS 5461 / FS 4096 / FS 2731 / FS 2048 / FS 1365 / FS 1024 / FS 683 / FS 512 / FS 341 / FS 256 / FS Voice filter in AD path 131072/ FS 65536 / FS 43691 / FS 32768 / FS 21845 / FS 16384 / FS 10923 / FS 8192 / FS 5461 / FS 4096 / FS 2731 / FS 2048 / FS 1365 / FS 1024 / FS 683 / FS 512 / FS
3-0
AGCDEC(3:0)
0000
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4 Control Registers
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Bits 6 5 4
Name ENAGCLIN ENAGCMIC AGCRANGE
Value 1 0 1 0 1 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
CR35 Description AGC control on AD path acts on Line In Gain AGC control on AD path does not act on Line In Gain AGC control on AD path acts on Mic Gain AGC control on AD path does not act on Mic Gain AGC action range is -21.0 dB to +21.0 dB AGC action range is -10.5 dB to +10.5 dB AGC requested output level -30.0 dB Gain -30.0 dB Gain -27.0 dB Gain -24.0 dB Gain -21.0 dB Gain -18.0 dB Gain -15.0 dB Gain -12.0 dB Gain -9.0 dB Gain -6.0 dB Gain
Def. 0 0 0
3-0
AGCLEV(3:0)
0000
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5 Control Interface and Master Clock
5
5.1
Control Interface and Master Clock
Control interface I2C mode
Figure 4. Control interface I2C format
ACK ACK REG n DATA IN STOP ACK ACK REG n DATA IN ACK ACK REG n+m DATA IN m+1 data bytes STOP ACK ACK
WRITE SINGLE BYTE
START
DEVICE ADDRESS
0 0 1 1 0 1 AS 0
REG n ADDRESS
WRITE MULTI BYTE
START
DEVICE ADDRESS
0 0 1 1 0 1 AS 0
REG n ADDRESS
CURRENT ADDR READ SINGLE BYTE
START
ACK DEVICE ADDRESS
0 0 1 1 0 1 AS 1
NO ACK
Current REG DATA OUT STOP ACK ACK ACK NO ACK
CURRENT ADDR READ MULTI BYTE
START
DEVICE ADDRESS
0 0 1 1 0 1 AS 1
Current REG DATA OUT
Curr REG+m DATA OUT m+1 data bytes STOP
RANDOM ADDR READ SINGLE BYTE
START
ACK DEVICE ADDRESS
0 0 1 1 0 1 AS 0
ACK DEVICE ADDRESS
0 0 1 1 0 1 AS 1
ACK REG n DATA OUT
NO ACK
REG n ADDRESS START ACK ACK
STOP ACK DEVICE ADDRESS
0 0 1 1 0 1 AS 1
RANDOM ADDR READ MULTI BYTE
START
ACK REG n DATA OUT
ACK REG n+m DATA OUT
NO ACK
DEVICE ADDRESS
0 0 1 1 0 1 AS 0
REG n ADDRESS START
m+1 data bytes
STOP
Note:
CMOD pin tied to GND
Figure 5. Control interface: I2C format timing
SDA
tBUF tHD (STA) tLOW tHD (DAT) tHIGH tSU (DAT) tSU (STA) tHD (STA) tSU (STO)
SCLK
tR
tF
P
S
Sr
P
P = STOP S = START Sr = START repeated
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5 Control Interface and Master Clock
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Control interface timing with IC format
Symbol fSCL tHIGH tLOW tR tF tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tBUF Parameter Clock frequency Clock pulse width high Clock pulse width low SDA and SCLK rise time SDA and SCLK fall time Start condition hold time Start condition setup time Data input hold time Data input setup time Stop condition setup time Bus free time 600 600 0 250 600 1300 600 1300 1000 300 Test Condition Min. Typ. Max. 400 Unit kHz ns ns ns ns ns ns ns ns ns ns
5.2
Control interface SPI mode
Figure 6. Control Interface SPI format(1)
CSB SCLK SDIN
W/R A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
8 bit Address
8 bit Data
SDO
SPIOHIZ=1
D7
D6
D5
D4
D3
D2
D1
D0
8 bit Data
1. CMOD pin tied to VCCIO; SDO pin position selected with bits SPIOSEL in CR33.
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Figure 7. Control interface: SPI format timing
5 Control Interface and Master Clock
tHICS
CSB
tSCSF tPSCK tLSCK tHSCK tHCS tSCSR
SCLK
0
tSDI tHDI
8
15
SDIN
W/R
tDDOF
SPIOHIZ=1 SPIOHIZ=0
D7
tDDO
D0
tDDOL
SDO
D7
D0
Control interface signal timing with SPI format
Symbol tHICS tSCSR tSCSF tHCS tSDI tHDI tDDOF tDDO tDDOL tPSCK tHSCK tLSCK Parameter CSB pulse width high Setup time CSB rising edge to SCLK rising edge Setup time CSB falling edge to SCLK rising edge Hold time CSB rising edge from SCLK rising edge Setup time SDIN to SCLK rising edge Hold time SDIN from SCLK rising edge SDO first Delay time from SCLK falling edge SDO Delay time from SCLK falling edge SDO Delay time from CSB rising edge Period of SCK SCK pulse width high SCK pulse width low Measured from VIH to VIH Measured from VIL to VIL 100 40 40 Test Condition Min. 80 20 20 20 20 20 30 20 30 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns
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5.3
Master clock timing
AMCK timing
Symbol tCKDC Parameter AMCK duty cycle AMCK range 4 MHz-8 MHz 8 MHz-32 MHz Min. 45 40 Typ. Max. 55 60 Unit % %
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6 Audio Interfaces
6
Figure 8.
Audio Interfaces
Audio interfaces formats: delayed, left and right justified
I2S format (delayed) with default polarity settings, ADHIZ=0
DA_SYNC/ AD_SYNC DA_CK/ AD_CK
1 AD_CK/DA_CK 1 AD_CK/DA_CK n-1 n LSB n LSB 1 MSB 1 MSB 2 n-1 n LSB n LSB
DA_DATA
1 MSB 1 MSB
2
n-bit word Left data 2 n-1
n-bit word Right data 2 n-1
AD_DATA
n-bit word Left data
n-bit word Right data
Left justified format with default polarity settings, ADHIZ=0
DA_SYNC/ AD_SYNC DA_CK/ AD_CK DA_DATA
1 MSB 1 MSB 2 n-1 n LSB n LSB 1 MSB 1 MSB 2 n-1 n LSB n LSB
n-bit word Left data 2 n-1
n-bit word Right data 2 n-1
AD_DATA
n-bit word Left data
n-bit word Right data
Right justified format with default polarity settings
32 AD_CK/DA_CK
32 AD_CK/DA_CK
DA_SYNC/ AD_SYNC DA_CK/ AD_CK DA_DATA
1 MSB 1 MSB 2 n-1 n LSB n LSB 1 MSB 1 MSB 2 n-1 n LSB n LSB
n-bit word Left data 2 n-1
n-bit word Right data 2 n-1
AD_DATA
n-bit word Left data
n-bit word Right data
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6 Audio Interfaces
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Figure 9.
Audio interfaces formats: DSP, SPI and PCM
DSP format delayed and non-delayed (default AD_CK/DA_CK polarity, ADHIZ=0)
DA_SYNC/ AD_SYNC DA_CK/ AD_CK DA_DATA
{
SYNCP=0
SYNCP=1
1 MSB 1 MSB
2
n-1
n-bit word Left data 2 n-1
n 1 LSB MSB n 1 LSB MSB
2
n-1
n-bit word Right data 2 n-1
n LSB n LSB
AD_DATA
n-bit word Left data
n-bit word Right data
SPI format (slave only) (default AD_CK/DA_CK polarity, ADHIZ=1 - Stereo or Mono)
DA_SYNC/ AD_SYNC DA_CK/ AD_CK DA_DATA
1 MSB x 1 MSB 2 3 n-1 n LSB n LSB High impedance x 1 MSB 1 MSB 2 3
n-bit word Left/Mono data 2 3 n-1
n-bit word Right/Mono data 2 3
AD_DATA
n-bit word Left/Mono data
n-bit word Right/Mono data
PCM format (default AD_CK/DA_CK polarity, ADHIZ=1)
DA_SYNC/ AD_SYNC
{
SYNCP=0
SYNCP=1
DA_CK/ AD_CK DA_DATA
1 MSB 1 MSB 2 3 n-bit word Mono data 2 3 n-bit word Mono data n-1 n-1 n LSB n LSB High impedance 1 MSB 1 MSB
AD_DATA
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Figure 10. Audio interface timings: Master mode
DA_SYNC/ AD_SYNC
tDSY
6 Audio Interfaces
DA_CK/ AD_CK
{
CKP=0
CKP=1
tSDDA tHDDA
DA_DATA
tDAD ADHIZ=1 ADHIZ=0 tDAD ADHIZ=1 ADHIZ=0 ADHIZ=1 ADHIZ=0 tDAD tDADZ ADHIZ=1 ADHIZ=0
AD_DATA PCM format only
AD_DATA All other formats
Figure 11. Audio interface timing: Slave mode
DA_SYNC/ AD_SYNC
tHSY tSSY
DA_CK/ AD_CK
{
CKP=0
tHCK tLCK
CKP=1
tSDDA tHDDA tPCK
DA_DATA
tDADST ADHIZ=1 ADHIZ=0 tDAD ADHIZ=1 ADHIZ=0 tDAD ADHIZ=1 ADHIZ=0 tDAD tDADZ ADHIZ=1 ADHIZ=0
AD_DATA PCM format
AD_DATA All other formats
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Audio interface signals timing
Symbol Parameter Delay of AD_SYNC/ DA_SYNC edge from AD_CK/DA_CK active edge Setup time DA_DATA to DA_CK active edge Hold time DA_DATA from DA_CK active edge Delay of AD_DATA edge from AD_CK active edge Delay of the first AD_DATA AD_SYNC active edge comes edge from AD_SYNC after AD_CK active edge active edge Delay of AD_DATA high impedance from AD_SYNC inactive edge Setup time AD_SYNC/ DA_SYNC to AD_CK/ DA_CK active edge Hold time AD_SYNC/ DA_SYNC from AD_CK/ DA_CK active edge Period of AD_CK/DA_CK AD_CK/DA_CK pulse width high AD_CK/DA_CK pulse width low PCM format 10 Test Condition Min. Typ. Max. Unit
tDSY
Master Mode
10
ns
tSDDA tHDDA tDAD
10 10 30
ns ns ns
tDADST
30
ns
tDADZ
50
ns
tSSY
Slave Mode
20
ns
tHSY tPCK tHCK tLCK
Slave Mode Slave Mode Measured from VIH to VIH Measured from VIL to VIL
20 100 40 40
ns ns ns ns
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7 Timing Specifications
7
Timing Specifications
Unless otherwise specified, VCCIO = 1.71 V to 2.7 V,Tamb = -30C to 85C, max capacitive load 20 pF; typical characteristics are specified at VCCIO = 2.4 V, Tamb = 25 C; all signals are referenced to GND, see Note below figure for timing definitions. Figure 12. A.C. testing input-output waveform
INPUT OUTPUT 0.8*VCCIO 0.7*VCCIO 0.2*VCCIO 0.3*VCCIO 0.7*VCCIO 0.3*VCCIO
TEST POINTS
AC Testing: inputs are driven at 0.8*VCCIO for a logic `1' and 0.2*VCCIO for a logic `0'. Timing measurements are made at 0.7*VCCIO for a logic `1' and 0.3*VCCIO for a logic `0'.
Note:
A signal is valid if it is above VIH or below VIL and invalid if it is between VIL and VIH. For the purpose of this specification the following conditions apply (see Figure 12 above): a) All input signal are defined as: VIL = 0.2*VCCIO, VIH = 0.8*VCCIO, tR < 10ns, tF < 10ns. b) Delay times are measured from the inputs signal valid to the output signal valid. c) Setup times are measured from the data input valid to the clock input invalid. d) Hold times are measured from the clock signal valid to the data input invalid. All timing specifications subject to change.
Note:
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8
8.1
Operative Ranges
Absolute maximum ratings
Parameter Value -0.5 to 3.6 -0.5 to 5 -0.5 to 7 GND-0.5 to VCCA+0.5 500 100 350 50 GND-0.5 to VCCIO+0.5 -64 to 150 -30 to 85 Unit V V V V mW mA mA mA V C C
VCC or VCCIO to GND VCCA or VCCP to GND VCCLS to GND Voltage at Analog Inputs (VCCA 3.3V) Maximum Power delivered to the load from LSP/N Peak Current at HPR,HPL Current at VCCP, VCCLS, GNDP Current at any digital output Voltage at any digital input (VCCIO 2.7V); limited at 50mA Storage temperature range Operating temperature range(1)
1. in some operating conditions the temperature can be limited to 70 C. See Loudspeaker Driver description from Section 3.9 for details.
8.2
Symbol VCC VCCA VCCIO VCCP VCCLS VG
Operative supply voltage
Parameter Digital supply Analog supply Note: VCCA VCC Digital I/O supply Stereo power drivers supply Mono power driver supply Single supply voltage range VCC=VCCA=VCCIO=VCCP=VCCLS A24V=1 (bit 1 in CR0) A24V=0 (bit 1 in CR0) A24V=1 (bit 1 in CR0) D12V=0 (bit 0 in CR0) D12V=1 (bit 0 in CR0) Condition Min. 1.71 2.7 2.4 1.71 1.2 VCCA VCCA 2.4 Max. 2.7 3.3 2.7 VCC 1.8 3.3 5.5 2.7 Unit V V V V V V V V
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8.3
Power Dissipation
Unless otherwise specified, VCCP = VCCLS = VCCA = 2.7V to 3.3V, VCCIO = VCC = 1.71V to 2.7V, Tamb = -30C to 85C, all analog outputs not loaded; typical characteristics are specified at VCCIO = VCC = 1.8V, VCCP = VCCLS = VCCA = 2.7V, Tamb = 25C.
Symbol POFF PAD PDA PDAAD PAA Parameter Power Down Dissipation Stereo ADC power Stereo DAC power Stereo ADC+DAC power Stereo Analog Path power Test Condition No Master Clock AMCK=13MHz Min. Typ. 0.2 2.9 26.3 22.6 44.0 13.8 Max. Unit W W mW mW mW mW
8.4
Typical power dissipation
Tamb = 25C; Analog Supply: VCCP = VCCLS = VCCA = 2.7V; Digital Supply:VCCIO = VCC = 1.8V Full scale signal in every path, 20k load at analog outputs.
No Master Clock
N. Function CR0-CR2 setting CR0=0x00 CR1=0x00 CR2=0x00 CR0=0xD0 CR1=0x0C CR2=0xC0 CR0=0xD0; CR1=0x0C; CR2=0xC3 MICLO=1 MICSEL=2 MIXMIC=1 MICSEL=2 Other settings Supply Analog: Digital: Total: Analog: Digital: Total: Analog: Digital: Total: Current 0.02 A 0.20 A 4.3 mA 2.0 A 5.4 mA 2.0 A Power 0.05 W 0.36 W 0.41 W 11.6 mW 0.0 mW 11.6 mW 14.6 mW 0.0 mW 14.6 mW
1
Power Down
2
Stereo analog path (Mic-LO) Stereo analog path (Mic-Mixer-LO)
3
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Master clock AMCK = 13 MHz
N. Function CR0-CR2 setting CR0=0x00 CR1=0x00 CR2=0x00 CR0=0xE8 CR1=0xCC CR2=0x00 CR0=0xE8 CR1=0x30 CR2=0x33 CR0=0xE8 CR1=0x0C CR2=0xC0 CR0=0xE8 CR1=0xFC CR2=0x33 CR0=0xE8 CR1=0xFF CR2=0xF3 CR0=0xE8 CR1=0xA8 CR2=0x06 MICSEL=1 ADMIC=1 Other settings Supply Analog: Digital: Total: Analog: Digital: Total: Analog: Digital: Total: Analog: Digital: Total: Analog: Digital: Total: Analog: Digital: Total: VCCA,VCCP: VCCLS: Digital Total: Current 0.02 A 2.20 A 7.9 mA 2.8 mA 6.1 mA 3.8 mA 4.8 mA 0.8 mA 13.5 mA 5.8 mA 15.2 mA 5.8 mA Power 0.05 W 3.96 W 4.01 W 21.3 mW 5.0 mW 26.3 mW 16.5 mW 6.8 mW 23.3 mW 13.0 mW 1.4 mW 13.8 mW 36.5 mW 10.4 mW 46.9 mW 41.0 mW 10.4 mW 51.4 mW 18.4 mW 5.5 mW 4.5 mW 28.4 mW
4
Power Down
5
Stereo ADC
6
Stereo DAC
MIXDAC=1
7
Stereo analog path (Mic-LO) Stereo ADC Stereo DAC Stereo ADC Stereo DAC Stereo analog path
MICLO=1 MICSEL=2 MICSEL=2 ADMIC=1 MIXDAC=1 LINSEL=2; MICSEL=2 ADLIN=1;MIXDAC=1 MICLO=1 MICSEL=2; LSMODE=2 ADMIC=1 MIXDAC=1 ADVOICE=1 DAVOICE=1
8
9
10
Voice TX+RX
6.8 mA 1.3 mA 2.5 mA
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9 Electrical Characteristics
9
Electrical Characteristics
Unless otherwise specified, VCCIO = 1.71 V to 2.7 V, Tamb = -30C to 85C; typical characteristic are specified at VCCIO = 2.0 V, Tamb = 25C; all signals are referenced to GND.
9.1
Symbol VIL VIH VOL VOH IIL IIH
Digital interfaces
Parameter Input low voltage Test Condition All digital inputs DC AC DC 0.7*VCCIO AC 0.8*VCCIO IL = 10A IL = 2A IL = 10A VCCIO-0.1 IL = 2A VCCIO-0.4 -1 1 0.1 0.4 Min. Typ. Max. 0.3*VCCIO 0.2*VCCIO Unit V V V V V V V V A A
Input high voltage
All digital inputs, All digital outputs
Output low voltage
Output high voltage
All digital outputs
Input low current
Any digital input, GND < VIN < VIL Any digital input, VIH < VIN < VCCIO Tristate outputs
Input high current Output current in high impedance (Tristate)
-1
1
IOZ
-1
1
A
Note:
See Figure 12: A.C. testing input-output waveform on page 49.
9.2
Symbol CAMCK VAMCK
AMCK with sinusoidal input
Parameter Minimum External Capacitance AMCK sinusoidal voltage swing Test Condition AMCKSIN=1, see CR30 AMCKSIN=1, see CR30 Min. 100 0.5 VCCIO Typ. Max. Unit pF VPP
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9.3
Symbol IMIC RMIC RLIN RLHP CLHP
Analog interfaces
Parameter MIC input leakage MIC input resistance Line in input resistance Headphones (HP) drivers load resistance Headphones (HP) drivers load capacitance Loudspeaker (LS) differential driver load resistance Loudspeaker (LS) differential driver load capacitance Differential offset voltage at LSP, LSN Line out (OL) diff./singleended driver load resistance Line out (OL) diff./singleended driver load capacitance HPL, HPR to GNDP or VCMHP HPL, HPR to GNDP or VCMHP LSP to LSN 6.4 8 Test Condition GND< VMIC< VCCA Min. -100 30 30 14.4 16/32 50 50* 50 Typ. Max. +100 Unit A k k pF nF
RLLS
CLLS
LSP to LSN
50 50* -50 +50
pF nF mV
VOFFLS
RL = 50 OLP/ORP to OLN/ORN or OLP/ORP to GND (decoupled) OLP/ORP to OLN/ORN or OLP/ORP to GND
RLOL
1
k
CLOL
TBD
* with series resistor
9.4
Symbol HDVL HDVH HDH PBVL PBVH PBD
Headset plug-in and push-button detector
Parameter Plug-in detected Plug-in undetected Plug-in detector hysteresis Push-button pressed Push-button released Push-button de-bounce time Voltage at HDET Voltage at HDET 1 15 50 Test Condition Voltage at HDET Voltage at HDET VCCA-0.5 100 0.5 Min. Typ. Max. VCCA-1 Unit V V mV V V ms
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9 Electrical Characteristics
9.5
Symbol VMBIAS IMBIAS RMBIAS CMBIAS PSRMB4 PSRMB20
Microphone bias
Parameter MBIAS output voltage MBIAS output current MBIAS output load MBIAS output capacitance MBIAS power supply rejection f<4kHz f<20kHz 60 50 From MBIAS to ground 3.5 150 Test Condition Min. 1.95 Typ. 2.1 Max. 2.25 600 Unit V A k pF dB dB
9.6
Symbol PSRL20 PSRL200 PSRPH PSRPOS PSRPOD PSRAM PSRAL
Power supply rejection ratio
Parameter PSRR VCCLS Test Condition Each output(LSP, LSN) f<20kHz f<200kHz Headphones f<20kHz Line out single ended f<20kHz Line out differential f<20kHz Mic input f<20kHz Line In f<20kHz Min. Typ. 65 47 65 TBD TBD 50 TBD Max. Unit dB dB dB dB dB dB dB
PSRR VCCP
PSRR VCCA
9.7
Symbol VLSLIMH VLSLIML VLSLIMD
LS gain limiter
Parameter High voltage at VCCLS (VLSH=1) Low voltage at VCCLS (VLSH=0) VCCLS Hysteresis Test Condition VCCLS raising VCCLS falling Min. Typ. 4.2 4.0 200 Max. Unit V V mV
Note: See CR32 for VLSH definition. See Loudspeaker driver description in Section 3.9 for details.
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10
10.1
Analog Input/output Operative Ranges
Analog levels
Reference full scale analog levels
Symbol Parameter 0dBFS level 0dBFS level low voltage mode Test Condition 2.7V < VCCA < 3.3V Min. Typ. 12 4 10 3.18 Max. Unit dBVpp Vpp dBVpp Vpp
2.4V < VCCA < 2.7V
10.2
Microphone input levels
Absolute levels at pins connected to preamplifiers
Analog supply range: 2.7 V < VCCA < 3.3 V
Symbol Parameter Overload level, single ended Overload level,single ended, versus MIC gain Overload level, differential Test Condition Min. Typ. 707 2 -6 - (MIC_Gain) 1.41 4 0 - (MIC_Gain) Max. Unit mVRMS Vpp dBFS dBFS mVRMS Vpp dBFS dBFS
MIC gain = 0 to 6dB
MIC gain > 6dB
MIC gain = 0dB
Overload level, differential, MIC gain > 0dB versus MIC gain
Note: When 2.4 V < VCCA < 2.7 V, voltage values are reduced by 2dB.
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10.3
Line input levels
Absolute levels at pins connected to the line-in amplifiers
Analog supply range: 2.7 V < VCCA < 3.3 V
Symbol Parameter Overload level, single ended Overload level (single ended) versus line in gain Test Condition Line in gain from - 20dB to 6dB Min. Typ. 707 2 -6 - (Line_In_Gain) 1.41 4 0 - (Line_In_Gain) Max. Unit mVRMS Vpp dBFS dBFS mVRMS Vpp dBFS dBFS
Line in gain > 6dB
20dB to 0dB Overload level (differential) Line in gain from - Overload level (differential) Line in gain > 0dB versus line in gain
Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB
10.4
Line output levels
Absolute levels at OLP/OLN, ORP/ORN
Analog supply range: 2.7 V < VCCA < 3.3 V
Symbol Parameter Test Condition 0 dB gain Full scale digital input 0 dB Gain Full scale digital input Min. Typ. 707 2 -6 1.41 4 0 Max. Unit mVRMS Vpp dBFS mVRMS Vpp dBFS
Output level, single ended
Output level, differential
Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB
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10.5
Power output levels HP
Absolute levels at HPL - HPR
Analog supply range: 2.7 V < VCCA < 3.3 V
Symbol Parameter Test Condition -6dB gain Full scale digital input 16 load VCCP > 3.2 V Min. Typ. 707 2 -6 40 Max. Unit mVRMS Vpp dBFS mW
Output level
Max output power(1)
Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB
10.6
Power output levels LS
Absolute levels at LSP - LSN (Differential)
Analog supply range: 2.7 V < VCCA < 3.3 V
Symbol Parameter Test Condition 0 dB gain Full scale digital input 8 load VCCLS > 4V Min. Typ. 1.41 4 0 500 Max. Unit VRMS Vpp dBFS mW
Output level
Max output power(1)
1. In some operating conditions the maximum output power can be limited. See "Section 8.1: Absolute maximum ratings" and "Loudspeaker Driver" description from Section 3.9: Analog output drivers for details. Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB
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11 Stereo Audio ADC Specifications
11
Stereo Audio ADC Specifications
Typical measures at VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8 V; Tamb=25 C;13 MHz AMCK
Symbol ADN ADDRM ADDRLI Parameter Resolution 20Hz to 20kHz, A-weighted Measured at -60dBFS MIC input, 21dB gain Line-In, 0dB gain Max level at MIC input, 21dB gain A-weighted Unweighted (20 Hz to 20 kHz) A-weighted Input referred ADC noise Mic input 0dB Gain Mic input 21dB Gain Mic input 39dB Gain Line in input 0dB Gain Line in input 18dB Gain Max level at MIC input, 21dB gain Measurement bandwidth 20Hz to 20kHz, Fs= 48kHz. Combined digital and analog filter characteristics Combined digital and analog filter characteristics AD96K=0 Combined digital and analog filter characteristics AD96K=0 Combined digital and analog filter characteristics AD96K=0 Measurement bandwidth up to 3.45Fs. Combined digital and analog filter characteristics, AD96K=0 Audio filters, 96kHz FS Audio filters, 48kHz FS Audio filters, 8kHz FS 0.55Fs 0 37 3.3 1.9 30 7.5 0.001 0.003 V V V V V % Test Condition Min. Typ. Max. 20 Unit Bits
Dynamic range
87 89
91 93
dB dB
ADSNA ADSN
Signal to noise ratio
90 86
dB dB
ADTHD
Total harmonic distortion Deviation from linear phase
1
Deg
ADfPB
Passband Passband ripple
0.45Fs 0.2
kHz dB kHz
ADfSB
Stopband
Stopband Attenuation
60
dB
ADtgd
Group delay Interchannel isolation Interchannel gain mismatch Gain error
0.11 0.4 2.6 90 0.2 0.5
ms ms ms dB dB dB
Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB
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12
Stereo Audio DAC Specifications
Typical measures at VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25 C;13MHz AMCK
Symbol DAN Parameter Resolution 20Hz to 20kHz, A-weighted. Measured at -60dBFS Differential line out Single-ended line out HPL/HPR to GND or VCMHP LSP-LSN Test Condition Min. Typ. Max. 20 Unit Bits
DADR
Dynamic range
90
95 93 94 94
dB dB dB dB
DASNA DASN
2Vpp output HPL, HPR gain set to -6dB, 16 load Signal to noise ratio A-weighted Unweighted (20 Hz to 20 kHz) Total harmonic distortion Worst case load Total harmonic distortion Deviation from linear phase 2Vpp output HPL, HPR gain set to -6dB, 16 load 2Vpp output, HPL, HPR gain set to -6dB, 1k load Measurement bandwidth 20Hz to 20kHz, Fs= 48kHz. Combined digital and analog filter characteristics Combined digital and analog filter characteristics, DA96K=0 Combined digital and analog filter characteristics, DA96K=0 Combined digital and analog filter characteristics, DA96K=0 Measurement bandwidth up to 3.45Fs. Combined digital and analog filter characteristics, DA96K=0 0.55Fs 0
94 90 0.02 0.04
dB dB %
DATHDL
DATHD
0.004
%
1
Deg
DAfPB
Passband Passband ripple
0.45Fs 0.2
kHz dB kHz
DAfSB
Stopband
Stopband attenuation Transient suppression filter cut-off frequency Out of band noise
50
dB
TSF
15 Measurement bandwidth 20 kHz to 100 kHz. Zero input signal Audio filters, 96kHz FS Audio filters, 48kHz FS Audio filters, 8kHz FS 2Vpp output HPR, HPL unloaded HPR, HPL with 16 to VCMHP
23
Hz
-85 0.09 0.4 2.6 100 60
dBr ms ms ms dB dB
DAtgd
Group delay
Interchannel isolation
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13 AD to DA Mixing (Sidetone) Specifications
Symbol
Parameter Interchannel gain mismatch Gain error
Test Condition
Min.
Typ.
Max. 0.2 0.5
Unit dB dB ms ms
SUT
Startup time from power up
FS=48 kHz
Line out HPL/R out
1 10
Note: When 2.4 V < VCCA < 2.7 V, values are reduced by 2 dB
13
Symbol STDEL
AD to DA Mixing (Sidetone) Specifications
Parameter AD to DA mixing (sidetone) delay Test Condition Valid for audio and voice filters Min. Typ. 5 Max. 10 Unit s
Typical measures at VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25 C;13MHz AMCK
14
Stereo Analog-only Path Specifications
Measured at differential line-out, ENOSC=1, No master clock. Typical measures at VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25 C
Symbol Parameter Test Condition 20Hz to 20kHz, A-weighted. Measured at -60dBFS MIC input, 21dB gain Line-In, 0dB gain Max level at line-in input, 0dB gain, A-weighted Unweighted (20 Hz to 20 kHz) 1kHz @ 0dBFS MIC input, 21dB gain Line-in input, 0dB gain 0.003 0.004 0.01 0.02 % % Min. Typ. Max. Unit
AADRM AADRLI
Dynamic range
90 90
95 97 97 94
dB dB dB dB
AASNA AASN
Signal to noise ratio
AATHD
Total harmonic distortion
Note: When 2.4V61/69
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15
ADC (TX) & DAC (RX) Specifications With Voice Filters Selected
Typical measures at VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25 C;13MHz AMCK
Symbol Parameter Test Condition 300Hz to 3.4kHz; 1kHz @ -60dBFS TX Path, MIC input, 21dB gain RX Path, LS Output, 0dB gain Min. Typ. Max. Unit
TXDR RXDR TXSN RXSN THD
Dynamic range
86 83
89 86 88 86 <0.001 0.005 -30 -24 -6 0.5 0.5 0.0 -14 -35 -47 -20 -12 -2 0.5 0.5 0.0 -14 -50 -85
dB dB dB dB % % dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBr ms ms
300Hz to 3.4kHz; 1kHz @ 0dBFS Signal to noise ratio TX Path, MIC input, 21dB gain RX Path, LS Output, 0dB gain THD 1kHz @ 0dBFS TX Path, MIC input, 21dB gain RX Path, LS Output, 0dB gain f=60Hz f=100Hz f=200Hz f=300Hz f=400Hz-3000Hz f=3400Hz f=4000H f=4600Hzz f=8000Hz f=60Hz f=100Hz f=200Hz f=300Hz f=400Hz-3000Hz f=3400Hz f=4000Hz f=5000Hz Measurement bandwidth 4kHz to 100kHz. Zero input signal TX path RX path
TXG
TX gain mask
-1.5 -0.5 -1.5
RXG
RX gain mask
-1.5 -0.5 -1.5
RX out of band noise Group delay
0.32 0.28
Note: When 2.4V62/69
STw5095
16 Typical Performance Plots
16
Typical Performance Plots
Figure 14. Dynamic compressor transfer function
1 Output Amplitude [FS] 100 1k Frequency [Hz] 10k 0.75 0.5 0.25 0 -0.25 -0.5 -0.75 -1 -1 -0.75-0.5-0.25 0 0.25 0.5 0.75 1 Input Amplitude [FS] Audio signal transfer function when the Dynamic Compressor is active.
Figure 13. Bass treble control, de-emphasis filter
15 Gain @ Fs=44.1 kHz [dB] 10 5 0 -5 -10 -15
Bass and treble gains are independently selectable in any combination. The de-emphasis filter (thick line, alternative to treble control) compensates for pre-emphasis used on some audio CDs. Gain error < 0.1dB. Filter characteristics at Fs=44.1kHz are plotted
Figure 15. ADC audio path measured filter response
0 -10 -20 Gain [dB] -30 -40 -50 -60 -70 -80 100 1k 10k Frequency [Hz] 100k
Figure 16. ADC in band audio path measured filter response
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
Gain [dB]
0
5k
10k 15k Frequency [Hz]
20k
48 kHz sample rate. Full ADC path Frequency response up to 100 kHz.
48 kHz Sample Rate. In band Frequency response
Figure 17. DAC digital audio filter characteristics
0 -20 Gain [dB] -40 -60 -80 100 1k 10k Frequency [Hz] 100k
Figure 18. DAC in band digital audio filter characteristics
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 5k 10k 15k 20k Frequency [Hz] 48 kHz Sample Rate In band Frequency response
DA96K=0; 48 kHz Sample Rate Frequency response up to 166kHz (3.45 Fs @ 48kHz sampling rate)
Gain [dB]
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16 Typical Performance Plots
STw5095
Figure 20. ADC 96 kHz audio in-band measured filter response
1
Figure 19. ADC 96 kHz audio path measured filter response
0 -10 Gain [dB] -30 -40 -50 -60 -70 -80
0 Gain [dB] -1 -2 -3 -4 -5 10 100 1k Frequency [Hz] 10k 100k 0 5k 10k 15k 20k 25k 30k 35k 40k 45k Frequency [Hz]
-20
The plot is extended down to 5 Hz to show the high pass filter implemented in the ADC 96 kHz sample rate, 96 kHz audio filter selected signal from Mic input
96 kHz sample rate, 96 kHz audio filter selected signal from Mic input.
Figure 21. ADC voice TX path measured filter response
0 -10 Gain [dB] -20 -30 -40 -50 -60 -70 100 1k Frequency [Hz] 10k
Figure 22. ADC voice TX path measured inband filter response
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
Gain [dB]
500
1k
1500 2k 2500 Frequency [Hz]
3k
3500
4k
8 kHz Sample rate, tx voice filter selected. Signal from Mic input
8 kHz sample rate, tx voice filter selected signal from Mic input.
Figure 23. DAC voice (RX) digital filter characteristics
0 -10 Gain [dB] -20 -30 -40 -50 -60 -70 100 1k Frequency [Hz] 10k
Figure 24. DAC voice (RX) in-band digital filter characteristics
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
Gain [dB]
500
1k
1500 2k 2500 Frequency [Hz]
3k
3500
4k
8 kHz sample rate, rx voice filter
8 kHz sample rate, rx voice filter
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STw5095
Figure 25. ADC path FFT
0 Amplitude [dBFS] -20 S/N [dB] -40 -60 -80 -100 -120 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k Frequency [Hz]
16 Typical Performance Plots
Figure 26. ADC S/N versus input-level
100 90 80 70 60 50 40 30 20 -60 -50 -40 -30 -20 Input Level [dBFS] -10 0
12 MHz master clock. Differential input at Mic preamplifier, 21 dB gain. 48 kHz sampling rate. Both channels active
12 MHz master clock Differential input at Line-In Amplifier, 0 dB Gain. 48 kHz Sampling Rate A-Weighted, Both channels active
Figure 27. DAC path FFT
0 Amplitude [dBFS] -20 -40 -60 -80
Figure 28. DAC S/N versus input-level
100 90 80 S/N [dB] 70 60 50 40 30 20
-100 -120 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k Frequency [Hz]
-60
-50
-40 -30 -20 Input Level [dBFS]
-10
0
12 MHz master clock. 48 kHz sampling rate Differential output at line-out, 1k load. Both channels active
12 MHz master clock. 48 kHz Sampling Rate Differential output at Line-Out, 1k load.
A-Weighted, Both channels active
Figure 29. Analog path FFT
0 Amplitude [dBFS] -20
Figure 30. Analog path S/N versus input-level
100 90 80 S/N [dB] 70 60 50 40 30
-40 -60 -80 -100 -120 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k Frequency [Hz]
20
-60
-50
-40 -30 -20 Input Level [dBFS]
-10
0
Differential input at Mic Preamplifier, 21 dB Gain. Direct Mic to Line-Out connection (MICLO=1) Differential output at Line-Out, 20k load. Both channels active
Differential input at Line-In Amplifier, 0 dB Gain. Line-In to DA-Mixer to Line-Out connection. Differential output at Line-Out, 20k load. A-weighted, both channels active
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17 Application Schematics
STw5095
17
Application Schematics
Figure 31. STw5095 application schematics
MBIAS 2.7k 750 100nF MIC1LP 10F Electret 100nF MIC1LN 750 VCCIO 2.7k 2.7k 750 100nF MIC1RP 10F Electret 100nF MIC1RN 750 2.7k IRQ HDET
See application example in Section 3.16 on page 19
Needed if IRQ is not set to CMOS
200nF
OCKAD CAPMIC OCKDA
MasterClocks for Other Digital Device or for Digital Audio Data Source
Line IN
L R
100nF 100nF
LINEINL LINEINR AUX1L AUX1R AUX2LP AUX2RP AUX2LN AUX2RN AUX3L AUX3R
Melody IN
0.47F
STw5095
AD_SYNC AD_DATA AD_CK
AD_Fs [8kHz-48kHz] A/D [88kHz-96kHz] Audio Data AD_Data AD_Data Clock
0.47F Voice IN 0.47F
Interface
FM IN 16/ 32 Typ 40mW Max.
L R
0.47F 0.47F
To have a single bidirectional interface connect: AD_SYNC to DA_SYNC AD_CK to DA_CK
Differential Connector
10F
CAPLINEIN
DA_Fs
DA_SYNC HPR VCMHP VCMHPS HPL 10F Standard HP Connection
As Close as possible to the pins
[8kHz-48kHz] [88kHz-96kHz]
DA_Data DA_Data
DA_DATA DA_CK
SENSE
Clock 100pF
D/A Audio Data Interface
CAPLS AMCK LSP
System Clock
[4MHz-32MHz]
8 typ 500mW Max.
As Close as possible to the pins
SENSE
LSPS LSNS LSN OLP SDA/SDIN SCLK AS/CSB OLN Data
SENSE
I2C compat. Bus
Clock L
Line OUT ORP R ORN GNDCM VCCLS GND VCC
CMOD
I2C compat. Bus selected
Leave the negative pins unconnected when used in Single-Ended Configuration
100nF
VCCA VCCP
100nF
100nF
VCCD
VCCIO VCCIO 100nF
GNDA
1F
10F
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GNDP
VCCA
VCCP
STw5095
18 Package Outline
18
Package Outline
Dimensions [mm] Ref. A (1) A1 A2 b D D1 E E1 e f ddd 0.450 0.600 4.850 0.250 4.850 Min. 1.010 0.150 0.820 0.300 5.000 3.500 5.000 3.500 0.500 0.750 0.550 0.900 0.080 TFBGA 5x5x1.20 64 F8x8 0.50 Thin Profile Fine Pitch Ball Grid Array 5.150 0.350 5.150 Typ. Max. 1.200 (2) OUTLINE AND MECHANICAL DATA
1. The total profile height is measured from the seating plane to the top of the component. 2. Max mounted height is 1.12mm.Based on a 0.28mm ball pad diameter. Solder paste is 0.15mm thickness and 0.28mm diameter.
Figure 32. Package mechanical data
D D1 e f A2 SEATING PLANE C
H G F E D C B A 12345678
f E1 e
E
A1 A1 CORNER INDEX AREA Ob (64 BALLS) A ddd C
See Note 1
BOTTOM VIEW
Note: 1 The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional.
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19 Revision history
STw5095
19
Revision history
Date 8-Nov-2005 Revision 1.0 Initial release Changes
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STw5095
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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