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ST72521M/R/AR
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
DATA BRIEFING
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Memories - 32K to 60K dual voltage High Density Flash (HDFlash) or ROM with read-out protection capability. In-Application Programming and In-Circuit Programming for HDFlash devices - 1K to 2K RAM Cloc anced reset system - Enhanced low voltage supervisor (LVD) for main supply and auxiliary voltage detector (AVD) with interrupt capability - Clock sources: crystal/ceramic resonator oscillators, internal or external RC oscillator, clock security system and bypass for external clock - PLL for 2x frequency multiplication - Four power saving modes: Halt, Active-Halt, Wait and Slow Interrupt Management - Nested interrupt controller - 14 interrupt vectors plus TRAP and RESET - TLI dedicated top level interrupt pin - 15 external interrupt lines (on 4 vectors) Up to 64 I/O Ports - 48 multifunctional bidirectional I/O lines - 34 alternate function lines - 16 high sink outputs 5 Timers - Main Clock Controller with: Real time base, Beep and Clock-out capabilities - Configurable watchdog timer - Two 16-bit timers with: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes - 8-bit PWM Auto-Reload timer with: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
Features ST72(F)521(M/R/AR)9
TQFP64 14 x 14 TQFP80 14 x 14 TQFP64 10 x 10
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4 Communications Interfaces - SPI synchronous serial interface - SCI asynchronous serial interface (LIN compatible) - I2C multimaster interface - CAN interface (2.0B Passive) Analog peripheral - 10-bit ADC with 16 input pins Instruction Set - 8-bit Data Manipulation - 63 Basic Instructions - 17 main Addressing Modes - 8 x 8 Unsigned Multiply Instruction - True Bit Manipulation Development Tools - Full hardware/software development package - In-Circuit Testing capability
ST72(F)521(R/AR)6
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Device Summary
ST72521(M/R/AR)7
Program memory - bytes 60K 48K 32K RAM (stack) - bytes 2048 (256) 1536 (256) 1024 (256) Operating Voltage 3.8V to 5.5V Temp. Range (ROM) 0C to 70C / -10C to +85 C / -40C to +85 C / -40C to +105C / -40C to +125C Temp. Range (Flash) -40C to +85 C / -40C to +125C N/A -40C to +125 C Package TQFP80 14x14 (M), TQFP64 14x14 (R), TQFP64 10x10 (AR) TQFP64 14x14 (R), TQFP64 10x10 (AR)
Rev. 1.5 April 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
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ST72521M/R/AR
1 INTRODUCTION
The ST72521(A)R and ST72521M devices are members of the ST7 microcontroller family designed for mid-range applications with a CAN bus interface (Controller Area Network). All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set and are available with FLASH or ROM program memory.
Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or stand-by state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
Figure 1. Device Block Diagram
8-BIT CORE ALU RESET VPP TLI VSS VDD EVD OSC1 OSC2 CONTROL RAM (1024-2048 Bytes) LVD AVD OSC I2C PORT A PORT B PB7:0 (8-bits) PWM ART PORT C TIMER B CAN SPI SCI PORT D PD7:0 (8-bits) 10-BIT ADC VAREF VSSA
1 On
PROGRAM MEMORY (32K - 60K Bytes)
WATCHDOG
ADDRESS AND DATA BUS
MCC/RTC/BEEP
PA7:0 (8-bits)
PORT F PF7:0 (8-bits) TIMER A BEEP PORT E PE7:0 (8-bits)
PC7:0 (8-bits)
PORT G1 PORT H1
PG7:0 (8-bits) PH7:0 (8-bits)
some devices only, see Device Summary on page 1
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2 PIN DESCRIPTION
Figure 2. 80-Pin TQFP 14x14 Package Pinout
PE3 / CANRX PE2 / CANTX PE1 / RDI PE0 / TDO VDD_2
PA7 (HS) / SCLI PA6 (HS) / SDAI PA5 (HS)
VPP / ICCSEL
OSC2 VSS_2
OSC1
PH7 PH6 PH5
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PE4 PE5 PE6 PE7 PB0 PB1 PB2 PB3 PG0 PG1 PG2 PG3 ARTCLK / (HS) PB4 ARTIC1 / PB5 ARTIC2 / PB6 PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 (HS) (HS) (HS) (HS) PWM3 / PWM2 / PWM1 / PWM0 / 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PA4 (HS)
PH4
TLI EVD RESET
ei0 ei2
VSS_1 VDD_1 PA3 (HS) PA2 PA1 PA0 PC7 / SS / AIN15 PC6 / SCK /ICCCLK PH3 PH2 PH1 PH0 PC5 / MOSI / AIN14 PC4 / MISO / ICCDATA PC3 (HS) /ICAP1_B PC2(HS) / ICAP2_B PC1 / OCMP1_B / AIN13 PC0 / OCMP2_B /AIN12 VSS_0 VDD_0
ei3
ei1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PG6 PG7 AIN4/PD4 AIN5 / PD5 AIN6 / PD6 AIN7 / PD7 VAREF VSSA VDD3 VSS3 PG4 PG5 MCO /AIN8 / PF0 BEEP / (HS) PF1 (HS) PF2 OCMP2_A / AIN9 /PF3 OCMP1_A/AIN10 /PF4 ICAP2_A/ AIN11 /PF5 ICAP1_A / (HS) / PF6 EXTCLK_A / (HS) PF7
(HS) 20mA high sink capability eix associated external interrupt vector
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PIN DESCRIPTION (Cont'd) Figure 3. 64-Pin TQFP 14x14 and 10x10 Package Pinout
PA7 (HS) / SCLI PA6 (HS) / SDAI
PE3 / CANRX PE2 / CANTX
PE0 / TDO VDD_2
PE1 / RDI
VPP / ICCSEL
PA5 (HS)
(HS) PE4 (HS) PE5 (HS) PE6 (HS) PE7 PWM3 / PB0 PWM2 / PB1 PWM1 / PB2 PWM0 /PB3 ARTCLK /(HS) PB4 ARTIC1 / PB5 ARTIC2 / PB6 PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 ei0 44 5 43 6 ei2 42 7 41 8 1 2 3 4 40 39 ei3 38 37 36 13 35 14 ei1 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 9 10 11 12 AIN7 / PD7 VAREF AIN4 / PD4 AIN5 / PD5 AIN6 / PD6 VDD_3 VSS_3 VSSA BEEP / (HS) PF1 (HS) PF2 OCMP2_A / AIN9 / PF3 MCO / AIN8 / PF0 OCMP1_A / AIN10 / PF4 ICAP2_A / AIN11 / PF5 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7
PA4 (HS)
OSC2 VSS_2
OSC1
EVD RESET
TLI
VSS_1 VDD_1 PA3 (HS) PA2 PA1 PA0 PC7 / SS / AIN15 PC6 / SCK / ICCCLK PC5 / MOSI / AIN14 PC4 / MISO / ICCDATA PC3 PC2 PC1 PC0 (HS) / ICAP1_B (HS) / ICAP2_B / OCMP1_B / AIN13 / OCMP2_B / AIN12
VSS_0 VDD_0
(HS) 20mA high sink capability eix associated external interrupt vector
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PIN DESCRIPTION (Cont'd) Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3VDD/0.7VDD CT= CMOS 0.3VDD/0.7VDD with input trigger TT= TTL 0.8V / 2V with Schmitt trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: - Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog - Output: OD = open drain 2), PP = push-pull The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Table 1. Device Pin Description
Pin n TQFP80 TQFP64 Type Pin Name Level Output Input Port Input float wpu ana int Main Output function (after reset) OD X X X X
ei2 ei2 ei2
Alternate function
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PE4 (HS) PE5 (HS) PE6 (HS) PE7 (HS) PB0/PWM3 PB1/PWM2 PB2/PWM1 PB3/PWM0 PG0 PG1 PG2 PG3 PB4 (HS)/ARTCLK PB5/ARTIC1 PB6/ARTIC2 PB7 PD0 /AIN0 PD1/AIN1 PD2/AIN2 PD3/AIN3 PG6 PG7 PD4/AIN4 PD5/AIN5 PD6/AIN6 PD7/AIN7
I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O TT I/O TT I/O TT I/O TT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O TT I/O TT I/O CT I/O CT I/O CT I/O CT
HS HS HS HS
X X X X X X X X X X X X
X X X X
PP X X X X X X X X X X X X X X X X X X X X X X X X X X
Port E4 Port E5 Port E6 Port E7 Port B0 Port B1 Port B2 Port B3 Port G0 Port G1 Port G2 Port G3 Port B4 Port B5 Port B6 Port B7 Port D0 Port D1 Port D2 Port D3 Port G6 Port G7 Port D4 Port D5 Port D6 Port D7 ADC Analog Input 4 ADC Analog Input 5 ADC Analog Input 6 ADC Analog Input 7 ADC Analog Input 0 ADC Analog Input 1 ADC Analog Input 2 ADC Analog Input 3 PWM-ART External Clock PWM-ART Input Capture 1 PWM-ART Input Capture 2 PWM Output 3 PWM Output 2 PWM Output 1 PWM Output 0
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
ei2 X X X X ei3 ei3 ei3 ei3 X X X X X X X X X X
HS
X X X X X X X X X X X X X X
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Pin n TQFP80 TQFP64 Type Pin Name
Level Output Input
Port Input float wpu ana int
OD
27 28 29 30 31 32 33 34 35 36
21 22 23 24 25 26 27 28
VAREF VSSA VDD_3 VSS_3 PG4 PG5 PF0/MCO/AIN8 PF1 (HS)/BEEP PF2 (HS) PF3/OCMP2_A/AIN9
I S S S I/O TT I/O TT I/O CT I/O CT I/O CT I/O CT HS HS X X X X X X X X X ei1 ei1 ei1 X X X X X X X X X X X X
PP
Main function Output (after reset)
Alternate function
Analog Reference Voltage for ADC Analog Ground Voltage Digital Main Supply Voltage Digital Ground Voltage Port G4 Port G5 Port F0 Port F1 Port F2 Port F3 Timer A OutADC Analog put Compare Input 9 2 Timer A OutADC Analog put Compare Input 10 1 Timer A Input ADC Analog Capture 2 Input 11 Timer A Input Capture 1 Timer A External Clock Source Main clock out (fOSC/2) ADC Analog Input 8
Beep signal output
37
29
PF4/OCMP1_A/AIN10
I/O CT I/O CT I/O CT I/O CT S S I/O CT HS HS
X
X
X
X
Port F4
38 39 40 41 42 43
30 31 32 33 34 35
PF5/ICAP2_A/AIN11 PF6 (HS)/ICAP1_A PF7 (HS)/EXTCLK_A VDD_0 VSS_0 PC0/OCMP2_B/AIN12
X X X
X X X
X X X
X X X
Port F5 Port F6 Port F7
Digital Main Supply Voltage Digital Ground Voltage X X X X Port C0 Timer B OutADC Analog put Compare Input 12 2 Timer B OutADC Analog put Compare Input 13 1 Timer B Input Capture 2 Timer B Input Capture 1 SPI Master In ICC Data In/ Slave Out put Data SPI Master ADC Analog Out / Slave In Input 14 Data
44 45 46 47
36 37 38 39
PC1/OCMP1_B/AIN13 PC2 (HS)/ICAP2_B PC3 (HS)/ICAP1_B PC4/MISO/ICCDATA
I/O CT I/O CT I/O CT I/O CT HS HS
X X X X
X X X X
X X X X
X X X X
Port C1 Port C2 Port C3 Port C4
48 49 50 51 52 53
40 41
PC5/MOSI/AIN14 PH0 PH1 PH2 PH3 PC6/SCK/ICCCLK
I/O CT I/O TT I/O TT I/O TT I/O TT I/O CT
X X X X X X
X X X X X X
X X X X X X
X X X X X X
Port C5 Port H0 Port H1 Port H2 Port H3 Port C6
SPI Serial Clock
ICC Clock Output
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ST72521M/R/AR
Pin n TQFP80 TQFP64 Type Pin Name
Level Output Input
Port Input float wpu ana int
OD
PP
Main function Output (after reset)
Alternate function
54 55 56 57 58 59 60 61 62 63 64
42 43 44 45 46 47 48 49 50 51 52
PC7/SS/AIN15 PA0 PA1 PA2 PA3 (HS) VDD_1 VSS_1 PA4 (HS) PA5 (HS) PA6 (HS)/SDAI PA7 (HS)/SCLI
I/O CT I/O CT I/O CT I/O CT I/O CT S S I/O CT I/O CT I/O CT I/O CT I HS HS HS HS HS
X X X X X
X ei0 ei0 ei0 ei0
X X X X X
X X X X X
Port C7 Port A0 Port A1 Port A2 Port A3
SPI Slave ADC Analog Select (active Input 15 low)
Digital Main Supply Voltage Digital Ground Voltage X X X X X X X X T T X X Port A4 Port A5 Port A6 Port A7 I2C Data 1) I2C Clock 1)
65
53
VPP/ ICCSEL RESET EVD TLI PH4 PH5 PH6 PH7 VSS_2 OSC23) OSC13) VDD_2 PE0/TDO PE1/RDI PE2/CANTX PE3/CANRX
Must be tied low. In flash programming mode, this pin acts as the programming voltage input VPP. High voltage must not be applied to ROM devices Top priority non maskable interrupt. External voltage detector X X X X X X X X X X X X X X X X X X Top level interrupt input pin Port H4 Port H5 Port H6 Port H7 Digital Ground Voltage Resonator oscillator inverter output or capacitor input for RC oscillator External clock input or Resonator oscillator inverter input or resistor input for RC oscillator Digital Main Supply Voltage X X X X X X X X X X X X X Port E0 Port E1 Port E2 Port E3 SCI Transmit Data Out SCI Receive Data In CAN Transmit Data Output CAN Receive Data Input
66 67 68 69 70 71 72 73 74
54 55 56 57 58
I/O CT I CT
I/O TT I/O TT I/O TT I/O TT S I/O
75 76 77 78 79 80
59 60 61 62 63 64
I S I/O CT I/O CT I/O CT I/O CT
Notes: 1. In the interrupt input column, "eiX" defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. In the open drain output column, "T" defines a true open drain I/O (P-Buffer and protection diode to VDD
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ST72521M/R/AR
are not implemented). 3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, an RC oscillator, or an external source to the on-chip oscillator; 4. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.
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3 PACKAGE CHARACTERISTICS
3.1 PACKAGE MECHANICAL DATA Figure 4. 80-Pin Thin Quad Flat Package
Dim.
D D1 A1 A A2
mm Min 0.05 1.35 0.22 0.09 16.00 14.00 16.00 14.00 0.65 0 0.45 3.5 0.60 1.00 80 7 0 1.40 0.32 Typ Max 1.60 0.15 0.002 Min
inches Typ Max 0.063 0.006
A A1 A2 b C D D1 E E1 e L L1 N
1.45 0.053 0.055 0.057 0.38 0.009 0.013 0.015 0.20 0.004 0.630 0.551 0.630 0.551 0.026 3.5 0.039 7 0.75 0.018 0.024 0.030 0.008
b
e E1 E
L1 L h
c
Number of Pins
Figure 5. 64-Pin Thin Quad Flat Package
D D1 A1 A A2
Dim. A A1 A2
mm Min 0.05 1.35 0.30 0.09 16.00 14.00 16.00 14.00 0.80 0 0.45 3.5 0.60 1.00 64 7 0 1.40 0.37 Typ Max 1.60 0.15 0.002 Min
inches Typ Max 0.063 0.006
1.45 0.053 0.055 0.057 0.45 0.012 0.015 0.018 0.20 0.004 0.630 0.551 0.630 0.551 0.031 3.5 0.039 7 0.75 0.018 0.024 0.030 0.008
b
b c D
e E1 E
D1 E E1 e L
L L1 c h
L1 N
Number of Pins
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ST72521M/R/AR
PACKAGE MECHANICAL DATA (Cont'd) Figure 6. 64-Pin Thin Quad Flat Package
Dim.
D D1 A1 A A2
mm Min 0.05 1.35 0.17 0.09 12.00 10.00 12.00 10.00 0.50 0 0.45 3.5 0.60 1.00 64 7 0 1.40 0.22 Typ Max 1.60 0.15 0.002 Min
inches Typ Max 0.063 0.006
A A1 A2 b
1.45 0.053 0.055 0.057 0.27 0.007 0.009 0.011 0.20 0.004 0.472 0.394 0.472 0.394 0.020 3.5 0.039 7 0.75 0.018 0.024 0.030 0.008
b
c D D1
E1
E e
E E1 e
c
L L1 N
L1 h L
Number of Pins
Figure 7. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil Width
mm Min 0.51 3.05 0.38 0.89 0.23 15.24 1.78 15.24 18.54 1.52 0.000 2.54 3.30 Number of Pins N 42 3.81 0.46 1.02 0.25 Typ Max 5.08 0.020 4.57 0.120 0.150 0.180 0.56 0.015 0.018 0.022 1.14 0.035 0.040 0.045 0.38 0.009 0.010 0.015 16.00 0.600 0.070 0.600 0.730 0.060 0.630 Min inches Typ Max 0.200
Dim.
E
A
A2 A
A1 A2
c E1 eA eB E
A1 b2 b D e
L
b b2 c D
0.015 GAGE PLANE
36.58 36.83 37.08 1.440 1.450 1.460 12.70 13.72 14.48 0.500 0.540 0.570
E E1 e eA eB eC L
eC eB
3.56 0.100 0.130 0.140
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Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2 C Patent. Rights to use these components in an I2 C system is granted provided that the system conforms to the I2 C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http:/ /www.st.com
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