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SSTV16857 * SSTVN16857 14-Bit Register with SSTL-2 Compatible I/O and Reset
September 2000 Revised June 2005
SSTV16857 * SSTVN16857 14-Bit Register with SSTL-2 Compatible I/O and Reset
General Description
The SSTV16857 is a 14-bit register designed for use with 184 and 232 pin PC1600, 2100, and 2700 DDR DIMM applications. The SSTVN16857 is a 14-bit register designed for use with 184 and 232 pin PC3200 DDR DIMM applications. These devices have a differential input clock, SSTL-2 compatible data inputs and a LVCMOS compatible RESET input. These devices have been designed for compliance with the JEDEC DDR module and register specifications. The devices are fabricated on an advanced submicron CMOS process and are designed to operate at power supplies of less than 3.6V's.
Features
s Compliant with DDR-I registered module specifications s Operates at 2.5V r 0.2V VDD s SSTL-2 compatible input and output structure s Differential SSTL-2 compatible clock inputs s Low power mode when device is reset s Industry standard 48 pin TSSOP package
Ordering Code:
Order Number SSTV16857MTD SSTVN16857MTD (Preliminary) Package Number MTD48 MTD48 Package Description 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Name Q1-Q14 D1-D14 RESET CK CK VREF VDDQ VDD Description SSTL-2 Compatible Output SSTL-2 Compatible Inputs Asynchronous LVCMOS Reset Input Positive Master Clock Input Negative Master Clock Input Voltage Reference Pin for SSTL Level Inputs Power Supply Voltage for Output Signals Power Supply Voltage for Inputs
Truth Table
RESET L H H H H Dn X or Floating L H X X CK X or Floating CK X or Floating Qn L L H Qn Qn
n n
L H
p p
H L
L Logic LOW H Logic HIGH X Don't Care, but not floating unless noted n LOW-to-HIGH Clock Transition p HIGH-to-LOW Clock Transition
(c) 2005 Fairchild Semiconductor Corporation
DS500387
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SSTV16857 * SSTVN16857
Functional Description
The SSTV16857 and SSTVN16587 are 14-bit registers with SSTL-2 compatible inputs and outputs. Input data is captured by the register on the positive edge crossing of the differential clock pair. When the LV-CMOS RESET signal is asserted LOW, all outputs and internal registers are asynchronously placed into the LOW logic state. In addition, the clock and data differential comparators are disabled for power savings. Output glitches are prevented by disabling the internal registers more quickly than the input comparators. When RESET is removed, the system designer must insure the clock and data inputs to the device are stable during the rising transition of the RESET signal. The SSTL-2 data inputs transition based on the value of VREF. VREF is a stable system reference used for setting the trip point of the input buffers of the SSTV16857/ SSTVN16857 and other SSTL-2 compatible devices. The RESET signal is a standard CMOS compatible input and is not referenced to the VREF signal.
Logic Diagram
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SSTV16857 * SSTVN16857
Absolute Maximum Ratings(Note 1)
Supply Voltage (VDDQ) Supply Voltage (VDD) Reference Voltage (VREF) Input Voltage (VI) Output Voltage (VO) Outputs Active (Note 2) DC Input Diode Current (IIK) VI 0V VI ! VDD DC Output Diode Current (IOK) VO 0V VO ! VDD DC Output Source/Sink Current (IOH/IOL) DC VDD or Ground Current per Supply Pin (IDD or Ground) Storage Temperature Range (Tstg)
0.5V to 3.6V 0.5V to 3.6V 0.5V to 3.6V 0.5V to VDD 0.5V 0.5V to VDDQ 0.5V 50 mA 50 mA 50 mA 50 mA r50 mA r100 mA 65qC to 150qC
Recommended Operating Conditions (Note 3)
Power Supply (VDDQ) SSTV16857 SSTVN16857 Power Supply (VDD) Operating Range Reference Supply (VREF SSTV16857 SSTVN16857 Termination Voltage (VTT) Input Voltage Output Voltage (VO) Output in Active States Output Current IOH/IOL VDD VDD 2.3V to 2.7V 2.5V to 2.7V SSTV16857 SSTVN16857 0V to VDDQ VDDQ/2) 1.15 to 1.35 1.25 to 1.35 VREF r 40 mV 0V to VDD VDDQ to 2.7V 2.3V to 2.7V 2.5V to 2.7V
Free Air Operating Temperature (TA)
r20 mA r20 mA 0qC to 70qC
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the "Electrical Characteristics" table are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed. Note 3: The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is asserted LOW.
DC Electrical Characteristics (SSTV16857) (2.3V d VDD d 2.7V)
Symbol VIKL VIKH VIH-AC VIL-AC VIH-DC VIL-DC VIH VIL VICR VI(PP) VOH VOL II IDD Parameter Input LOW Clamp Voltage Input HIGH Clamp Voltage AC HIGH Level Input Voltage AC LOW Level Input Voltage DC HIGH Level Input Voltage DC LOW Level Input Voltage HIGH Level Input Voltage LOW Level Input Voltage Common Mode Input Voltage Range Peak to Peak Input Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Leakage Current Static Standby Static Operating II II Conditions VDD (V) 2.3 2.3 VREF310mV VREF310mV VREF150mV VREF150mV 1.7 0.7 0.97 360 2.3 to 2.7 2.3 2.3 to 2.7 2.3 2.7 0 0 2.7 25 mA VDD 0.2 1.95 0.2 0.35 1.53 Min Max Units V V V V V V V V V mV V V
18 mA 18 mA
1.2
3.5
Data Inputs Data Inputs Data Inputs Data Inputs RESET RESET CLK, CLK CLK, CLK IOH IOH IOL IOL VI
100 PA 16 mA
100 PA 16 mA VDD or GND GND, IO VDD, IO
r5.0
10
PA PA
RESET RESET VI
VIH(AC) or VIL(AC)
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SSTV16857 * SSTVN16857
DC Electrical Characteristics (SSTV16857)
Symbol IDDD Parameter Dynamic Operating Current Clock Only RESET VI Conditions VDD, IO 0
(Continued)
VDD (V)
Min
Max
Units
VIH(AC) or VIL(AC)
90
PA/MHz
CK, CK Duty Cycle 50% Dynamic Operating Current per Data Input RESET VI VDD, IO 0 2.7 15
VIH(AC) or VIL(AC)
CK, CK Duty Cycle 50% Data Input ROH ROL RO' Output HIGH On Resistance Output LOW On Resistance | ROH - ROL | IOH IOL IO 1/2 Clock 2.3 to 2.7 2.3 to 2.7 25qC 2.5 7 7 Rate 50% Duty Cycle
PA/MHz
20 mA
20 mA 20 mA, TA
20 20 4
: : :
DC Electrical Characteristics (SSTVN16857) (2.5V d VDD d 2.7V)
Symbol VIKL VIKH VIH-AC VIL-AC VIH-DC VIL-DC VIH VIL VICR VI(PP) VOH VOL II IDD Parameter Input LOW Clamp Voltage Input HIGH Clamp Voltage AC HIGH Level Input Voltage AC LOW Level Input Voltage DC HIGH Level Input Voltage DC LOW Level Input Voltage HIGH Level Input Voltage LOW Level Input Voltage Common Mode Input Voltage Range Peak to Peak Input Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Leakage Current Static Standby Static Operating II II Conditions VDD (V) 2.5 2.5 VREF310mV VREF310mV VREF150mV VREF150mV 1.7 0.7 0.97 360 2.5 to 2.7 2.5 2.5 to 2.7 2.5 2.7 0 0 2.7 25 mA VDD 0.2 1.95 0.2 0.35 1.53 Min Max Units V V V V V V V V V mV V V
18 mA 18 mA
1.2
3.5
Data Inputs Data Inputs Data Inputs Data Inputs RESET RESET CLK, CLK CLK, CLK IOH IOH IOL IOL VI
100 PA 16 mA
100 PA 16 mA VDD or GND GND, IO VDD, IO
r5.0
10
PA PA
RESET RESET VI
VIH(AC) or VIL(AC) VDD, IO 0
IDDD
Dynamic Operating Current Clock Only
RESET VI
VIH(AC) or VIL(AC)
90
PA/MHz
CK, CK Duty Cycle 50% Dynamic Operating Current per Data Input RESET VI VDD, IO 0 2.7 15
VIH(AC) or VIL(AC)
CK, CK Duty Cycle 50% Data Input ROH ROL RO' Output HIGH On Resistance Output LOW On Resistance | ROH - ROL | IOH IOL IO 1/2 Clock 2.5 to 2.7 2.5 to 2.7 25qC 2.5 7 7 Rate 50% Duty Cycle
PA/MHz
20 mA
20 mA 20 mA, TA
20 20 4
: : :
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SSTV16857 * SSTVN16857
AC Electrical Characteristics (SSTV16857) (Note 4)
TA Symbol Parameter VDD 0qC to 70qC, CL 30 pF, RL 50: Units 2.5V r 0.2V; VDDQ Min fMAX tW tACT (Note 5) tINACT (Note 5) tS tH tREM tPHL, tPLH tPHL tSK(Pn-Pn) Maximum Clock Frequency Pulse Duration, CK, CK HIGH or LOW (Figure 2) Differential Inputs Activation Time, data inputs must be LOW after RESET HIGH (Figure 3) Differential Inputs De-activation Time, data and clock inputs must be held at valid levels (not floating) after RESET LOW Setup Time, Fast Slew Rate (Note 6)(Note 7) (Figure 5) Setup Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5) Hold Time, Fast Slew Rate (Note 6)(Note 8) (Figure 5) Hold Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5) Reset Removal Time (Figure 7) Propagation Delay CLK, CLK to Qn (Figure 4) Propagation Delay RESET to Qn (Figure 6) Output to Output Skew 0.65 0.9 0.75 0.9 10 1.1 2.8 5.0 200 ns ns ns ns ns ps 22 ns 200 2.5 22 2.5V r 0.2V Max MHz ns ns
Note 4: Refer to Figure 1 through Figure 7. Note 5: This parameter is not production tested. Note 6: For data signal input slew rate t 1 V/ns. Note 7: For data signal input slew rate t 0.5 V/ns and 1 V/ns. Note 8: For CK, CK signals input slew rates are t 1 V/ns.
AC Electrical Characteristics (SSTVN16857) (Note 9)
TA Symbol Parameter VDD 0qC to 70qC, CL 30 pF, RL 50: Units 2.5V r 0.2V; VDDQ Min fMAX tW tACT (Note 5) tINACT (Note 5) tS tH tREM tPHL, tPLH tPSS tPHL tSK(Pn-Pn) Maximum Clock Frequency Pulse Duration, CK, CK HIGH or LOW (Figure 2) Differential Inputs Activation Time, data inputs must be LOW after RESET HIGH (Figure 3) Differential Inputs De-activation Time, Data and Clock Inputs must be held at valid levels (not floating) after RESET LOW Setup Time, Fast Slew Rate (Note 9)(Note 12) (Figure 5) Setup Time, Slow Slew Rate (Note 12)(Note 13) (Figure 5) Hold Time, Fast Slew Rate (Note 11)(Note 13) (Figure 5) Hold Time, Slow Slew Rate (Note 12)(Note 13) (Figure 5) Reset Removal Time (Figure 7) Propagation Delay CLK, CLK to Qn (Figure 4) Propagation Delay Simultaneous Switching CLK, CLK to Qn (Note 14) Propagation Delay RESET to Qn (Figure 6) Output to Output Skew 0.65 0.75 0.75 0.9 10 1.1 2.4 2.7 5.0 200 ns ns ns ns ns ns ps 22 ns 220 2.5 22 2.5V r 0.2V Max MHz ns ns
Note 9: Refer to Figure 1 through Figure 7. Note 10: This parameter is not production tested. Note 11: For data signal input slew rate t 1 V/ns. Note 12: For data signal input slew rate t 0.5 V/ns and 1 V/ns. Note 13: For CK, CK signals input slew rates are t 1 V/ns. Note 14: Simultaneous Switching is guaranteed by characterization.
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SSTV16857 * SSTVN16857
Capacitance (Note 15)
Symbol CIN Parameter Data Pin Input Capacitance CK, CK - Input Capacitance RESET
Note 15: TA
Min 2.0 2.5 2.5
Typ
Max 3.0 3.5 3.5
Units pF pF pF VDD VDD VDD 2.5V, VI
Conditions VREF r 350 mV 1.25V, VI(PP) 360 mV
2.5V, VICR 2.5V, VI
VDD to GND
25qC, f
1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms (See Notes A through F below)
Note: CL includes probe and jog capacitance
FIGURE 1. AC Test Circuit
FIGURE 2. Voltage Waveforms - Pulse Duration
Note: IDD tested with clock and data inputs held at VDD or GND, and IO 0 mA.
FIGURE 3. Voltage and Current Waveforms Inputs Active and Inactive Times
FIGURE 4. Voltage Waveforms Propagation Delay Times
FIGURE 5. Voltage Waveforms - Setup and Hold Times
FIGURE 6. Voltage Waveforms RESET Propagation Delay Times Note A: All input pulses are supplied by generators having the following characteristics: PRR d 10 MHz, Z0 50:, input slew rate 1V/ns r 20% (unless otherwise specified). Note B: The outputs are measured one at a time with one transition per measurement. Note C: VTT VREF VDD/2. Note D: VIH VREF 310 mV (AC voltage levels) for differential inputs. VIH VDD for LVCMOS input. Note E: VIL VREF 310 mV (AC voltage levels) for differential inputs. VIL GND for LVCMOS input.
FIGURE 7. Voltage Waveforms RESET Removal Delay Times
Note F: Removal time (tREM) is tested with one data input held active HIGH. The propagation time from CK to the corresponding output must meet valid timing specifications for the measurement to be accurate.
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SSTV16857 * SSTVN16857 14-Bit Register with SSTL-2 Compatible I/O and Reset
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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