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SRDA05-4R2 Low Capacitance Surface Mount TVS for High-Speed Data Interfaces
The SRDA05-4 transient voltage suppressor is designed to protect equipment attached to high speed communication lines from ESD, EFT, and lightning.
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* SO-8 Package * Peak Power - 500 Watts 8 x 20 mS * ESD Rating:
IEC 61000-4-2 (ESD) 15 kV (air) 8 kV (contact) IEC 61000-4-4 (EFT) 40 A (5/50 ns) IEC 61000-4-5 (lightning) 23 (8/20 ms) UL Flammability Rating of 94 V-0
SO-8 LOW CAPACITANCE VOLTAGE SUPPRESSOR 500 WATTS PEAK POWER 6 VOLTS
PIN CONFIGURATION AND SCHEMATIC
I/O 1 1 REF 1 2 8 REF 2 7 I/O 4 6 I/O 3 5 REF 2
*
Typical Applications:
* High Speed Communication Line Protection
MAXIMUM RATINGS
Rating Peak Power Dissipation 8 x 20 mS @ TA = 25C (Note 1) Junction and Storage Temperature Range Lead Solder Temperature - Maximum 10 Seconds Duration Symbol Ppk TJ, Tstg TL Value 500 -55 to +150 260 Unit W C C
REF 1 3 I/O 2 4
8 1 SO-8 CASE 751 PLASTIC
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Non-repetitive current pulse 8 x 20 mS exponential decay waveform
MARKING DIAGRAM
8 SRDA5 AYWW 1 SRDA5 A Y WW = Specific Device Code = Assembly Location = Year = Work Week
ORDERING INFORMATION
Device SRDA05-4R2 Package SO-8 Shipping 2500/Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2006
1
January, 2006 - Rev. 4
Publication Order Number: SRDA05-4R2/D
SRDA05-4R2
ELECTRICAL CHARACTERISTICS
Characteristic Reverse Breakdown Voltage @ It = 1.0 mA Reverse Leakage Current @ VRWN = 5.0 Volts Maximum Clamping Voltage @ IPP = 1.0 A, 8 x 20 mS Maximum Clamping Voltage @ IPP = 10 A, 8 x 20 mS Between I/O Pins and Ground @ VR = 0 Volts, 1.0 MHz Between I/O Pins @ VR = 0 Volts, 1.0 MHz Symbol VBR IR VC VC Capacitance Capacitance Min 6.0 N/A N/A N/A - - Typ - - - - 10 5 Max - 10 9.8 12 15 8 Unit V mA V V pF pF
ELECTRICAL CHARACTERISTICS
(TA = 25C unless otherwise noted) UNIDIRECTIONAL (Circuit tied to Pins 1 and 3 or 2 and 3) Symbol IPP VC VRWM IR VBR IT QVBR IF VF ZZT IZK ZZK Parameter Maximum Reverse Peak Pulse Current Clamping Voltage @ IPP Working Peak Reverse Voltage Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT Test Current Maximum Temperature Coefficient of VBR Forward Current Forward Voltage @ IF Maximum Zener Impedance @ IZT Reverse Current Maximum Zener Impedance @ IZK VC VBR VRWM IF
I
IR VF IT
V
IPP
Uni-Directional TVS
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SRDA05-4R2
TYPICAL CHARACTERISTICS
9 VZ, REVERSE BREAKDOWN (V) IR, REVERSE LEAKAGE (mA) -50 0 50 100 T, TEMPERATURE (C) 150 200 8 7 6 5 4 3 2 1 0 -100 8 7 6 5 4 3 2 1 0 -100 -50 0 50 100 150 200
T, TEMPERATURE (C)
Figure 1. Reverse Breakdown versus Temperature
100 % OF PEAK PULSE CURRENT 90 80 70 60 50 40 30 20 10 0 0 20 40 t, TIME (ms) 60 80 tP PEAK VALUE IRSM @ 8 ms PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms HALF VALUE IRSM/2 @ 20 ms VC, CLAMPING VOLTAGE (V) 35 30 25 20 15 10 5 0 0
Figure 2. Reverse Leakage versus Temperature
tr
10
20
30
40
50
60
70
80
90
IPP, PEAK PULSE CURRENT (A)
Figure 3. 8 x 20 ms Pulse Waveform
Figure 4. Clamping Voltage versus Peak Pulse Current
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SRDA05-4R2
APPLICATIONS INFORMATION The SRDA05-4R2 is a low capacitance TVS diode array designed to protect sensitive electronics such as communications systems, computers, and computer peripherals against damage due to ESD events or transient overvoltage conditions. Because of its low capacitance, it can be used in high speed I/O data lines. The integrated design of the SRDA05-4R2 offers surge rated, low capacitance steering diodes and a TVS diode integrated in a single package (SO-8). If a transient condition occurs, the steering diodes will drive the transient to the positive rail of the power supply or to ground. The TVS device protects the power line against overvoltage conditions avoiding damage to the power supply and other downstream components. SRDA05-4R2 Configuration Options The SRDA05-4R2 is able to protect up to four data lines against transient overvoltage conditions by driving them to a fixed reference point for clamping purposes. The steering diodes will be forward biased whenever the voltage on the protected line exceeds the reference voltage (Vf or Vcc+Vf). The diodes will force the transient current to bypass the sensitive circuit. Data lines are connected at pins 1, 4, 6 and 7. The negative reference is connected at pins 5 and 8. These pins must be connected directly to ground using a ground plane to minimize the PCB's ground inductance. It is very important to reduce the PCB trace lengths as much as possible to minimize parasitic inductances. Option 1 Protection of four data lines and the power supply using Vcc as reference.
I/O 1 I/O 2 I/O 3 1 2 VCC 3 4 I/O 3 I/O 4 8 7 6 5 I/O 4
Option 2 Protection of four data lines with bias and power supply isolation resistor.
I/O 1 I/O 2 VCC 1 10 K 2 3 4 I/O 3 I/O 4 8 7 6 5
The SRDA05-4R2 can be isolated from the power supply by connecting a series resistor between pins 2 & 3 and Vcc. A 10 kW resistor is recommended for this application. This will maintain a bias on the internal TVS and steering diodes, reducing their capacitance. Option 3 Protection of four data lines using the internal TVS diode as reference.
I/O 1 I/O 2 1 NC NC 2 3 4 8 7 6 5
In applications lacking a positive supply reference or those cases in which a fully isolated power supply is required, the internal TVS can be used as the reference. For these applications, pins 2 and 3 are not connected. In this configuration, the steering diodes will conduct whenever the voltage on the protected line exceeds the working voltage of the TVS plus one diode drop (Vc=Vf + VTVS). ESD Protection of Power Supply Lines When using diodes for data line protection, referencing to a supply rail provides advantages. Biasing the diodes reduces their capacitance and minimizes signal distortion. Implementing this topology with discrete devices does have disadvantages. This configuration is shown below:
For this configuration, connect pins 2 & 3 directly to the positive supply rail (Vcc). The data lines are referenced to the supply voltage. The internal TVS diode prevents overvoltage on the supply rail. Biasing of the steering diodes reduces their capacitance.
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SRDA05-4R2
Power Supply
VCC
IESDpos
Protected Data Line Device
D1
IESDpos IESDneg
D2 IESDneg VF + VCC -VF
Looking at the figure above, it can be seen that when a positive ESD condition occurs, diode D1 will be forward biased while diode D2 will be forward biased when a negative ESD condition occurs. For slower transient conditions, this system may be approximated as follows: For positive pulse conditions: Vc = Vcc + VfD1 For negative pulse conditions: Vc = -VfD2 ESD events can have rise times on the order of some number of nanoseconds. Under these conditions, the effect of parasitic inductance must be considered. A pictorial representation of this is shown below.
Power Supply VCC Protected Device D1 Data Line D2 VC = VCC + Vf + (L diESD/dt) IESDneg IESDpos IESDneg
inductance will provide significant benefits in transient immunity. Even with good board layout, some disadvantages are still present when discrete diodes are used to suppress ESD events across datalines and the supply rail. Discrete diodes with good transient power capability will have larger die and therefore higher capacitance. This capacitance becomes problematic as transmission frequencies increase. Reducing capacitance generally requires reducing die size. These small die will have higher forward voltage characteristics at typical ESD transient current levels. This voltage combined with the smaller die can result in device failure. The ON Semiconductor SRDA05-4R2 was developed to overcome the disadvantages encountered when using discrete diodes for ESD protection. This device integrates a TVS diode within a network of steering diodes.
D1 D3 D5 D7
D2
D4
D6
D8
IESDpos
0 SRDA05-4R2 Equivalent Circuit
During an ESD condition, the ESD current will be driven to ground through the TVS diode as shown below.
Power Supply VCC D1 IESDpos
VC = -Vf - (L diESD/dt)
An approximation of the clamping voltage for these fast transients would be: For positive pulse conditions: Vc = Vcc + Vf + (L diESD/dt) For negative pulse conditions: Vc = -Vf - (L diESD/dt) As shown in the formulas, the clamping voltage (Vc) not only depends on the Vf of the steering diodes but also on the L diESD/dt factor. A relatively small trace inductance can result in hundreds of volts appearing on the supply rail. This endangers both the power supply and anything attached to that rail. This highlights the importance of good board layout. Taking care to minimize the effects of parasitic
Protected Device
Data Line D2
The resulting clamping voltage on the protected IC will be: Vc = VFD1 + VTVS. The clamping voltage of the TVS diode is provided in Figure 4 and depends on the magnitude of the ESD current. The steering diodes are fast switching devices with unique forward voltage and low capacitance characteristics.
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SRDA05-4R2
TYPICAL APPLICATIONS
UPSTREAM USB PORT VBUS VBUS D+ D- GND VBUS USB Controller RT RT VBUS
SRDA05-4R2
VBUS VBUS D+ D- GND
DOWNSTREAM USB PORT
CT CT
VBUS
NUP2201MR6
VBUS RT D+ RT CT CT D- GND DOWNSTREAM USB PORT
ESD Protection for USB Port
RJ45 Connector TX+ TX+
TX- TX- PHY Ethernet (10/100) RX+ Coupling Transformers
RX+
RX- RX- SRDA05-4R2 VCC GND N/C N/C
Protection for Ethernet 10/100 (Differential mode)
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SRDA05-4R2
R1 RTIP R2 RRING VCC R3 T1
T1/E1 TRANCEIVER SRDA05-4R2
R4 TTIP R5 TRING T2
TI/E1 Interface Protection
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SRDA05-4R2
PACKAGE DIMENSIONS
SO-8 CASE 751-07 ISSUE AG
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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SRDA05-4R2/D

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