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Preliminary Product Description The SLD2083CZ is a 10 Watt high performance LDMOS transistor designed for operation to 2700MHz. It is an excellent solution for applications requiring high linearity and efficiency at a low cost. The SLD2083CZ is typically used in the design of driver stages for power amplifiers, repeaters, and RFID applications. The power transistor is fabricated using Sirenza's high performance XeMOS IITM process. Functional Schematic Diagram SLD2083CZ Pb RoHS Compliant & Green Package 10 Watt Discrete LDMOS Device Ceramic Package Product Features ESD Protection * * * * * * * * * 10 Watt Output P1dB Single Polarity Supply Voltage High Gain: 18 dB Typical High Efficiency Advanced, XeMOS II LDMOS Integrated ESD Protection, Class 1A Applications Base Station PA driver Repeater RFID Case Flange = Ground RF Specifications Parameter Frequency Gain Efficiency IRL Description: Test Conditions in Sirenza Evaluation Board VDS = 28.0V, IDQ = 125mA, TFlange = 25C Frequency of Operation 10 Watt CW, 902MHz-928MHz Drain Efficiency at 10 Watt CW, 915MHz Input Return Loss, 10 Watt Output Power, 915MHz 3rd Order IMD at 10 Watt PEP (Two Tone), 915MHz 1dB Compression (P1dB), 915MHz ACPR=-55dB, IS-95 ACPR=-45dB, IS-95 Unit MHz dB % dB dBc Watt Watt Watt Min 17 40 10 1.8 3.2 Typ 18 47 -15 -28 11 1.6 3.6 Max 2700 -10 -26 - Linearity The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2005 Sirenza Microdevices, Inc. All worldwide rights reserved. 303 S. Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC 1 http://www.sirenza.com EDS-103754 Rev D Preliminary SLD2083CZ 10 Watt LDMOS FET DC Specifications Parameter gm VGSThreshold VDS Breakdown Ciss Crss Coss RDSon Forward Transconductance @ 125mA IDQ IDS=3mA 1mA IDS current Input Capacitance (Gate to Source) VGS=0V, VDS=28V Reverse Capacitance (Gate to Drain) VGS=0V, VDS=28V Output Capacitance (Drain to Source) VGS=0V, VDS=28V Drain to Source Resistance, VGS=10V, VDS=250mV Unit mA / V Volt Volt pF pF pF Min Typical 590 3.8 65 27.5 0.81 14.65 0.6 Max Quality Specifications Parameter ESD Rating MTTF RTH Human Body Model 85oC Leadframe, 200oC Channel Thermal Resistance (Junction to Case) Unit Volts Hours C/W Min Typical 500 1.2 X 106 4 Max Pin Description Pin # 1 2 Flange Function Gate Drain Source, Gnd Description Transistor RF input and gate bias voltage. The gate bias voltage must be temperature compensated to maintain constant bias current over the operating temperature range. Care must be taken to protect against video transients that exceed the recommended maximum input power or voltage. . Transistor RF output and drain bias voltage. Typical voltage is 28V. Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for optimum thermal and RF performance. See mounting instructions for recommendation. Absolute Maximum Ratings Parameters Drain Voltage (VDS ) Gate Voltage (VGS) RF Input Power Load Impedance for Continuous Operation Without Damage Output Device Channel Temperature Lead Temperature During Solder Reflow Operating Temperature Range Storage Temperature Range Value 35 20 +33 10:1 +200 +270 -20 to +90 -40 to +100 Unit V V dBm VSWR C C C C Pin Diagram ESD Protection Pin 1 Pin 2 Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation see typical setup values specified in the table on page one. Case Flange = Ground Caution: ESD Sensitive Appropriate precaution in handling, packaging and testing devices must be observed. 303 S. Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC 2 http://www.sirenza.com EDS-103754 Rev D Preliminary SLD2083CZ 10 Watt LDMOS FET Typical EVB Test Data Gain, Efficiency vs. Output Power Freq=915MHz, Temp=25oC, VDS=28V, IDQ=125mA 20 19.9 Gain (dB) 19.8 19.7 19.6 19.5 19.4 0 2 4 6 8 10 12 14 Gain Efficiency 60 50 40 30 20 10 0 Efficiency (%) Output Power (W) Gain vs. Frequency and Temperature Pout=10W, VDS=28V, IDQ=125mA 20 19.5 Gain (dB) 19 18.5 18 17.5 900 905 910 915 920 925 930 90 Deg C 25 Deg C -20 Deg C Frequency (MHz) Two Tone IM3 vs. Output Power Freq=915/916MHz, Temp=25 oC, VDS=28V, IDQ=125mA -20.0 -25.0 -30.0 IMD3(dBc) -35.0 -40.0 -45.0 -50.0 -55.0 0.0 2.0 4.0 6.0 902MHz 915MHz 928MHz Average Output Power (W) 303 S. Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC 3 http://www.sirenza.com EDS-103754 Rev D Preliminary SLD2083CZ 10 Watt LDMOS FET SLD2083CZ EVB Layout and BoM Evaluation Board Bill of Materials Description Res, 10, 1/10W, 1%, 0805 Polarized Inductor Coilcraft 1.6nH 0603 Res, 0.0, 1/16W, 5%, 0603 Cap, 1000 pF, 100V, 10%, 0603 Cap, 0.01 uF, 100V, 5%, 0805 Cap, 0.5 pF, 250V, +/-.1pF, 0603 Cap, 3.6 pF, 250V, +/-.1pF, 0603 Cap, 12 pF, 250V, 1%, 0603 Cap, 15 pF, 250V, 2%, 0603 Cap, 68 pF, 250V, 5%, 0603 Res, 10 Ohm, 0402 CAP 0.22UF 50V CERAMIC X7R 1206 SLD2083CZ g R10 J1 L1 R2, R4, R6, R7, R9, R11 C7, C8 C10, C15 C11 C14 C2 C1 C3, C4, C5, C6 R5, R15 C13, C16 Q1 Part Impedance Information (Typical) Frequency (MHz) 870 880 900 930 960 Input R (Ohms) 0.5 0.5 0.8 0.7 0.8 Input X (Ohms) 2.0 1.9 1.8 1.7 1.4 Output R (Ohms) 4.3 4.3 4.4 4.5 4.7 Output X (Ohms) 1.9 2.0 2.0 2.0 2.0 Impedances are circuit impedances as seen from device at device lead. To download Gerber files, DXF drawings, a detailed BOM, and assembly recommendations for the test board with fixture contact Sirenza applications. 303 S. Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC 4 http://www.sirenza.com EDS-103754 Rev D Preliminary SLD2083CZ 10 Watt LDMOS FET Package Outline Drawings Chamferred Lead is FET Drain Lead Coplanarity Lead foot to backside 0.000 0.002 0.0000.002 0.290 0.160 R0.015 DETAIL A TOP VIEW 0.200 0.100 0.090 0.160 0.140 0.050 0.160 0.008 SIDE VIEW END VIEW DETAIL A Recommended Landing Pads for the RF083 Package Part Number Ordering Information Part Number SLD2083CZ Devices Per Reel 500 Reel Size 7'' All Dimensions are in inches 303 S. Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC 5 http://www.sirenza.com EDS-103754 Rev D |
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