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1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
S5K3A1EA (1/3" SXGA CMOS Image Sensor)
Preliminary Specification Revision 0.4 Jun, 2004
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S5K3A1EA
1/3" SXGA CMOS IMAGE SENSOR
DOCUMENT TITLE
1/3" Optical Size 1280x1024(SXGA) 2.8V / 1.8V CMOS Image Sensor
REVISION HISTORY
Revision No. 0.0 0.1 0.2 0.3 0.4 History Initial Draft DC Characteristics Changed. Register Map Updated. Imaging Characteristics Changed Imaging Characteristics Changed S5K3A1EA13 Product Added AC Characteristics Changed Ob_area Recommended Setting Changed Draft Date Feb.03, 2004 Mar.29.2004 Apr.09.2004 Jun.10.2004 Jun.11.2004 Remark Preliminary
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1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
INTRODUCTION
The S5K3A1EA is highly integrated single chip CMOS image sensor, fabricated by SAMSUNG 0.18um CMOS image sensor process technology. It is developed for image application to realize high efficiency photo sensor. The sensor has 1280 x 1024 effective pixels with 1/3 inch optical format. The sensor has on-chip 10-bit ADC blocks to digitize the pixel output and also on-chip CDS to reduce Fixed Pattern Noise (FPN) drastically. With its few interface signals and 10-bit raw data directly connected to the external devices, a camera system can be configured easily.
FEATURES
-- Process Technology: 0.18m Dual Gate Oxide SPQM CMOS -- Optical Size: 1/3 inch -- Unit Pixel: 3.8 m X 3.8 m -- Effective Resolution: 1280X1024, SXGA -- Line Progressive Read Out. -- 10-bit Raw Image Data Output -- Windowing and Panning -- Sub-Sampling (2X, 4X, 8X) -- Timing Generator for Frame Memoryless Scaler -- Timing Generator for Stepless Zooming -- Continuous and Single Frame Capture Mode -- Programmable Exposure Time and Gain Control -- Auto Dark Level Compensation -- Standby Mode for Power Saving -- Maximum 15 Frames per Second for Full Frame Readout with 24 MHz Output Data Rate -- Bad Pixel Replacement -- Dual Power Supply Voltage: 2.8V/1.8V (2.8V for analog, 1.8V for digital) -- Package Type: 48-CLCC/PLCC
PRODUCTS
Product Code S5K3A1EA01 S5K3A1EA02 S5K3A1EA03 S5K3A1EA13 Power Supply 2.8V / 1.8 V 2.8V / 1.8 V 2.8V / 1.8 V 2.8V / 1.8 V Backend Process None On-chip micro lens On-chip color filter and micro lens On-chip color filter and micro lens Description Monochrome image sensor High sensitivity monochrome Image sensor RGB color image sensor RGB color image sensor
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S5K3A1EA
1/3" SXGA CMOS IMAGE SENSOR
BLOCK DIAGRAM
VDDIO
VSSIO
VDDD VSSD
MCLK
Main Clock Divider
10-bit Column ADC Odd Column CDS DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
RSTN STBYN STRB VSYNC HSYNC DCLK
Active Pixel Sensor Array
Control Registers SCL SDA
Even Column CDS 10-bit Column ADC
I2C Interface
4
Processing
Row Driver
Timing Generator
VDDA VSSA
Post
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
PIXEL ARRAY MAP (TOP VIEW ON CHIP. DISPLAYED IMAGE WILL BE FLIPPED.)
Active Pixels 10 4
Optical Black Pixels
Default Window of Interest 1280X1024
GBGBGB RGRGRG GBGBGB RGRGRG
10
4
GBGBGB RGRGRG GBGBGB RGRGRG GBGBGB RGRGRG
GBGBGB RGRGRG
4
10
(14,14) read out start point (0,0)
4 10
5
S5K3A1EA
1/3" SXGA CMOS IMAGE SENSOR
PIN CONFIGURATION
VDDIO
VSSD
VSSA
VSSA
VDDA
VDDA
VDDA
VDDD
6
5
4
3
2
48
VDDD
47
46
45
44
VDDA
VSSA
MCLK DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DCLK
7 8 9 10 11 12 13 14 15 16 17 19 20 21 22 23
1
43
VSSA 42 41 40 39 38 37 36 35 34
SDA SCL RSTN STBYN STRB VDDA VSSA VREF TEST2 TEST1 HSYNC VSYNC
First Readout Pixel
33 32
24
25
26
27
28
29 VDDA
VDDD
VSSD
VSSA
VSSA
VSSA
VDDA
VDDA
6
VSSIO
VSSD
VDDA
VSSA
30
18
31
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
MAXIMUM ABSOLUTE RATINGS
Characteristic Analog maximum absolute voltage (VDDA supply relative to VSSA ) Digital and I/O maximum absolute voltage (VDDIO supply relative to VSSIO VDDD supply relative to VSSD) Input voltage Operating temperature Storage temperature Symbol VDDH VDDL VIN TOPR TSTG Value -0.3 to 3.8 -0.3 to 2.7 -0.3 to 2.7 -20 to +60 -40 to +125(1) -40 to +85(2)
NOTES: 1. The maximum allowed storage temperature for S5K3A1EA01. 2. The maximum allowed storage temperature for S5K3A1EA02 and S5K3A1EA03.
Unit V
C
7
S5K3A1EA
1/3" SXGA CMOS IMAGE SENSOR
ELECTRICAL CHARACTERISTICS
DC Characteristics (TA = -20 to +60C, CL = 15pF) Characteristics Operating voltage Symbol VDDH VDDL Input voltage(1) VIH VIL Input leakage current(2) Input leakage current with pull-down(3) High level output voltage(4) IOH = -4mA Low level output voltage(5) High-Z output leakage current(6) Input capacitance(1) Supply current IOZ CIN ISTBL VOL IOL = 1A IOL = 4mA VOUT = VSS or VDDL STBYN=Low(Active) All input clocks = Low 0 lux illumination applied to VDDIO and VDDD pin STBYN=Low(Active) All input clocks = Low 0 lux illumination applied to VDDA pin fMCLK = 12MHz 0 lux illumination applied to VDDIO and VDDD pin fMCLK = 12MHz 0 lux illumination applied to VDDA pin IIL IILD VOH VIN = VDDL VIN = VDDL IOH = -1A Condition applied to VDDA pins applied to VDDIO and VDDD pin Min 2.6 1.65 1.27 -10 5 VDDL0.05 1.2 -10 Typ 2.8 1.8 18 Max 3.0 1.95 0.57 10 40 0.05 0.45 10 4 10 A pF A V A Unit V
ISTBH
-
-
10
A
IDDL
-
10
15
mA
IDDH
-
20
25
mA
NOTES: 1. Applied to MCLK, RSTN, STBYN, STRB, SCL, SDA, TEST1, TEST2 pins. 2. Applied to MCLK, RSTN, STBYN, STRB, SCL, SDA pins 3. Applied to TEST1, TEST2 pin 4. Applied to DCLK, HSYNC, VSYNC, DATA0 to DATA9 pin. IOH : High level output current 5. Applied to DCLK, HSYNC, VSYNC, DATA0 to DATA9, SCL, SDA pin. IOL : Low level output current 6. Applied to SDA pin when in High-Z output state
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1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
9
S5K3A1EA
1/3" SXGA CMOS IMAGE SENSOR
Imaging Characteristics (Light source with 3200K of color temperature and IR cut filter (CM-500S, 1mm thickness) is used. Electrical operating conditions follow the recommended typical values. The control registers are set to the default values. TA = 25C if not specified.) Characteristic Saturation level(1) Sensitivity(2) Dark level(3) Symbol VSAT S VDARK Condition TA = 40C TA = 60C Dynamic range(4) Signal to noise ratio(5) Dark signal non-uniformity(6) Photo response nonuniformity(7) Vertical fixed pattern noise(8) Horizontal fixed pattern noise(9) DR S/N DSNU PRNU VFPN HFPN TA = 60C Min 600 Typ 650 1500 4 20 60 40 4 4 4 Max 8 40 40 8 8 8 mV/sec % % % dB Unit mV mV/lux sec mV/sec
NOTES: 1. Measured minimum output level at 100 lux illumination for exposure time 1/30 sec. 7X7 rank filter is applied for the whole pixel area to eliminate the values from defective pixels. 2. Measured average output at 25% of saturation level illumination for exposure time 1/30 sec. Green channel output values are used for color version. 3. Measured average output at zero illumination without any offset compensation for exposure time 1/30 sec. 4. 20 log (saturation level/ dark level RMS noise excluding fixed pattern noise). 60dB is limited by 10-bit ADC. 5. 20 log (average output level / RMS noise excluding fixed pattern noise) at 25% of saturation level illumination for exposure time 1/30 sec. 6. Difference between maximum and minimum pixel output levels at zero illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to eliminate the values from defective pixels. 7, Difference between maximum and minimum pixel output levels divided by average output level at 25% of saturation level illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to eliminate the values from defective pixels. 8. For the column-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec. 9. For the row-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for neighboring 7 rows at 25% of saturation level illumination for exposure time 1/30 sec.
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1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
AC Characteristics (VDDH = 2.8V 0.25V, VDDL = 1.8V 0.15V, TA = -20 to + 60 C, CL = 10pF) Characteristic Main input clock frequency Data output clock frequency Propagation delay time from main input clock Symbol fMCLK fDCLK tPDMV tPDMH tPDMD tPDMO Propagation delay time from data output clock tPDDV tPDDH tPDDO Reset input pulse width Standby input pulse width tWRST tWSTB Condition Duty = 50% VSYNC output HSYNC output DCLK output DATA output VSYNC output HSYNC output DATA output RSTN=low(active) STBYN=low(active) Min 6 6 5 4 Typ 12 12 Max 48 30 10 10 6 10 4 4 4 TMCLK(1) ns Unit MHz
NOTES: 1. TMCLK is the period of the master input clock, MCLK.
0.5VDD tPDMD DCLK tPDDO DATA tPDMO tPDDH HSYNC tPDMH tPDDV tPDDH tPDMD
MCLK
tPDMH
VSYNC
tPDMV
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S5K3A1EA
1/3" SXGA CMOS IMAGE SENSOR
MCLK tWRST RSTN tWSTB
STBYN system reset partial power down complete power down
I2C Serial Interface Characteristics (1) Characteristic Clock frequency Clock high pulse width Clock low pulse width Clock rise/fall time Data set-up time Data hold time START condition setup time START condition hold time STOP condition setup time STOP to new START gap Capacitance for each pin Capacitive bus load Pull-up resistor Symbol fSCL tWH tWL tR/tF tDS tDH tSTRS tSTRH tSTPS tGSS CPIN CBUS RPU Condition SCL SCL SCL, SDA SDA to SCL SCL to SDA SCL, SDA SCL, SDA SCL, SDA to VDD Min 0.6 1.3 0.1 4 4 4 8 1.5 4 200 10 k pF Typ Max 400 0.3 0.9 TMCLK(2) Unit kHz s
NOTES: 2 1. I C is a proprietary Phillips interface bus. 2. TMCLK is the period of the master input clock, MCLK.
tWL 0.9VDD SCL 0.1VDD tSTRH tDH tDS tSTPS tWH tF tR
tSTRS 0.9VDD
SDA
0.1VDD
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1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
PIN DESCRIPTION
Pin No VDDD (6,25,48) VDDIO (5) VSSD (19,26,47) VSSIO (20) VDDA(1,4,21,24, 28,29,37,44,45) VSSA(2,3,22,23, 27,30,36,43,46) MCLK (7) RSTN (40) STBYN (39) STRB (38) DATA0~DATA9 (8 ~ 17) DCLK (18) HSYNC (32) VSYNC (31) SCL (41) SDA (42) VREF (35) TEST1 (33) I/O Power Power Power Power Power Power I I I I O O O O I I/O I/O I Master clock Reset Standby Strobe Image data output Data clock Horizontal sync clock Vertical sync clock Serial interface clock Serial interface data Reference voltage Test input 1 Analog power supply Name Digital power supply For I/O circuit (VDDL) 0V (GND) 0V (GND) For analog circuit (VDDH) 0V (GND) Master clock pulse input for all timing generators. Initializing all the device registers. (Active low) Activating power saving mode. ( high=normal operation, low=power saving mode ) Triggering the integration start and stop when single frame capture mode. 10-bit image data outputs. When ADC resolution is reduced, the unused lower bits are set to 0. Image data output synchronizing pulse output. Horizontal synchronizing pulse or data valid signal output. Vertical synchronizing pulse or line valid signal output. I2C serial interface clock input I2C serial interface data bus (external pull-up resistor required) For proper operation, the external capacitor larger than 0.1uF must be connected between VREF and VDDA. Test input signal. Though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins. Test input signal. Though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins. Function For logical circuit (VDDL)
TEST2 (34)
I
Test input 2
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S5K3A1EA
1/3" SXGA CMOS IMAGE SENSOR
CONTROL REGISTERS
Address (Hex) 00h Reset Value 01h Bits [7] [6] [5] [4:2] Mnemonic p2_r_con bprm ccsm mcdiv Description (Factory use only) CDS timing control Bad pixel replacement mode 0b: disabled (default), 1b: enabled Color channel separation mode 0b: not separated (default), 1b: separated Main clock divider 000b: DCLK=MCLK(default), 001b: DCLK=MCLK/2 010b: DCLK=MCLK/4, 011b: DCLK=MCLK/8 100b: DCLK=MCLK/16, 101b: DCLK=MCLK/32 111b: forbidden value Electronic shutter mode 0b: disabled (default), 1b: enabled ADC resolution 0b: 8-bit, 1b: 10-bit (default) Shutter error correction register Vertical mirror control 0b: normal (default), 1b: mirrored Horizontal mirror control 0b: normal (default), 1b: mirrored Row sub-sampling mode 00b: disabled (default), 01b: 2X, 10b: 4X, 11b: 8X Column sub-sampling mode 00b: disabled (default), 01b: 2X, 10b: 4X, 11b: 8X Row start point for window of interest wrp[10:0] = 14d(default) Column start point for window of interest wcp[10:0] = 14d(default) Row depth for window of interest wrd[10:0] = 1024d(default) Column width for window of interest wcw[10:0] = 1280d(default) (Factory use only) Analog offset reference offsdef[7:0] = 128d (default)
[1] [0] 01h 00h [7] [6] [5] [4] [3:2]
shutc adcres shut_err_cor Not_use mircv mirch subsr
[1:0]
subsc
02h 03h 04h 05h 06h 07h 08h 09h 0Ah
00h 0Eh 00h 0Eh 04h 00h 05h 00h 80h
[2:0] [7:0] [2:0] [7:0] [2:0] [7:0] [2:0] [7:0] [7:0]
wrp_high wrp_low wcp_high wcp_low wrd_high wrd_low wcw_high wcw_low offsdef
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1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
Address (Hex) 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h
Reset Value 04h 65h 04h 65h 00h 00h 00h
Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7] [6] [5] [4] [3] [2] [1]
Mnemonic sint_high sint_low cintr_high cintr_low cintc_high cintc_low hspolar hsdisp vspolar vsdisp global_mod roll_mod mech_mod
Description Integration time in single frame capture mode sint[15:0] = 1125d (default) Row-step integration time in continuous frame capture mode cintr[15:0] = 1125d (default) Column-step integration time in continuous frame capture mode cintc[15:0] = 0d (default) HSYNC polarity 0: active high (default), 1: active low HSYNC display mode 0: sync mode (default), 1: data valid mode VSYNC polarity 0: active high (default), 1: active low VSYNC display mode 0: sync mode (default), 1: data valid mode Single frame capture integration mode Field shift shutter mode Single frame capture integration mode Rolling shutter mode Single frame capture integration mode simultaneous frame integration with mechanical shutter Single frame capture mode enable 0b: disabled (default), 1b: enabled VSYNC width vswd[7:0] = 1d (default) VSYNC start position vsstrt[9:0] = 0d (default) Vertical blank depth vblank[12:0] = 101d (default) HSYNC width hswd[7:0] = 32d (default) HSYNC start position hsstrt[9:0] = 0d (default) Horizontal blank depth hblank[15:0] = 142d (default)
[0] 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 01h 00h 00h 00h 65h 20h 00h 00h 00h 8Eh [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
sfcen vswd vsstrt_high vsstrt_low vblank_high vblank_low hswd hsstrt_high hsstrt_high hblank_high hblank_low
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S5K3A1EA
1/3" SXGA CMOS IMAGE SENSOR
Address (Hex) 1Ch 1Dh
Reset Value 00h 00h
Bits [6:0] [6:0]
Mnemonic pgcr pgcg1 Red channel gain
Description
pgcr[6:0] = 0d (default) Green(Red row) channel gain or all channel gain (ccsm=0) pgcg1[6:0] = 0d (default) 1Eh 1Fh 20h 21h 22h 23h 24h 25h 00h 00h 0Fh 0Fh 0Fh 0Fh 80h 80h [6:0] [6:0] [4:0] [4:0] [4:0] [4:0] [7:0] [7:0] pgcg2 pgcb sgg1 sgg2 sgg3 sgg4 offsr offsg1 Green(Blue row) channel gain pgcg2[6:0] = 0d (default) Blue channel gain pgcb[6:0] = 0d (default) 1 quadrisectional global gain sgg1[4:0] = 0F(default) 2 quadrisectional global gain sgg2[4:0] = 0F(default) 3 quadrisectional global gain sgg3[4:0] = 0F(default) 4 quadrisectional global gain sgg4[4:0] = 0F(default) Red channel analog offset Offsr[7:0] = 128 (default) Green(Red row) channel analog offset or all channel offset (ccsm=0) offsg1[7:0] = 128 (default) 26h 27h 28h 80h 80h 14h [7:0] [7:0] [7] [6:0] 29h 00h [7:0] offsg2 offsb clipen pthresh adcoffs Green(Blue row) channel analog offset offsg2[7:0] = 128 (default) Blue channel analog offset offsb[7:0] = 128 (default) (Factory use only) Reset clipping enable Bad pixel threshold pthresh[6:0] = 20d (default) ADC offset (count delay register) adcoffs[7:0] = 0d (default) ADLC formula : Dfinal = D(n) + adcoffs When adcoffs[7] is 1 , adc offset is +adcoffs[6:0], else adc offset is - adcoffs[6:0]
th rd nd st
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1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
Address (Hex) 2Ah 2Bh 2Ch 2Dh
Reset Value 40h 00h 00h 02h
Bits [7:5] [4:0] [7:0] [7:0] [7:6] [5] [4] [3:2] [1] [0]
Mnemonic stbystrt stbystp rxstrt blank Not_use id_inv sck_inv Not_use i2ctest nandtree adlc_mod_d adlc_mod_c adlc_mod_b adlc_mod_a feedback_gain_B
Description (Factory use only) Stand-by start (Factory use only) Stand-by stop (Factory use only) Reset start control Blank register for general purpose (Factory use only) Line color inversion (Factory use only) Column color inversion (Factory use only) IIC test mode (Factory use only) NAND tree test mode Adlc mode always enable when this register is high. 0b: disabled (default), 1b: enabled Adlc mode works when gain values are changed 0b: disabled (default), 1b: enabled Adlc mode works when shutter values are changed 0b: disabled (default), 1b: enabled Adlc mode works till adlc length value 0b: disabled (default), 1b: enabled Feedback gain value about ADLC 00b : 0, 01b : 0.5(default), 10b : 0.75, 11b : 1 ADLC formula : Dfinal = D(n) + adcoffs D(n) = A*(OB(n) + OB(n-1)) + B*D(n-1) Feedback gain value about ADLC 00b : 0, 01b : 0.5, 10b : 0.25(default), 11b : 0.125
2Eh
06h
[7] [6] [5] [4] [3:2]
[1:0]
feedback_gain_A
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S5K3A1EA
1/3" SXGA CMOS IMAGE SENSOR
Address (Hex) 2Fh
Reset Value 00h
Bits [7] [6] [5] [4] [3]
Mnemonic dckout_en dfo fixvs isp_sel ob_sel
Description DCK pad control 0b : output enable (default), 1b : stable value I/O driver fan-out control register. VSYNC always high at frame start point. 0b: disabled (default), 1b: enabled (Factory use only) ADLC formula : D = D(n) + adcoff D(n) = A*(OB(n) + OB(n-1)) + B*D(n-1) 0b : OB(n-1) = OB(n-1) (default) 1b : OB(n-1) = OB(n) OB area selection 0b:128*8 (default), 1b:512*2 (recommended) ADLC function works only during this value when adlc_mod_a enabled, 00b : 1 frame, 01b : 2 frames, 10b : 3 frames, 11b : 4 frames (Factory use only) rx & tx signals are enable only active area. 0b: disabled (default), 1b: enabled (Factory use only) 0b: disabled (default), 1b: enabled (Factory use only) 0b: disabled (default), 1b: enabled (Factory use only)When this register is zero, H-sync keeps same period in one frame. Guardband mode 0b: disabled, 1b: enabled(default) Stepless mode enable 0b: disabled (default), 1b: enabled Guardband start position Guardband end position Keep the same frame in zoom mode. This register compensates remainder of frame. (Factory use only) CDS timing control (Factory use only) CDS timing control (Factory use only) CDS timing control (Factory use only) CDS timing control
[2] [1:0]
ob_area adlc_length
30h
02h
[7:6] [5]
Not_use pwr_save2
[4] [3] [2] [1] [0] 31h 32h 33h 34h 35h 36h 1Eh 32h 00h 00h CCh CCh [7:0] [7:0] [5:0] [7:0] [7:4] [3:0] [7:4] [3:0]
pwr_save1 ggo_en rsm_en gbmod stpless_mod gb_start gb_end vs_postc_high vs_postc_low p12_stp p11_stp p2r_stp p2_stp
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1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
Address (Hex) 37h 38h 39h 3Ah
Reset Value 00h 00h 0Ah 1Ah
Bits [7:0] [7:0] [7:0] [7] [6] [5] [4] [3:0]
Mnemonic holdline_high holdline_low vsend_ofset-high Not use tx_add shutx_sel cal_en cal_stp
Description Active output delay about its register value
This register value is must larger than OB line. (Factory use only)Add tg to reduce NIT. (Factory use only)Enlarge shutter TX width to reduce NIT. (Factory use only) calibration enable (Factory use only) calibration signal control
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S5K3A1EA
1/3" SXGA CMOS IMAGE SENSOR
OPERATION DESCRIPTION
1. Output Data Format 1-1. Main Clock Divider All the data output and sync signals are synchronized to data clock output (DCLK). It is generated by dividing the input main clock (MCLK). The dividing ratio is 1, 2, 4, 8, 16, and 32 according to main clock dividing control register (mcdiv). For 10-bit ADC and SXGA resolution, dividing ratio of 1 is required. If dividing ratio of 1 is used, the duty must be within 40% to 60%. 1-2. Synchronous Signal Output The horizontal sync(HSYNC) and vertical sync(VSYNC) signals are also available. The sync pulse width, polarity and position are programmable by control registers (ref. timing chart). When display mode is enabled, the sync signal outputs indicate that the output data is valid (hsdisp=1) or the output rows are valid (vsdisp=1). 1-3. Window of Interest Control Window of Interest (WOI) is defined as the pixel address range to be read out. The WOI can be assigned anywhere on the pixel array. It is composed of four values: row start pointer(wrp), column start pointer(wcp), row depth(wrd) and column width(wcw). Each value can be programmed by control registers. For convenience of color signal processing, wcp is truncated to even numbers so that the starting data of each line is the red and green column of Bayer pattern. Figure 1 refers to a pictorial representation of the WOI on the displayed pixel image. 0 0 (wcp,wrp) wcw 1307
Window Of Interest wrd
1051 Figure 1. WOI definition. 1-4. Vertical Mirror and Horizontal Mirror Mode Control The pixel data are read out from left to right in horizontal direction and from top to bottom in vertical direction normally. By changing the mirror mode, the read-out sequence can be reversed and the resulting image can be flipped like a mirror image. Pixel data are read out from right to left in horizontal mirror mode and from bottom to top in vertical mirror mode. The horizontal and the vertical mirror mode can be programmed by Horizontal Mirror Control Register (mirch) and Vertical Mirror Control Register (mircv). 1-5. Sub-sampling Control The user can read out the pixel data in sub-sampling rate in both horizontal and vertical direction. Sub-sampling can be done in four rates : full, 1/2, 1/4 and 1/8. The user controls the sub-sampling using the Sub-sampling
20
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
Control Registers, subsr and subsc. The sub-sampling is performed only in the Bayer space. In Figure 2, the Bayer space sub-sampling examples are shown. R G R G R G R G R G R G R G R G G B G B G B G B G B G B G B G B R G R G R G R G R G R G R G R G GRGRGRGRGR BGBGBGBGBG GRGRGRGRGR BGBGBGBGBG GRGRGRGRGR BGBGBGBGBG GRGRGRGRGR BGBGBGBGBG GRGRGRGRGR BGBGBGBGBG GRGRGRGRGR BGBGBGBGBG GRGRGRGRGR BGBGBGBGBG GRGRGRGRGR BGBGBGBGBG subsr=01b, subsc=01b G B G B G B G B G B G B G B G B R G R G R G R G R G R G R G R G G B G B G B G B G B G B G B G B R G R G R G R G R G R G R G R G G B G B G B G B G B G B G B G B R G R G R G R G R G R G R G R G GRGRGRGRGR BGBGBGBGBG GRGRGRGRGR BGBGBGBGBG GRGRGRGRGR BGBGBGBGBG GRGRGRGRGR BGBGBGBGBG GRGRGRGRGR BGBGBGBGBG GRGRGRGRGR BGBGBGBGBG GRGRGRGRGR BGBGBGBGBG GRGRGRGRGR BGBGBGBGBG subsr=00b, subsc=10b G B G B G B G B G B G B G B G B R G R G R G R G R G R G R G R G G B G B G B G B G B G B G B G B
Figure 2. Bayer Space Sub-Sampling Examples 1-6. Line Rate and Frame Rate Control (Virtual Frame) The line rate and the frame rate can be changed by varying the size of virtual frame. The virtual frame's width and depth are controlled by effective WOI and blank depths. The effective WOI is scaled by the subsampling factors from WOI set by register values. For CDS and ADC function, the virtual column width must be larger than (adcres+1)*256/(2^mcdiv)+264, where adcres is the ADC resolution control register value. The horizontal and vertical blanking time (hblank, vblank) should be over 60 and 4, respectively. The detailed restriction of h-blank period is shown in table 1. Table 1. Restriction of h-blank period (minimum 1H-period(dck) minimum 1H-period(dck) mcdiv[2:0] 0 1 2 3 4 5 adcres = 1 1412 836 548 404 332 300 adcres = 0 548 404 332 300 278 270
Setting procedure of hblank, vblank and vs_postc is as follows. Frame cycle = ((wcw>>subsc) + hblank) x ((wrd>>subsr) + vblank) + vs_postc vblank >= 4 (isp_sel=1) vs_postc < 1H ( (wcw>>subsc) + hblank) ) 1-7. Continuous Frame Capture Mode(CFCM) Integration Time Control (Electronic Shutter Control)
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S5K3A1EA
1/3" SXGA CMOS IMAGE SENSOR
In CFCM operation, the integration time is controlled by shutter operation. The shutter operation is done when shutter control register (shutc) is set to "1". In shutter operation, the integration time is determined by the Row Step Integration Time Control Register(cintr) and Column Step Integration Time Control Register(cintc) In CFCM integration time control. There are two different modes. One is normal shutter mode. The other is shutter TX wide mode to reduce nonlinear integration time. The effective integration time(EIT) formulas of each mode are as follows. 1) normal mode (00h[2] = 1, 01h[7] = 1, 3Ah[5] = 1) EIT = (cintr - 1) x ( (wcw>>subsc) + hblank ) + cintc + 145 (dck) restriction of cintr? 1 <= cintr <= (wrd>>subsr) + vblankr -1 restriction of cintc? 0 <= cintc <= (wcw>>subsc) + hblank - 7 2) shutter TX wide mode (00h[2] = 1, 01h[7] = 0, 3Ah[5] = 1) EIT = (cintr - 1) x ( (wcw>>subsc) + hblank ) + cintc + 145 (dck) restriction of cintr? 1 <= cintr <= (wrd>>subsr) + vblankr - 1 restriction of cintr? case of (1 <= cintr <= (wrd>>subsr) + vblankr - 2) 0 <= cintc <= (wcw>>subsc) + hblank - 7 case of (cintr = (wrd>>subsr) + vblankr - 1) 0 <= cintc <= (wcw>>subsc) + hblank - 195 1-8. Single Frame Capture Mode(SFCM) Integration Time Control To capture a still image, SFCM can be set by Single Frame Capture Enable Register(sfcen). There are two types of integration mode implemented. In the rolling shutter mode (sfcim=0), the integration time is controlled by SFCM Integration Time Register (sint). The light integration period for each rows progresses with reading rows. The integration time is expressed as : Integration Time = sint * (1 line time) In the mechanical shutter mode (sfcim=1), the integration time for all rows is the period during the external input signal, STRB is active. After STRB goes to be inactive, the external mechanical shutter should shut off incident lignt on image sensor and the data readout sequence starts.
2. Analog to Digital Converter ( ADC) The image sensor has on-chip ADC. Two-channel column parallel ADC scheme is used for separated color channel gain and offset control. 2-1. ADC resolution The default value of ADC resolution is 10bit and can be changed to 8bit or 9bit by control the ADC Resolution Control Register (adcres). Lowering ADC resolution reduces the required minimum line time. When the number of effective output bits is reduced, upper n-bits of output ports are valid and lower bits always have values of "0". 2-2. Correlated Double Sampling ( CDS ) The analog output signal of each pixel includes some temporal random noise caused by the pixel reset action
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1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
and some fixed pattern noise by the in-pixel amplifier offset deviation. To eliminate those noise components, a correlated double sampling(CDS) circuit is used before converting to digital. The output signal of each pixel is sampled twice, once for the reset level and once for the actual signal level. 2-3. Programmable Gain and Offset Control The user can controls the gain of individual color channel by the Programmable Gain Control Registers (pgcr, pgcg1, pgcg2, pgcb) and offset by Offset Control Registers (offsr, offsg1, offsg2, offsb). If the Color Channel Separation Mode is disabled (ccsm=0), pgcg1 and offsg1 change the gains and offsets for all channels. As increasing the gain control register, the ADC conversion input range decreases and the gain increases as following equation and the relative channel gain is shown in figure 3 Channel Gain = 128 / (128 - Programmable Gain Control Register Value[6:0]) R G1 R G1 G2 B G2 B R G1 R G1 G2 B G2 B
10 9 8 Relative Channel Gain
Channel Gain (dB)
45 40 35 30 25 20 15 10 5 0
7 6 5 4 3 2 1 0 16 32 48 64 80 96 112 128 Program m able Gain Control
0
16
32
48
64
80
96
112
128
Program m able Gain Control
Figure 3. Relative Channel Gain
2-4. Quadrisectional Global Gain Control The user can controls the global gain to change the gain for all color channels by the Global Gain Control Registers (sgg1, sgg2, sgg3, sgg4). The global gain control register is composed of four register groups and each register value decides the gain for each quarter section of output code level. At MCLK=12MHz and ggo_en=L, the global gain is determined by the following formula. Global Gain = (sgg[4:0]+1) / 16
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S5K3A1EA
1/3" SXGA CMOS IMAGE SENSOR
2.2 2
10
5 1.8 1.6 1.4 Global Gain (dB) -5 1.2 1 0.8 0.6 0.4 -20 0.2 0 0 4 8 12 16 20 24 28 32 Programmable Gain Control -25 0 4 8 12 16 20 24 28 32 Programmable Gain Control -15 0
Relative Global Gain
-10
Figure 4. Relative Global Gain The ADC gain is dependent on MCLK frequency (not on DCLK frequency) and ADC resolution. The default global gain is set for typical MCLK frequency (12MHz) and 10-bit ADC. When the frequency and ADC resolution is changed, the global gain should be changed to maintain the resulting gain over unity for assuring appropriate ADC conversion range. The recommended minimum global gain setting depending on ggo_en and adcres is shown in figure 5 and table 2.
30 28 26 24 Minimum Global Gain 22 20 18 16 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 MCLK Frequency (MHz)
10-bit ADC resolution 8-bit ADC resolution
Figure 5. Recommended Minimum Global Gain Control Value (ggo_en = L)
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1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
Table 2. Recommended Minimum Global Gain Setting (adcres = H) MCLK [MHz] 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 30 31 32 33 34 35 36 37 38 39 31 27 23 21 19 17 15 14 13 12 11 11 10 10 9 9 8 8 7 7 7 7 6 6 6 6 6 5 5 5 5 5 5 5 4 ggo_en = L Decimal Hexadecimal 1F 1B 17 15 13 11 0F 0E 0D 0C 0B 0B 0A 0A 09 09 08 08 07 07 07 07 06 06 06 06 06 05 05 05 05 05 05 05 04 31 29 27 25 23 22 21 20 19 18 17 16 15 15 14 14 13 13 13 13 12 11 11 11 10 10 10 10 9 ggo_en=H Decimal Hexadecimal 1F 1D 1B 19 17 16 15 14 13 12 11 10 0F 0F 0E 0E 0D 0D 0C 0D 0C 0B 0B 0B 0A 0A 0A 0A 09
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S5K3A1EA
1/3" SXGA CMOS IMAGE SENSOR
40 41 42 43 44 45 46 47 48
4 4 4 4 4 4 4 4 3
04 04 04 04 04 04 04 04 03
9 9 9 8 8 8 8 8 7
09 09 09 08 08 08 08 08 07
By appropriately programming these four register values, the different output resolution according to the signal can be achieved and the intra-scene dynamic range can be increased by 16 times. In another application, the sectional global gain control can be used as a rough gamma correction with four sectional linear approximation curve as shown in Figure 6.
sgg1
sgg2
sgg3
sgg4
ADC input signal
sgg1=11111b sgg2=01111b sgg3=00111b sgg4=00011b
sgg1=01111b sgg2=01111b sgg3=01111b sgg4=01111b
0
255
511
767
1023
ADC output code at 10-bit resolution
Figure 6. Quadrisectional Glabal Gain Control
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1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
3. Post Processing 3-1. Dark Level Compensation The dark level of Image sensor is defined as average output level without illumination. It includes pixel ouput caused by leakage current of the photodiodes and ADC offset. To compensate the dark level, the output level of optical black(OB) pixels can be a good reference value. When Auto Dark Level Compensation Register (dlcm) is set, the image sensor detects the OB pixel level at the start of every frame and anglog-to-digital conversion range is shifted to compensate the dark level for that frame. So, the resulting output data of that frame will be almost zero under dark state. If user wants the dark level which is not zero, the ADC Offset Register (adcoffs) can be used. The lower 7-bit value represent the offset value in outout code for compensation and the MSB is the sign to define whether the offset is positive (adcoffs[7]=0) or negative (adcoffs[7]=1). When not in auto dark level compensation mode, the adcoffs[7:0] act as a output code value to subtract the output image data. Please notify that the all the 8-bit data are used for an offset value without sign bit. ADLC formula : Dfinal = D(n) + adcoffs D(n) = (feed_gain_a)*(OB(n) + OB(n-1)) + (feed_gain_b)*D(n-1) 3-2. Bad Pixel Replacement When the Bad Pixel Replacement Register (bprm) is enabled, the image sensor check that the image data is less or greater than horizontally neighboring pixels in same color channel by the preset threshold value (pthresh). If satisfied, the output of the pixel is replaced by the averaged value of the neighboring two pixels. The detectable defected pixels are rare and the bad pixel replacement action can remove defected image effectively. But it reduces the line resolution in horizontal direction. 4. I2C Serial Interface The I2C is an industry standard serial interface. The I2C contains a serial two-wire half duplex interface that features bi-directional operation, master or slave mode. The general SDA and SCL are the bi-directional data and clock pins, respectively. These pins are open-drain type ports and will require a pull-up resistor to VDD. The image sensor operates in salve mode only and the SCL is input only. The I2C bus interface is composed of following parts : START signal, 7-bit slave device address (0010001b) transmission followed by a read/write bit, an acknowledgement signal from the slave, 8-bit data transfer followed by an acknowledgement signal and STOP signal. The SDA bus line may only be changed while SCL is low. The data on the SDA bus line is valid on the high-to-low transition of SCL.
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S5K3A1EA
1/3" SXGA CMOS IMAGE SENSOR
SCL SDA "0"
Start
"0"
"1"
"0"
"0"
"0"
"1"
Write Ack
D 7
D 6
D
D
D
D
D
D
Ack
I2C Bus Address
I2C Register Address
SCL SDA D 7 D 6 D D D D D D
Ack Stop
Data to Write
Figure 7. I2C Bus Write Cycle
SCL SDA "0"
Start
"0"
"1"
"0"
"0"
"0"
"1"
Write Ack
D 7
D 6
D
D
D
D
D
D
Ack
X
I2C Bus Address
I2C Register Address
SCL SDA "0"
Re-Start
"0"
"1"
"0"
"0"
"0"
"1"
Read Ack
D 7
D 6
D
D
D
D
D
D
Ack Stop
I2C Bus Address
Data to be Read
Figure 8. I2C Bus Read Cycle
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1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
TIMING CHART
VERTICAL TIMING DIAGRAM Continuous Frame Capture Mode ( Default Case )
1 frame = wrd + vblank ( 1125 rows ) VSYNC vswd (1row) 10 rows = vsend_ofset HSYNC DATA wrp(14th row)
wrd (1024 rows)
vblank (101 rows)
( Delayed Vertical Sync Case)
1 frame = wrd + vblank ( 1125 rows ) VSYNC 10 rows = vsend_ofset HSYNC DATA wrp(14th row) 2rows 2rows vsstrt vswd
( Vertical Data Valid Mode Case) vsdisp=1
VSYNC 10 rows = vsend_ofset HSYNC (hsdisp=0) HSYNC (hsdisp=1) DATA wrp(14th row) wrd (1024 rows) vblank (101 rows)
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S5K3A1EA
1/3" SXGA CMOS IMAGE SENSOR
VERTICAL TIMING DIAGRAM (continued) ( Short OB Line & Fixed Vertical Sync mode) isp_sel = 1& fix_vs = 1
1 frame = wrd + vblank ( 1125 rows ) VSYNC Normal frame output vswd (1row) 4 rows = vsend_ofset HSYNC
DATA wrp(14th row) wrd (1024 rows) vblank (101 rows) wrp(14th row)
( Short OB Line & Normal Sync mode) isp_sel = 1, vsstrt = 1117d, vswd = 2d
1 frame = wrd + vblank ( 1125 rows ) DEFAULT VSYNC VSYNC vswd (2rows) 4 rows = vsend_ofset HSYNC DATA wrp(14th row) wrd (1024 rows) vblank (101 rows) wrp(14th row) Normal frame output vsstrt (1117 rows)
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1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
VERTICAL TIMING DIAGRAM (continued) Single Frame Capture Mode ( Rolling Shutter Case, sfcen = 1 & roll_mod = 1 )
Normal frame output STRB Integration time for 1st readout row Integration time for 2nd readout row Integration time for 3rd readout row Integration time for 4th readout row
VSYNC
sint X (1 row time) = integration time
HSYNC DATA wrp(14th row) wrd (1024 rows)
( Mechanical Shutter Case, sfcen=1 & mech_mod = 1 )
Normal frame output STRB
Integration time for all pixels VSYNC
HSYNC
DATA External Mechanical Shutter Can be opened
wrp(14th row) wrd (1024 rows) Should be closed
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S5K3A1EA
1/3" SXGA CMOS IMAGE SENSOR
( Global Shutter Case, sfcen=1 & global_mod = 1 )
Normal frame output STRB Integration time for all pixels VSYNC
HSYNC
DATA wrp(14th row) wrd (1024 rows)
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1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
HORIZONTAL TIMING DIAGRAM ( Default Case )
VSYNC 1 row = wcw + hblank ( 1422 columns )
HSYNC hswd DCLK 10 DCLK
DATA wcp ( 14th column) wcw ( 1280 columns ) hblank ( 142 columns )
( Delayed Horizontal Sync Case )
1 row = wcw + hblank VSYNC HSYNC hsstrt DCLK hswd
DATA wcw
( Horizontal Data Valid Mode Case ) hsdisp=1
VSYNC HSYNC
DCLK
DATA wcw hblank
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S5K3A1EA
1/3" SXGA CMOS IMAGE SENSOR
PACKAGE DIMENSION 48pin CLCC (unit = mm)
6 7 14.22SQ +0.30/-0.13 1 48 43 42
TOP VIEW
Center of Image Area (X=+0.088 0.15, Y=0.002 0.15 from package center) Max. Chip Rotation = 1.5 degree Max. Chip Tilt = 0.05mm 18 19 30 31
Glass
SIDE VIEW
0.55 0.05 1.65 0.18
11.176 0.13 1.016 0.08 48 1
BOTTOM VIEW
R 0.15 4 Corners
0.51 0.08
1.016 0.18
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