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PI1004-1 PI1004-2
Programmable Point-of-Load Controller with 6-bit VID
Description
The PI1004 IC combines a Voltage Identification Digital Input (VID) controlled reference with control and supervisory functions to accurately set the regulator output voltage at the point of load, for isolated and CPU DC-DC converters in desktop and server applications. The PI1004 feature set is intended to be used in conjunction with a variety of power architectures, including Factorized Power Architecture (FPA), to provide CPU power in accordance with Intel(R) VR10.X requirements. The feature set includes a precision error amplifier for remote differential sensing of the output voltage, a six bit programmable VID reference voltage output with 12.5 mV resolution, and flexible adaptive voltage positioning. The regulation voltage can also be shifted below the VID range with a programmable offset current. The controller includes an over-voltage indicator output, an open collector power-good output, under-voltage lockout and an externally programmable soft start. The PI1004 is available in two options; PI1004-1: Programmable VID offset current and no OVP output. The VID offset current is used to create an offset to the DAC output. PI1004-2: OVP output and no VID offset.
Features
* 0.5% Typical initial output voltage accuracy * Remote differential output voltage sense * 6 Bit DAC, with 12.5 mV resolution * 5 V to 12 V Operation * Power good output with blanking * Programmable adaptive voltage positioning (AVP) * Over voltage protection (OVP) output or programmable VID offset * Programmable soft start * Optimized for VRM/VRD 10.X specifications * 20 MHz Gain bandwidth amplifier * Enable input
Applications
* Supports FPA * Intel(R) VR10.X CPU Power * Workstation CPU Power * Isolated DC-DC Converters
Package
* 24-Lead (4mm x 4mm) QFN
Typical Circuit
PRM-AL VTM
Vin
ZVS
Vf
++ -K -
PI1004
V*I
Vout
Vref
+ -
VID DAC
} D0-D5
Figure 1 - Basic connection in FPA application. Picor Corporation * picorpower.com PI1004 Data Sheet Rev. 2.5 Page 1 of 16
Pin Description
PIN # Pin Name
1- 6 VID[0:5]
Description
Voltage identification digital inputs. The VID inputs program the reference voltage on the REFOUT pin. Tying all VID pins high is treated as a fault and sets the fault latch. To hardwire the VID code, the inputs may be connected to Vcc or SGND as applicable. See Table 1 for VID codes. Power-good open-collector output. This pin is an open circuit when (REFIN-230 mV) VO (REFIN+160 mV) and the input bus voltage is not in a UVLO condition. When VO is outside the VO window, (REFIN230 mV ) < VO < (REFIN+160 mV) or the input bus voltage is in a UVLO condition, or if the ENABLE is low, the PWRGD output is low. PI1004-1 only. Provides a programmable VID offset current. A current equal to the current out of the OFFSET pin is added to IAVP to provide a fixed negative offset. To program the offset connect a resistor between OFFSET and SGND. The current is nominally equal to 0.25 V / ROFFSET. Not used tie to Vcc. PI1004-2 only. Over-voltage protection signal, TTL output. When VO (REFIN+220 mV) and the input bus voltage is not in a UVLO condition and ENABLE is high, OVP is high. When VO < (REFIN+220 mV) or the input bus voltage is in a UVLO condition, or ENABLE is low, OVP is low. Logic input control of biasing. If ENABLE = low the PI1004 is disabled and quiescent current is reduced to <400 uA. If ENABLE = high the PI1004 is enabled and the part operates normally if Vcc > UVLO. Soft start programming terminal. The error amp non-inverting input (EAIP) is clamped below the level of the SS pin. An internal 5uA charging current is provided to program soft start with an external capacitor. Soft start pin is discharged and held low with ENABLE low, UVLO, or VID=x11111. To control soft-start connect a capacitor between the SS pin and SGND. Output voltage positive sense signal used for the power good and over-voltage protection circuits. Connect directly to the output or if feedback divider is employed, connect to the output through a voltage divider with the same ratio as the feedback divider. Load current negative sense terminal. Connect ISN to the negative side of the sense resistor. If AVP is not used, tie ISN to SGND. Load current positive sense terminal. Connect ISP to the positive side of the sense resistor to detect load current for AVP. If AVP is not used, tie ISP to SGND. Adaptive voltage positioning gain resistor connection. The sink current from the IAVP pin is: IAVP = 4*[V(ISP)-V(ISN)]/RG. If AVP is not used, tie RG to Vcc. Adaptive voltage positioning sink current. This pin sinks current proportional to the load. Connect to the EAIP pin with an AVP resistor (RAVP) tied from EAIP to REFOUT. The regulator output voltage will drop with increasing load. If AVP is not used, connect IAVP to Vcc. Reference input voltage for the over-voltage protection and power good indicators. Normally REFIN is tied to REFOUT. Non-inverting input to the error amplifier. If AVP and offset are not used, connect EAIP to REFOUT. To use AVP connect directly to IAVP and to REFOUT through a resistor. Inverting input to the error amplifier. Connect EAIN to the positive remote output voltage sense point through the feedback network. Run in parallel to the SGND connection to avoid noise pick-up. Error amplifier output terminal. Reference output voltage as defined by the VID codes in Table 1. The reference is capable of sourcing up to 1 mA of current. In a typical CPU application REFOUT is connected to REFIN to set the thresholds for Power Good and to EAIP through a resistor to enable Adaptive Voltage Positioning. Internal circuit supply. Bypass Vcc to SGND with a 0.1 F capacitor. Internal substrate connection and negative output voltage sense terminal. Connect to the negative remote output voltage sense point and run in parallel with the positive sense line to avoid noise pick-up. No connect. Post package programming pin.
7
PWRGD
8
OFFSET
8
OVP
9 10
ENABLE SS
11
VO
12 13 14 15
ISN ISP RG IAVP
16 17 18 19 20
REFIN EAIP EAIN EAO REFOUT
21 22
VCC SGND
23,24
NC
Picor Corporation * picorpower.com
PI1004 Data Sheet Rev. 2.5 Page 2 of 16
Absolute Maximum Ratings
These are stress ratings only and functional operation of the device at these ratings is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Vcc, EAO........................................-0.3 V to 16 V / 20 mA OVP ...............................................-0.3 V to 16 V / 10 mA VID5:0, ENABLE, SS, ISN, ISP, RG, IAVP, EAIP, EAIN, REFOUT, OFFSET ...................-0.3 V to 16 V / 1 mA PWRGD, ......................................-0.3 V to 5.5 V / 10 mA REFIN, VO, .....................................-0.3 V to 5.5 V / 1 mA SGND.......................................................................20 mA Storage Temperature .............................-65 C to 150 C ESD Sensitivity Class Rating.........................................1 C Soldering Temp. IR or Convection (20 sec) 3 pg 15 ....250 C
Package Connection Diagram
24-Lead (4mm x 4mm)
QFN
* Pin 8 has a different function for each PI1004 version: PI1004-1 pin 8 is OFFSET PI1004-2 pin 8 is OVP
Electrical Specifications
Unless otherwise specified: -40C < Tj < 125 C, 4.5V < VCC < 13.2V PARAMETER
SUPPLY SYSTEM Operating current Shutdown current Input supply range (Vcc) UV start threshold (Vcc) UV stop threshold (Vcc) UV hysteresis VID REFERENCE System set point accuracy (See Table 1 for nominal voltage.) Line regulation REFOUT drive capability Input logic low Input logic high VID input bias current ERROR AMPLIFIER Open loop gain Unity gain bandwidth Output slew rate Error amp source current Error amp sink current Input bias current Input offset current Input offset voltage Common mode input range Output voltage range CMRR PSRR
Picor Corporation * picorpower.com
MIN
TYP
5 160
MAX
7 400 13.2 4.5 4.4 200
UNIT
mA A V V V mV
CONDITIONS
Enable > 0.8 V, VCC=9 V Enable < 0.3 V
4.5 4.1 4.0 30 4.3 4.2 130
-0.8 -0.05
+0.8 0.05 1 0.4
% %/V mA V V A dB MHz V/sec mA A
0C TA 70C, VCC=8.5 V For all VID codes, measured at EAO in unity gain 0C TA 70C
0.8 0.1 80 110 20 14 4 250 9 500 0.6 60 -3 -0.05 0.5 80 80 3 Vcc - 2 Vcc -1.6 2
EAIP = 1.25 V 30 pF load
A nA mV V V dB dB
PI1004 Data Sheet Rev. 2.5 Page 3 of 16
Unity Gain. EAIP = 1.25 V
Electrical Specifications (continued)
PARAMETER
POWER GOOD OUTPUT (see Note1) Under-voltage trip threshold Under-voltage clear threshold Under-voltage hysteresis Over-voltage trip threshold Over-voltage clear threshold Over-voltage hysteresis Output low PWRGD blanking TIME ENABLE INPUT Logic low threshold Logic high threshold Open circuit voltage Input pull-up current OVP CIRCUIT (PI1004-2 only) (see Note1) Over-voltage trip threshold Over-voltage clear threshold Over-voltage hysteresis OVP logic high OVP logic high current OVP logic low OVP response time VO pin input current REFIN pin input current SOFT START CIRCUIT SS charge current SS discharge current SS clamp voltage SS reset voltage SS discharge voltage AVP CIRCUIT Common mode input voltage range Differential input voltage range AVP current sink range IAVP transconductance IAVP headroom Input bias current, ISP, ISN Programmable VID OFFSET (PI1004-1 only) OFFSET output voltage OFFSET to IAVP headroom 240 0.2 250 260 mV V ROFFSET = 10 k 0.97 0.2 5 1.00 -0.05 0 0.4 135 200 1.03 V mV A mS V A RG=4 k, ISP = 135 mV ISN = 0V 3 0.2 2.3 0.2 5 0.7 2.6 0.25 2.9 0.3 0.1 7 A mA V V V 0C TA 70C 0.5 0.25 0.25 0.6 0.6 180 120 40 2.5 2 220 150 70 3.5 4.5 0.4 250 180 100 4.5 mV mV mV V mA V sec A A Iovp = 0.5 mA 0C TA 70C 0C TA 70C 0C TA 70C Iovp = -2 mA 2 0.8 1.8 0.3 V V V A 0C TA 70C 50 100
MIN
-280 -185 -100 125 75 35
TYP
-230 -150 - 80 160 110 50
MAX
-185 -100 -50 +185 +135 80 0.4 300
UNITS
mV mV mV mV mV mV V sec
CONDITIONS
0C TA 70C 0C TA 70C 0C TA 70C 0C TA 70C 0C TA 70C 0C TA 70C IPWRGD = 4 mA (Enabled) IPWRGD = 250 A (Disabled)
Note 1: Power good and overvoltage inputs are referenced to VO-REFIN
Picor Corporation * picorpower.com
PI1004 Data Sheet Rev. 2.5 Page 4 of 16
VID Pins
(0 = low, 1 = high)
VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID4 VID3 VID2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 VID0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 (EAO)
1
VID Pins
(0 = low, 1 = high)
VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 VID2 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 (EAO)
1
0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 OFF OFF
2
1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 1.5500 1.5625 1.5750 1.5875 1.6000
2
1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.2000
Table 1. Voltage Identification Table 1 NOTES: 1. (EAO) is equal to the maximum output voltage specified by the Intel design guide, Voltage Regulator-Down (VRD) 10.0, February 2004. 2. EAO is held low during VID OFF codes.
Picor Corporation * picorpower.com
PI1004 Data Sheet Rev. 2.5 Page 5 of 16
Functional Description
The block diagram in Figure 2 shows that the PI1004-1 has a programmed VID offset function and no OVP function. Figure 3 shows the PI1004-2 with the OVP function in place of the VID offset. Unless otherwise stated please refer to Figure 2 and application diagram Figure 4a for the following description. Voltage identification and Reference Out The REFOUT output pin provides a scaled temperature stable reference voltage (see temperature curves in figure 15) that is incremented by the VID input state decoding and DAC (digital to analog converter) function. The 6 bit DAC provides a minimum increment resolution of 12.5mV. The VR10.X VID code accuracy shown in Table 1 is measured at the output of the error amp in the unity gain buffer configuration. REFOUT will be determined by VID[5:0] according to the Intel VR10.X Voltage Identification Table. In a typical CPU application using AVP (Adaptive Voltage Positioning) REFIN is tied directly to REFOUT and EAIP is tied to REFOUT through a resistor for AVP adjustment. VID = x1111 is treated as a fault and sets the Fault Latch function that will be explained further in the other sections. Current Sensing and AVP Pins ISN and ISP form the input to a differential voltage sense amplifier that can be used for current sensing and adaptive voltage positioning (AVP). The amplifier has a narrow common mode input range for ground reference voltages. The AVP amplifier has a fixed gain of 4 to amplify the voltage across a sense resistor that is representative of the load current. The output voltage of the amplifier is fed to a unity gain buffer and impressed across the external RG resistor converting the voltage to a current that is reflected as a sink current at the IAVP pin 15. The PI-1004-1 has a second voltage to current converter to create the OFFSET function with a fixed reference voltage of 250mV that is impressed across an external ROFFSET resistor. This voltage to current conversion reflects a fixed sink current at the IAVP pin. The sum of these two currents flows through the external resistor, RAVP when connected as shown in figure 4a completing the adaptive and offset functions. The control error amplifier input voltage will be dependent on the reference determined by the VID input state, minus any programmed offset voltage, minus the AVP correction for load setting the slope of the load line. The IAVP pin is set up to provide a current proportional to the load current. Various load lines can be selected by choosing values of the output current shunt resistor, RG and the resistor between REFOUT and EAIP (RAVP) for the proper droop. The value of the current shunt should be chosen for a voltage drop of 135mV or slightly lower at full load. Differential Output Voltage Sense The core control error amplifier has two non-inverting inputs to accommodate a soft start feature. With the proper non-faulted conditions the soft-start charging current of 5uA will be sourced out of the SS pin to an external capacitor. This feature provides the ability to control the rate of rise in the output voltage up to the point of regulation. The fault conditions are defined in the fault circuitry section and listed in Table 2. If a fault condition exits the internal sink transistor will hold the SS pin to the signal ground potential. Recovery from any of the fault conditions will result in a full soft-start interval. The lower of the two non-inverting inputs of the error amplifier will dominate. When all faults are cleared the SS input provides the dominant ramping input voltage until it exceeds the EAIP reference. The SS input continues to ramp to the soft-start clamp voltage while the EAIP
INPUTS
ENABLE L H H H H L L UVLO X H VID[5:0] X X VID Valid VID Valid X11111 OVP L L Active Active Active PWRGD L
(Limited drive)
OUTPUTS
REFOUT L VID VID VID VID Active L H L EAO L L SS L L
L Active Active Active
ENABLE Low = Off
UVLO High = VCC is low
OVP High = Fault
PWRGD Low = Fault
VID = See VID Table 1
Table 2. I/O Functional States Picor Corporation * picorpower.com PI1004 Data Sheet Rev. 2.5 Page 6 of 16
Applications Description
becomes the control reference. The amplifier EAIN inverting input and the EAO output pin can be configured as a unity gain follower or as an inverting amplifier with the proper feedback components to set the close loop gain and frequency response of the voltage control loop. Differential sensing is accomplished by referencing the entire PI1004 to the negative return of the load (typically CPUVSS). The SGND pin serves a dual purpose of returning the PI1004 VCC current and sensing the low side of the load. The internal reference "rides" on SGND to compensate for voltage changes at the load. Special care must be taken in the layout to avoid noise pick-up or offsets due to ground loop currents. Fault Circuitry There are three input conditions that will set the fault latch determined by ENABLE, VIDOFF or UVLO states as shown in Table 2. Any fault will clamp the non-inverting error amp input (EAIP) and SS pin to SGND. The fault latch is reset when the SS pin drops below 0.25 V AND all faults are cleared at the Set dominant latch input. Power Good and Over-Voltage Protection The PWRGD and OVP (OVP in PI1004-2 only) pins provide output signals when the output voltage exceeds internally set thresholds. The inputs to the PWRGD and OVP comparators are referenced to REFIN and VO. The PWRGD and OVP signals are outputs for system use and do not trigger an internal fault. Programmable VID Offset REFOUT is set to the VR10 maximum output voltage according to Table 1. For PI1004-1, the no-load VID output voltage can be reduced to accommodate various load line tolerance bands with the OFFSET function. Once the value of RAVP has been chosen for the desired load line, ROFFSET can be selected for the required no-load offset. Refer to Figure 4d to determine resistor values setting the AVP and Offset parameters. Figures 5-10 demonstrate some of the dynamic performance of these functions such as AVP response time, REFOUT response to VID change, VID blanking interval, error amplifier unity gain slew rate and soft-start response to stepped Vcc in that order. Figures 11-14 demonstrate typical DAC error performance at specific temperatures and Figure 15 demonstrates the VID performance from -55 to 125 degrees Celsius at VID=1.2V. The PI1004 products were developed to enable Vicor's FPA (Factorized Power Architecture) to meet Intel's requirements defined in VRM/VRD 10.X specifications. A simplified schematic representation of this topology is shown in Figure 4a. DC Performance data of this configuration using the PI1004-1 is shown in Figures 16-17 and dynamic performance is shown in Figures 18a-g, 19a-b and 20. In addition to FPA applications, independent functions of the PI1004 can be used in different combinations as building blocks in control applications. The PI-1004 can be used as a VID controlled reference in an embedded power converter circuit. The PI1004 error amp can be configured as a unity gain buffer to provide the VRD capable reference to the non-inverting input to the control amp. If AVP is required, a method for sensing the load current would need to be implemented. In isolated applications as shown in Figure 4b, the reference and error amplifier might replace a TL431 (Vcc power is required for the PI1004) while the PWRGD, OVP and AVP blocks replace a quad comparator. The PI1004 is a candidate for any application that uses a reference and several amplifiers or comparators especially where digital or hard-wire setting of voltages can be accommodated. The IC can be used as a programmable reference control for a converter or power supply with a positive reference based trim configuration as shown in Figure 4c. For these applications a programmable output voltage and overvoltage features can be created using the error amp as a buffer creating a VR10 reference for the SC/trim input of the converter. Care must be taken not to exceed the amplifier output sink and source current capabilities and to be compatible with the converter reference pin. The AVP block of circuits can be used to create two independent voltage to current converters providing a sink current that is the sum of the two at the IAVP pin. Again consideration of the specified range for these functions is required. Finally the Power Good block can be used as basic comparators for voltage monitoring with the addition of an independent output on the OVP pin in the PI1004-2 An additional bit of resolution can be added to the DAC by using the circuit shown in Figure 4d with proper sequencing by the microprocessor 6.25 mV increments are possible.
Picor Corporation * picorpower.com
PI1004 Data Sheet Rev. 2.5 Page 7 of 16
Block Diagrams
Figure 2 - PI1004-1 Programmable VID offset current
Figure 3 - PI1004-2 Over voltage protection output Picor Corporation * picorpower.com PI1004 Data Sheet Rev. 2.5 Page 8 of 16
Application Diagrams
From CPU
{
1 2 3
VID0 VID1 VID2 4 VID3 5 VID4 6 VID5
7 9
REFOUT REFIN
20 16 17 15
RAVP
PI1004-1
EAIP IAVP
Vcc PWRGD Out Enable Input
PWRGD ENABLE ISN
12
ISP
13
EAO
19
EAIN
18
VO
11
VCC
21
SGND
22
OFFSET
8
SS
10
RG
14
RG ROFFSET
VC PC TM IL NC PR
+In
+In
PRM-AL
VH SC SG OS NC CD
+In
+Out
-Out
+Out
C1
TM VC PC
VTM
+Out
CPU
Ceramic Bypass
-Out
-In
-In
-Out
-In
C1= Ceramic Cap
Figure 4a - Simplified FPA CPU VRD10.0 power application.
NC
NC
VID Signal or Hard Wired VID Code
Vcc Bias Power Good
PWRGD
VCC
DC-DC CONVERTER
6 VID5
PI1004-2
EAIP 17 IAVP 15
VO
7 PWRGD 8 OVP 9 ENABLE SGND EAIN EAO ISN ISP VO SS
SC/Trim
18
EAIN
VID3 4 VID4 5
RG 14 VCC 21 Vcc Bias
19 EAO
PI1004-2
VID5 6
OVP Signal
9
ENABLE REFOUT REFIN SGND EAIP
OVP 8
19 Disable Signal from primary side Voltage Feedback Signal
18
11
12 13 22 10 Out-
22 Sense-
10
SS
20
16
17
Sec Out-
Pri
Vout-
Figure 4b - Embedded Isolated Power Converter Application using the PI1004-2. Picor Corporation * picorpower.com
Figure 4c - Power Brick or Converter Application using the PI1004-2. PI1004 Data Sheet Rev. 2.5 Page 9 of 16
{
{
1 VID0 2 VID1 3 VID2 4 VID3 5 VID4
24
23 REFOUT 20 REFIN 16
Vout+
Load Sense+ Load
PWRGD 21 11 7 VID0 1 VID1 2 VID2 3
Sense+
VID Signal or Hard Wired VID Code
Load SenseLoad
Note: Inverted forced Beta of Q2
24 NC 21 23 NC 19 18 20
Vcc
VCC
EAO EAIN REFOUT
I = IE 0.01 IB
Vou t
VID Signal or Hard Wired VID Code
{
VID Pull-up VID_6.25mV R1 R2 1mA RBit 7 * Inverted Q1 Q2 2N2222 Roffset
1 2 3
VID0 VID1 VID2
4 VID3 5 VID4 6 VID5
PI1004-1
EAIP IAVP ISP 17 15 13 12 14
Example
RAVP
10A =1mA IEQ2 = 10A IB = 0.01
8
OFFSET
ISN RG REFIN SGND VO
}
RG
Rsense
R2 =
VIDpullup - 0.6V IB
RBit 7 R AVP . 250 6.25
10 C2
SS
11
16
22
Out -
R1 = 10 * R2
Figure 4d - Application circuit using the AVP and Offset features of the PI1004-1 plus optional 7 Bit resolution.
Component value selection for AVP, Offset and 7 Bit resolution a. Select AVP droop voltage at full load b. Select IAVP droop current at full load (200A max) c. Select current sense input voltage at maximum load (VISP - VISN) d. Select VOffset voltage level to center DAC voltage e. Add VID6 (seven bit) resolution Q1, Q2 circuit
Example VDROOP = 100mV AVP = 100A VSENSE = 120mV VOFFSET = 25mV
1. RAVP =
Vdroop 100mV = = 1K IAVP 100A
2. RG =
4*VSense 4*120mV = = 4.8K 100A IAVP
3. ROffset =
250mV*RAVP 250mV*1K = = 10K VOffset 25mV 250mV 40K
4. RBit7 =
250mV 6.25mV
* RAVP
=
250mV 6.25mV
* 1K
= 40K
5.
IEQ2 =
250mV RBit7
=
= 6.25A
See R1 and R2 Note above.
Picor Corporation * picorpower.com
PI1004 Data Sheet Rev. 2.5 Page 10 of 16
Time: 400 ns/div Figure 5 - Error Amp Output (EAO) and Adaptive Voltage Positioning (AVP) response to negative step. Error amp unity gain. ISN grounded, RAVP=1 K, RG=4 K CH1: ISP 200 mV/div CH3: EAO 200 mV/div CH2: RG 200 mV/div CH4: EAIP 200 mV/div
Time: 400 ns/div Figure 6 - Error Amp Output (EAO) and Adaptive Voltage Positioning (AVP) response to positive step. Error amp unity gain. ISN grounded, RAVP=1 K, RG=4 K CH1: ISP 200 mV/div CH3: EAO 200 mV/div CH2: RG 200 mV/div CH4: EAIP 200 mV/div
Time: 20s/div Figure 7 - REFOUT settling time CH1: VID4, 5 V/div CH2: REFOUT; 100 mV/div Figure 8 - REFOUT blanking time CH1: VID5, 5 V/div CH2: REFOUT; 100 mV/div
Time: 1.0s/div
Time: 40 ns/div Figure 9 - Unity Gain Error Amp slew rate CH1: EAIP; 500 mV/div CH2: EAO; 500 mV/div
Time: 40 s/div Figure 10 - Startup, Fast Vcc RAMP CH1: VCC; 2 V/div CH3: PWRGD; 2 V/div CH2: EAO; 1 V/div CH4: SS; 1 V/div
Picor Corporation * picorpower.com
PI1004 Data Sheet Rev. 2.5 Page 11 of 16
0.8 0.6 0.4
0.8 0.6 0.4
DAC Error (%)
0.2 0.0 -0.2 -0.4 -0.6 -0.8 0.8375 1.0875 1.3375 1.5875
DAC Error (%)
0.2 0.0 -0.2 -0.4 -0.6 -0.8 0.8375 1.0875 1.3375 1.5875
Ideal DAC Voltage (Volts) : Vcc=8.5V
Ideal DAC Voltage (Volts) : Vcc=8.5V
Figure 11 - DAC Error at 0C
Figure 12 - DAC Error at 30C
0.8 0.6 0.4
0.8 0.6 0.4
DAC Error (%)
0.2 0.0 -0.2 -0.4 -0.6 -0.8 0.8375 1.0875 1.3375 1.5875
DAC Error (%)
0.2 0.0 -0.2 -0.4 -0.6 -0.8 0.8375 1.0875 1.3375 1.5875
Ideal DAC Voltage (Volts) : Vcc=8.5V
Ideal DAC Voltage (Volts) : Vcc=8.5V
Figure 13 - DAC Error at 70C
Figure 14 - DAC Error at 125C
0.2 0.1
VID % Change
0 -0.1 -0.2 -0.3 -0.4 -60 -10 40 90 140
Junction Temperature (C)
Figure 15 - Typical VID temperature performance @ VID = 111010 = 1.2 V
Picor Corporation * picorpower.com
PI1004 Data Sheet Rev. 2.5 Page 12 of 16
Application Measurements Using Fig. 4a
1.45 1.40
1.45 1.40
Vo_max [V] Vo_min [V] LL NL HL
Output Voltage (V)
1.35 1.30 1.25 1.20
Output Voltage (V)
1.35 1.30 1.25 1.20
Vo_max [V] Vo_min [V] LL NL HL
0
50
100
150
0
50
100
150
Output current (A)
Output current (A)
Figure 16 - Load Line Performance; Vin: 10.2/12.0/13.8 V, Vout: 1.4 V, Ta: Room temp
Figure 17 - Load Line Performance; Vin: 10.2/12.0/13.8 V, Vout: 1.4 V, Tj: 100C
Figure 18a - Transient Load Response 5 A-95 A-5 A VID=0.8375 Cload=240 F
Figure 18b - Transient Load Response 95 A-5 A VID=0.8375 Cload=240 F
Figure 18c - Transient Load Response 5 A-95 A-5 A VID=1.0 Cload=240 F
Figure 18d - Transient Load Response 95 A-5 A VID=1.0 Cload=240 F
Picor Corporation * picorpower.com
PI1004 Data Sheet Rev. 2.5 Page 13 of 16
Figure 18e - Transient Load Response 5 A-95 A-5 A VID=1.6 V Cload=240 F
Figure 18f - Transient Load Response 95 A-5 A VID=1.6 V Cload=240 F
Figure 19a - Monotonic Full Range DAC Incrementing VID=0.8375 V to VID=1.6 V
Figure 19b - Monotonic Full Range DAC Decrementing VID=1.6 V to VID=0.8375 V
12.0 10.0
Output Voltage Ripple (mVp-p)
8.0 6.0 4.0 2.0 0.0 0 50 100 150
LL NL HL Spec max
Output Current (A)
Figure 20 - Output voltage ripple vs. output current; Vin: 10.2/12.0/13.8 V, Vout: 1.0 V, Ta: Room temp.
Picor Corporation * picorpower.com
PI1004 Data Sheet Rev. 2.5 Page 14 of 16
Package Description
Layout Guidelines
Good layout technique is required for systems that combine sensitive amplifiers and switching converters. Extra care must be taken to provide high frequency decoupling and to avoid introducing noise at sensitive nodes. * The capacitors for VCC decoupling and Soft Start should provide low impedance paths to each pin and be referenced to SGND close to the PI1004. * The connections from load VSS to SGND and the load VCC to EAIP form an output voltage sense pair and should be routed in parallel to avoid noise pick-up. If the layout allows PI1004 return current to flow through the load VSS to SGND connection, trace resistance must be considered to avoid an excessive offset voltage within the trace.
A3 Side View A1
E
1 2 D
PICOR 1004-X (LOT#) DATE CODE
Top View
0.10mm(.004") 0.08mm(.003") A
* The PI1004 EA integrator capacitor should be routed in a short loop to minimize noise pick-up. * RG and ROFFSET should be tied to SGND near the PI1004 to avoid noise pickup.
D2 D2/2 MILLIMETERS INCHES
DIM A A1 A3
E2 2 1 E2/2
MIN 0.80 0.00 -0.20 2.70 2.70 0.30
NOM 0.85 0.02 0.20ref 0.25 4.00 2.80 4.00 2.80 0.50 0.40
MAX .90 0.05 -0.30 2.90 2.90 0.50
MIN .031 .000 -.008 .106 .106 .012
NOM .033 .001 .008 ref .010 .157 .110 .157 .110 .020 .016
MAX .035 .002 -.012 .114 .114 .020
NXb D D2 E E2
NXL e Bottom View NXb
e NXL
Controlling Dimensions: Millimeters
Thermal Resistance Ratings
PARAMETER
Maximum Junction-to-Ambient 2 Maximum Junction-to-Case
SYMBOL
JA JC
TYPICAL
46 2
UNIT
C/W C/W
Ordering Information
PART NUMBER
PI1004-1-QAHG PI1004-2-QAHG
PACKAGE
24 lead (4mm x 4mm) QFN 24 lead (4mm x 4mm) QFN
BRANDING
1004-1 1004-2
TEMP. RANGE
-40C to 125C -40C to 125C
TRANSPORT MEDIA
T&R T&R
Note 2: In accordance with JEDEC JESD 51-5 Note 3: This product is MSL classified at the peak soldering reflow temperature listed in the Absolute Maximum Rating section to meet the lead free requirements of the joint IPC(R) and JEDEC(R) standard J-STD-020C.
Picor Corporation * picorpower.com PI1004 Data Sheet Rev. 2.5 Page 15 of 16
Vicor's comprehensive line of power solutions includes high-density AC-DC & DC-DC modules and accessory components, fully configurable AC-DC & DC-DC power supplies, and complete custom power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. No license is granted by implication or otherwise under any patent or patent rights of Vicor. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. All sales are subject to Vicor's Terms and Conditions of Sale, which are available upon request.
Specifications are subject to change without notice.
Vicor Corporation 25 Frontage Road, Andover, MA, USA 01810 Tel: 800-735-6200 Fax: 978-475-6715 Email Vicor Express: vicorexp@vicr.com Technical Support: apps@vicr.com
Picor Corporation * picorpower.com * PI1004 Data Sheet
P/N 28955
Rev. 2.5
10/05

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