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| Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated FEATURES * Repetitive Avalanche Rated * Fast switching * Stable off-state characteristics * High thermal cycling performance * Isolated package PHX6N50E SYMBOL d QUICK REFERENCE DATA VDSS = 500 V g ID = 3.1 A RDS(ON) 1.5 s GENERAL DESCRIPTION N-channel, enhancement mode field-effect power transistor, intended for use in off-line switched mode power supplies, T.V. and computer monitor power supplies, d.c. to d.c. converters, motor control circuits and general purpose switching applications. The PHX6N50E is supplied in the SOT186A full pack, isolated package. PINNING PIN 1 2 3 case gate drain source isolated DESCRIPTION SOT186A case 123 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total dissipation Operating junction and storage temperature range CONDITIONS Tj = 25 C to 150C Tj = 25 C to 150C; RGS = 20 k Ths = 25 C; VGS = 10 V Ths = 100 C; VGS = 10 V Ths = 25 C Ths = 25 C MIN. - 55 MAX. 500 500 30 3.1 2 24 35 150 UNIT V V V A A A W C AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy CONDITIONS MIN. MAX. 287 UNIT mJ Unclamped inductive load, IAS = 4.2 A; tp = 0.21 ms; Tj prior to avalanche = 25C; VDD 50 V; RGS = 50 ; VGS = 10 V; refer to fig:17 Repetitive avalanche energy1 IAR = 5.9 A; tp = 2.5 s; Tj prior to avalanche = 25C; RGS = 50 ; VGS = 10 V; refer to fig:18 Repetitive and non-repetitive avalanche current EAR IAS, IAR - 10 5.9 mJ A 1 pulse width and repetition rate limited by Tj max. December 1998 1 Rev 1.200 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated ISOLATION LIMITING VALUE & CHARACTERISTIC Ths = 25 C unless otherwise specified SYMBOL Visol PARAMETER R.M.S. isolation voltage from all three terminals to external heatsink CONDITIONS f = 50-60 Hz; sinusoidal waveform; R.H. 65% ; clean and dustfree MIN. TYP. PHX6N50E MAX. 2500 UNIT V Cisol Capacitance from T2 to external f = 1 MHz heatsink - 10 - pF THERMAL RESISTANCES SYMBOL PARAMETER Rth j-hs Rth j-a Thermal resistance junction to heatsink Thermal resistance junction to ambient CONDITIONS with heatsink compound MIN. TYP. MAX. UNIT 55 3.6 K/W K/W ELECTRICAL CHARACTERISTICS Tj = 25 C unless otherwise specified SYMBOL PARAMETER Drain-source breakdown voltage V(BR)DSS / Drain-source breakdown Tj voltage temperature coefficient RDS(ON) Drain-source on resistance VGS(TO) Gate threshold voltage gfs Forward transconductance IDSS Drain-source leakage current IGSS Qg(tot) Qgs Qgd td(on) tr td(off) tf Ld Ls Ciss Coss Crss V(BR)DSS CONDITIONS VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 0.25 mA MIN. 500 2.0 2 TYP. MAX. UNIT 0.1 1.2 3.0 3.6 1 30 10 53 4 28 10 33 92 40 4.5 7.5 610 96 54 1.5 4.0 25 250 200 64 6 34 V %/K V S A A nA nC nC nC ns ns ns ns nH nH pF pF pF VGS = 10 V; ID = 3 A VDS = VGS; ID = 0.25 mA VDS = 30 V; ID = 3 A VDS = 500 V; VGS = 0 V VDS = 400 V; VGS = 0 V; Tj = 125 C Gate-source leakage current VGS = 30 V; VDS = 0 V Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 6 A; VDD = 400 V; VGS = 10 V VDD = 250 V; RD = 39 ; RG = 12 Measured from drain lead to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz December 1998 2 Rev 1.200 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS Tj = 25 C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS Ths = 25C Ths = 25C IS = 6 A; VGS = 0 V IS = 6 A; VGS = 0 V; dI/dt = 100 A/s MIN. - PHX6N50E TYP. MAX. UNIT 390 4 5.9 24 1.2 A A V ns C December 1998 3 Rev 1.200 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHX6N50E 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating with heatsink compound 10 Zth j-hs, Transient thermal impedance (K/W) D = 0.5 PHX2N60 1 0.2 0.1 0.05 0.02 0.1 0.01 single pulse P D tp t D= p T t 100ms 1s T 0 20 40 60 80 Ths / C 100 120 140 0.001 1us 10us 100us 1ms 10ms tp, pulse width (s) Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Ths) ID% Normalised Current Derating with heatsink compound Fig.4. Transient thermal impedance. Zth j-hs = f(t); parameter D = tp/T 120 110 100 90 80 70 60 50 40 30 20 10 0 15 ID, Drain current (Amps) Tj = 25 C PHP4N50 7V 10 V 6.5 V 10 6V 5.5 V 5 5V VGS = 4.5 V 0 20 40 60 80 Ths / C 100 120 140 0 0 5 10 15 20 VDS, Drain-Source voltage (Volts) 25 30 Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Ths); conditions: VGS 10 V ID, Drain current (Amps) Fig.5. Typical output characteristics. ID = f(VDS); parameter VGS RDS(on), Drain-Source on resistance (Ohms) 4.5 V 5V 5.5 V VGS = 6 V PHP4N50 Tj = 25 C 100 PHX4N50 4 10 RD 1 O S( = N) VD S /ID tp = 10 us 100 us 1 ms 10 ms DC 3 6.5 V 7V 2 10 V 0.1 100 ms 1 0.01 1 10 100 1000 VDS, Drain-source voltage (Volts) 10000 0 0 5 10 ID, Drain current (Amps) 15 Fig.3. Safe operating area. Ths = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.6. Typical on-state resistance. RDS(ON) = f(ID); parameter VGS December 1998 4 Rev 1.200 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHX6N50E 15 ID, Drain current (Amps) VDS > ID x RDS(on)max PHP4N50 4 VGS(TO) / V max. 10 3 typ. min. 2 5 1 Tj = 25 C Tj = 150 C 0 0 0 2 4 6 VGS, Gate-Source voltage (Volts) 8 10 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj gfs, Transconductance (S) VDS > ID x RDS(on)max 5 Tj = 25 C 4 3 150 C PHP4N50 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS ID / A SUB-THRESHOLD CONDUCTION 6 1E-01 1E-02 1E-03 2% typ 98 % 1E-04 2 1E-05 1 0 1E-06 0 5 ID, Drain current (A) 10 15 0 1 2 VGS / V 3 4 Fig.8. Typical transconductance. gfs = f(ID); parameter Tj a Normalised RDS(ON) = f(Tj) Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS PHP4N50 Ciss 1000 Junction capacitances (pF) 2 100 1 Coss Crss 0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 10 1 10 100 VDS, Drain-Source voltage (Volts) 1000 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 3 A; VGS = 10 V Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz December 1998 5 Rev 1.200 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHX6N50E 15 VGS, Gate-Source voltage (Volts) ID = 6 A Tj = 25 C 250 V PHP4N50 20 IF, Source-Drain diode current (Amps) VGS = 0 V PHP4N50 15 10 100 V VDD = 400 V 10 150 C 5 Tj = 25 C 5 0 0 10 20 30 40 50 Qg, Gate charge (nC) 60 70 80 0 0 0.2 0.4 0.6 0.8 1 VSDS, Source-Drain voltage (Volts) 1.2 1.4 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS PHP4N50 10 Fig.16. Source-Drain diode characteristic. IF = f(VSDS); parameter Tj 1000 Switching times (ns) VDD = 250 V VGS = 10 V RD = 39 Ohms Tj = 25 C td(off) tf tr Non-repetitive Avalanche current, IAS (A) 100 25 C Tj prior to avalanche = 125 C 1 VDS 10 td(on) tp ID PHP6N50E 1E-05 1E-04 Avalanche time, tp (s) 1E-03 1E-02 1 0.1 1E-06 0 10 20 30 40 RG, Gate resistance (Ohms) 50 60 Fig.14. Typical switching times; td(on), tr, td(off), tf = f(RG) Fig.17. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tp); unclamped inductive load 1.15 1.1 1.05 Normalised Drain-source breakdown voltage V(BR)DSS @ Tj V(BR)DSS @ 25 C 10 Maximum Repetitive Avalanche Current, IAR (A) Tj prior to avalanche = 25 C 1 1 0.95 0.9 0.85 -100 125 C 0.1 PHP6N50E 0.01 1E-06 -50 0 50 Tj, Junction temperature (C) 100 150 1E-05 1E-04 Avalanche time, tp (s) 1E-03 1E-02 Fig.15. Normalised drain-source breakdown voltage; V(BR)DSS/V(BR)DSS 25 C = f(Tj) Fig.18. Maximum permissible repetitive avalanche current (IAR) versus avalanche time (tp) December 1998 6 Rev 1.200 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated MECHANICAL DATA Dimensions in mm Net Mass: 2 g 10.3 max 3.2 3.0 PHX6N50E 4.6 max 2.9 max Recesses (2x) 2.5 0.8 max. depth 2.8 6.4 15.8 19 max. max. seating plane 15.8 max 3 max. not tinned 3 2.5 13.5 min. 1 0.4 M 2 3 1.0 (2x) 0.6 2.54 0.5 2.5 1.3 0.9 0.7 5.08 Fig.19. SOT186A; The seating plane is electrically isolated from all terminals. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for F-pack envelopes. 3. Epoxy meets UL94 V0 at 1/8". December 1998 7 Rev 1.200 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated DEFINITIONS Data sheet status Objective specification Product specification Limiting values PHX6N50E This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. December 1998 8 Rev 1.200 |
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