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PH8030L
N-channel TrenchMOS logic level FET
Rev. 01 -- 6 February 2006 Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology.
1.2 Features
s Optimized for use in DC-to-DC converters s Logic level compatible s Very low switching and conduction losses s Lead-free package
1.3 Applications
s DC-to-DC converters s Voltage regulators s Switched-mode power supplies s Notebook computers
1.4 Quick reference data
s VDS 30 V s RDSon 5.9 m s ID 76.7 A s QGD = 3.1 nC (typ)
2. Pinning information
Table 1: Pin 1, 2, 3 4 mb Pinning Description source (S) gate (G) mounting base; connected to drain (D)
mb
D
Simplified outline
Symbol
G
mbb076
S
1234
SOT669 (LFPAK)
Philips Semiconductors
PH8030L
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2: Ordering information Package Name PH8030L LFPAK Description plastic single-ended surface mounted package (LFPAK); 4 leads Version SOT669 Type number
4. Limiting values
Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage drain-gate voltage (DC) gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature source current peak source current Tmb = 25 C Tmb = 25 C; pulsed; tp 10 s unclamped inductive load; ID = 31 A; tp = 0.14 ms; VDS 30 V; RGS = 50 ; VGS = 10 V; starting at Tj = 25 C Tmb = 25 C; VGS = 10 V; see Figure 2 and 3 Tmb = 100 C; VGS = 10 V; see Figure 2 Tmb = 25 C; pulsed; tp 10 s; see Figure 3 Tmb = 25 C; see Figure 1 Conditions 25 C Tj 150 C 25 C Tj 150 C; RGS = 20 k Min -55 -55 Max 30 30 20 76.7 48.5 300 62.5 +150 +150 52 208 95 Unit V V V A A A W C C A A mJ
Source-drain diode
Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy
PH8030L_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 6 February 2006
2 of 12
Philips Semiconductors
PH8030L
N-channel TrenchMOS logic level FET
120 Pder (%) 80
03aa15
120 Ider (%)
03aa23
80
40
40
0 0 50 100 150 Tmb (C) 200
0 0 50 100 150 200 Tmb (C)
P tot P der = ------------------------ x 100 % P
tot ( 25 C )
ID I der = -------------------- x 100 % I
D ( 25 C )
Fig 1. Normalized total power dissipation as a function of mounting base temperature
103 ID (A) 102 Limit RDSon = VDS / ID
Fig 2. Normalized continuous drain current as a function of mounting base temperature
003aab245
tp = 10 s 100 s
10 DC 1
1 ms 10 ms 100 ms
10-1 10-1
1
10
VDS (V)
102
Tmb = 25 C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PH8030L_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 6 February 2006
3 of 12
Philips Semiconductors
PH8030L
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 4: Rth(j-mb) Thermal characteristics Conditions Min Typ Max 2 Unit K/W thermal resistance from junction to mounting base see Figure 4 Symbol Parameter
10 Zth(j-mb) (K/W) 1 = 0.5 0.2 0.1 10-1 0.05 0.02 single pulse
tp T P
003aab246
=
tp T
t
10-2 10-5
10-4
10-3
10-2
10-1
1
tp (s)
10
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PH8030L_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 6 February 2006
4 of 12
Philips Semiconductors
PH8030L
N-channel TrenchMOS logic level FET
6. Characteristics
Table 5: Characteristics Tj = 25 C unless otherwise specified. Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 A; VGS = 0 V Tj = 25 C Tj = -55 C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; see Figure 9 and 10 Tj = 25 C Tj = 150 C Tj = -55 C IDSS drain leakage current VDS = 30 V; VGS = 0 V Tj = 25 C Tj = 150 C IGSS RG RDSon gate leakage current gate resistance drain-source on-state resistance VGS = 16 V; VDS = 0 V f = 1 MHz VGS = 10 V; ID = 25 A; see Figure 6 and 8 Tj = 25 C Tj = 150 C VGS = 4.5 V; ID = 25 A; see Figure 6 and 8 Dynamic characteristics QG(tot) QGS QGS1 QGS2 QGD VGS(pl) QG(tot) Ciss Coss Crss Ciss td(on) tr td(off) tf VSD trr Qr total gate charge gate-source charge pre-VGS(th) gate-source charge post-VGS(th) gate-source charge gate-drain charge gate-source plateau voltage total gate charge input capacitance output capacitance reverse transfer capacitance input capacitance turn-on delay time rise time turn-off delay time fall time source-drain voltage reverse recovery time recovered charge IS = 25 A; VGS = 0 V; see Figure 13 IS = 20 A; dIS/dt = -100 A/s; VGS = 0 V VGS = 0 V; VDS = 0 V; f = 1 MHz VDS = 12 V; RL = 0.5 ; VGS = 4.5 V; RG = 5.6 ID = 0 A; VDS = 0 V; VGS = 4.5 V VGS = 0 V; VDS = 12 V; f = 1 MHz; see Figure 14 ID = 25 A; VDS = 12 V; VGS = 4.5 V; see Figure 11 and 12 15.2 8.5 4.1 4.4 3.1 3.5 14 2260 460 210 2540 25 53 27 14 0.85 34 11.5 1.2 nC nC nC nC nC V nC pF pF pF pF ns ns ns ns V ns nC 4.7 8.5 7.3 5.9 10.6 9.7 m m m 1.75 1 100 100 A A nA 1.3 0.8 1.7 2.15 2.6 V V V 30 27 V V Conditions Min Typ Max Unit
Source-drain diode
PH8030L_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 6 February 2006
5 of 12
Philips Semiconductors
PH8030L
N-channel TrenchMOS logic level FET
100 ID (A) 80
003aab247
VGS (V) = 10
6
5
4.5
16 RDSon (m)
003aab248
3.2
3.4
3.6
4
12
VGS (V) = 4
60 3.6 8 40 3.4 3.2 20 3 2.8 0 0 0.2 0.4 0.6 VDS (V) 0.8 0 0 20 40 60 80 ID (A) 100 4.5 5 6 4 10
Tj = 25 C
Tj = 25 C
Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values
100 ID (A) 80
003aab249
Fig 6. Drain-source on-state resistance as a function of drain current; typical values
2 a 1.6
003aab273
60
1.2
40
0.8
20
Tj = 150 C
0.4 25 C 0 -60
0 0 1 2 3 4 VGS (V) 5
0
60
120
Tj (C)
180
Tj = 25 C and 150 C; VDS > ID x RDSon
R DSon a = ----------------------------R DSon ( 25 C ) Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature
Fig 7. Transfer characteristics: drain current as a function of gate-source voltage; typical values
PH8030L_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 6 February 2006
6 of 12
Philips Semiconductors
PH8030L
N-channel TrenchMOS logic level FET
3 VGS(th) (V) 2.5 max 2 typ 1.5 min
003aab272
10-3 ID (A) 10-4
003aab271
min
typ
max
1
10-5
0.5
0 -60
10-6 0 60 120 Tj (C) 180 0 0.5 1 1.5 2 VGS (V) 2.5
ID = 1 mA; VDS = VGS
Tj = 25 C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of junction temperature
10 VGS (V) 8 12 V 6 VDS = 19 V ID = 25 A Tj = 25 C
003aab250
Fig 10. Sub-threshold drain current as a function of gate-source voltage
VDS ID VGS(pl)
4
VGS(th)
2
VGS QGS1 QGS2 QGD QG(tot)
003aaa508
0 0 10 20 30 QG (nC) 40
QGS
ID = 25 A; VDS = 12 V and 19 V
Fig 11. Gate-source voltage as a function of gate charge; typical values
Fig 12. Gate charge waveform definitions
PH8030L_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 6 February 2006
7 of 12
Philips Semiconductors
PH8030L
N-channel TrenchMOS logic level FET
100 IS (A) 80
003aab251
104 C (pF)
003aab252
Ciss 60 103 40 150 C 20 Crss 0 0.2 10 0.4 0.6 0.8 1 VSD (V) 1.2
2
Tj = 25 C
Coss
10-1
1
10
VDS (V)
102
Tj = 25 C and 150 C; VGS = 0 V
VGS = 0 V; f = 1 MHz
Fig 13. Source current as a function of source-drain voltage; typical values
Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
003aab253
104
C (pF)
Ciss
Crss 103
102 10-1
1
VGS (V)
10
VDS = 0 V; f = 1 MHz
Fig 15. Input and reverse transfer capacitances as a function of gate-source voltage; typical values
PH8030L_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 6 February 2006
8 of 12
Philips Semiconductors
PH8030L
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface mounted package (LFPAK); 4 leads SOT669
E b2 L1
A c2
A2
C E1 b3
mounting base D1 H D
b4
L2
1
e
2
3
b
1/2 e
4
wM A c X
A A1 C
(A 3)
detail X L yC 0 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A A1 A2 A3 b b2 b3 2.2 2.0 b4 0.9 0.7 c c2 D (1) D1(1) E(1) E1(1) max 5.0 4.8 3.3 3.1 e 1.27 H 6.2 5.8 L 0.85 0.40 L1 1.3 0.8 L2 1.3 0.8 w 0.25 y 0.1 8 0
1.20 0.15 1.10 0.50 4.41 0.25 1.01 0.00 0.95 0.35 3.62
0.25 0.30 4.10 4.20 0.19 0.24 3.80
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT669 REFERENCES IEC JEDEC MO-235 JEITA EUROPEAN PROJECTION ISSUE DATE 03-09-15 04-10-13
Fig 16. Package outline SOT669 (LFPAK)
PH8030L_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 6 February 2006
9 of 12
Philips Semiconductors
PH8030L
N-channel TrenchMOS logic level FET
8. Revision history
Table 6: Revision history Release date 20060206 Data sheet status Product data sheet Change notice Doc. number Supersedes Document ID PH8030L_1
PH8030L_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 6 February 2006
10 of 12
Philips Semiconductors
PH8030L
N-channel TrenchMOS logic level FET
9. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
10. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
12. Trademarks
Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of Koninklijke Philips Electronics N.V.
11. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
13. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
PH8030L_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 6 February 2006
11 of 12
Philips Semiconductors
PH8030L
N-channel TrenchMOS logic level FET
14. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 11 12 13 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information . . . . . . . . . . . . . . . . . . . . 11
(c) Koninklijke Philips Electronics N.V. 2006
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 6 February 2006 Document number: PH8030L_1
Published in The Netherlands

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