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NJU6538
PRELIMINARY
1/8, 1/9, 1/10 Duty BITMAP LCD DRIVER with KEY SCAN
GENERAL DESCRIPTION
The NJU6538 is a 10-common x 65-segment bitmap LCD driver to display graphics or characters. It contains 650 bits display data RAM, microprocessor interface circuit, common and segment drivers, key scan circuit, and general output ports. An image data from MPU through the serial interface is stored into the 650 bits internal displayed on the LCD panel through the commons and segments drivers. The NJU6538 displays 10 x 65 dots graphics or 11-character 1-line by 5 x 7 dots character + 3 x 65 dots icons. It contains key scan circuit transmitting the 25-keys maximum (5 x 5 = 25) to MPU. Also it provides 4 general purpose output ports with PWM output function maximum to drive LEDs or others directly. Furthermore, the NJU6538 can select a LCD driving voltage out of 16 steps voltage by the instruction adjust the display contrast of LCD panel.
PACKAGE OUTLINE
NJU6538FG1
NJU6538FC2
FEATURES
Direct Correspondence between Display Data RAM and LCD Pixel Display Data RAM : 650-bits LCD Drivers : 65-seg, 10-com Serial interface (SIO, SCL, CS) Programmable Duty Ratio 1/8 Duty 7-common x 65-segment + 1-icon common 1/9 Duty 7-common x 65-segment + 2-icon common 1/10Duty 7-common x 65-segment + 3-icon common Bias Ratio 1/4 bias 25-key scan Function (5 x 5 matrix) Needless for anti-reverse current diodes in key scan general Output Ports with 128-steps PWM output (possible LED driving) maximum 4-ports Useful Instruction Set Display ON/OFF, Page Address Set, Column Address Set, Display Data write, ADC Select, Inverse Display ON/OFF, whole display ON/OFF, Reset, EVR Register Set, Duty Select, Power Save mode set, General Output Port PWM phase / frequency set, General Output Port PWM data set, General Output Port / Key scan output select Bleeder Resistance On-chip Software Contrast Control (16 steps) Operating Voltage Logic Operating Voltage 2.7 to 5.5V LCD Driving Voltage 5.0 to 10.0V Package Outline QFP100-G1 QFP100-C2 C-MOS Technology (Substrate: P)
Ver.2003-05-09
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NJU6538
-2-
PIN CONFIGRATION
S0/Po3 S1 S2 S3 S4 K0 K1 K2 K3 K4 VDD VLCD1 VLCD2 V0 V1 V2 VSS OSC RESb CE Po0 Po1 Po2 S0/Po3 S1 S2 S3 S4 K0 K1 K2 K3 K4 VDD VLCD1 VLCD2 V0 V1 V2 VSS OSC RESb CE SCL SIO
NJU6538FG1
NJU6538FC2
SCL SIO SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26
Po2 Po1 Po0 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49
COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51
SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29
Ver.2003-05-09
NJU6538
BLOCK DIAGRAM
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10
VLCD1 E.V.R. Common Driver VLCD2 V0 Instruction Decoder V1 V2 VSS Instruction Data Buffer Page Address Decoder Input Buffer Segment Driver
Display Data RAM
Column Address Decoder
OSC
Oscillator
Timing Generator
Key Data Buffer
RESb Power ON Reset
RESET
Serial I/F
Key Scan Control
General Output Driver
S4 S3 S2 S1
Po3/S0
SCL
SIO
Ver.2003-05-09
Po2 Po1 Po0
CE
K0 K1 K2 K3 K4
SEG63 SEG64 SEG65
SEG1 SEG2 SEG3
Reset
-3-
NJU6538
TERMINAL DESCRIPTION
No. FG1 FC2 1 to 65 3 to 67 66 to 72 68 to 74 73 to 75 75 to 77 76 to 78 78 to 80
Symbol
SEG1 to SEG65 COM1 to COM7 COM8 to COM10 Po0 to Po2
I/O
O O O O
Description
Segment output terminal. Common output terminal. Icon common output terminal. General output port 128-step PWM waveform output by MPU control. General output port / Key scanning input terminal Select General output port or Key scanning input terminal by the instruction. A function must be selected either Po3 or S0 General output port 128-step PWM waveform output by MPU control. Key scanning input terminals (No need for anti-reverse current diode in key scan)
79
81
Po3/S0
O
80 to 83 84 to 88 89 90 91 92 93 94 95 96 97 98 99 100
82 to 85 86 to 90 91 92 93 94 94 96 97 98 99 100 1 2
S1 to S4 K0 to K4 VDD VLCD1 VLCD2 V0 V1 V2 VSS OSC RESb CE SCL SIO
O I I I I/O I I I I/O
Key scanning input terminals. (No need for anti-reverse current diode in key scan) Key scanning input terminals. (with internal pull-down resistor) Power supply terminal.(2.7V to 5.5V) LCD driving voltage input terminal. LCD driving voltage stabilization capacitor terminals. Connect the capacitor between each terminal and Vss.
Ground terminal.
Osclator terminal. Conect the external resistor. Reset terminal. (with internal pull-up resistor) In case of only Power-on Reset should be open. Chip enable terminal Serial clock input terminal Serial Data input or output terminal
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Ver.2003-05-09
NJU6538
FUNCTIONAL DESCRIPTION
(1) Description for each blocks (1-1) Serial I/F The serial I/F controls serial data from external data. (1-2) Instruction data buffer The instruction data buffer stores instruction code from external. (1-3) Instruction decoder The instruction decoder decodes instruction code and controls each blocks. (1-4) Display data RAM The Display data RAM stores data for display from MPU. (1-5) Segment driver The Segment driver generates driving waveform to segment terminal on display data. (1-6) General output driver The General output driver generates output signal level to general output terminal on output data. (1-7) Common driver The Common driver generates driving waveform to common terminal. (1-8) Electrical Variable Resistance (E.V.R.) The Electrical Variable Resistance adjusts LCD driving voltage from V0 to V2. (1-9) Key scan controller The Key scan controller controls to input from external Key data. (1-10) Key data buffer The data buffer for key stores Key data until next key data is stored.
(1-11) CR Oscillator The Oscillator is external connect resistor, which generates the master clock. (1-12) Reset circuit The Reset circuit is type of detectable voltage. It resets internal circuit when the power turns on or drop the voltage.
Fig.1 Display data RAM (DDRAM) Map
Page address Data D0 D1 D2 Display Pattern Common Drivers COM1 COM2 COM3
D0="0"
D3 D4 D5 D6 D0
PAGE 0
COM4 COM5 COM6 COM7 COM8
D0="1"
D1 D2
PAGE 1
COM9 COM10
Column Address
ADC
D0="0" D0="1"
00 01 02 03 04 05 06 40 3F 3E 3D 3C 3B 3A 1 2 3 4 5 6 7 ----------------
3F 01 64
40 00 65
Segment Drivers
Ver.2003-05-09
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NJU6538
(2) Instruction 3-wired Serial I/F is clock synchronized of the SCL clock. and D7 to D0 signal select data or instruction by A0 signal. The data input as MSB(D7) first serially. Table 1. Instruction Code Code
A0 0 0 D7 1 1 D6 0 0 D5 1 1 D4 0 1 D3 1 0 D2 1 0 D1 1 0 D0 0/1 0/1
(*: Don't Care) Description
LCD display ON / OFF D0=0 : OFF, D0=1 : ON Set the page of DDRAM to the page address registor. D0=0 : PAGE 0, D0=1 : PAGE 1 Set the Higher order 3 bits column address to rhe registor. Set the Lower order 4 bits column address to rhe registor. Write the data into the Display data RAM(DDRAM) Set the DDRAM to SEG driver D0=0 : Nomal, D0=1 : Inverse Inverse LCD display ON / OFF D0=0 : Nomal, D0=1 : Inverse Whole Display tern ON D0=0: Normal, D0=1: Whole Display Initialize the internal circuit Set the Contrast control E.V.R. (16 steps) Duty set (1/8,1/9,1/10) (D2,D1,D0)=( 0,0,0) : 1/8Duty (D2,D1,D0)=( 0,0,1) : 1/9 Duty (D2,D1,D0)=( 0,1,0) : 1/10 Duty Set the Power save mode (D1,D0)=(0,0) : Nomal (D1,D0)=(0,1) : Power save 1 (D1,D0)=(1,0) : Power save 2 (D1,D0)=(1,1) : Power save 3 Set the PWM phase / freqency D1: PWM Phase set D0: PWM Freqenccy set Select the General output port for PWM level set PWMEN=0:"L" output PWMEN=1:PWM output Set the Higher order 3 bits PWM data to rhe registor. Set the Lower order 4 bits PWM data to rhe registor. Select General output port or Key scan output select by Po3/S0 terminal D0=0 : General output port D0=1 : Key scan output Do not use this instruction.
Instruction
(a)
Display ON/OFF Page address set Culumn address set Higher order 3-bits Culumn address set Lower order 4-bits Display data write ADC select Inverse display On / Off Whole display ON / Normal display Reset E.V.R. Register Set
(b)
0 0 1 0 0 0 0 0
0 0 * 1 1 1 1 0
0 0
0 0
1 0
*
(c)
Higher order Column add. Lower order Column add.
(d) (e) (f) (g) (h) (i)
Write data 0 0 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0/1 0/1 0/1 0
E.V.R. data
(j)
Duty select
0
0
0
1
1
0
Duty
(k)
Power save mode set
0
0
1
0
0
0
0
Power save
Phase
Freq.
(l)
General output port PWM phase / freqency set General output port serect General output port PWM set High order 3-bits / PWM enable set General output port PWM set Lower order 4-bits
0
0
1
0
1
0
0
0
0
1
1
0
0 PWMEN
0
Port
(m)
0
1
0
0
0
High order PWM data
0
0
1
1
1
Lower order PWM data
(n)
General output port / Key scan output select
0
1
0
0
1
0
0
0
0/1
(o)
Maker test
0
1
1
1
1
Test data
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Ver.2003-05-09
NJU6538
(2-1) Instruction discription (a) Display ON / OFF This instruction selects display turn-on or turn-off regardless of the contents of the DDRAM.
A0 0 D
D7 1
D6 0
D5 1
D4 0
D3 1
D2 1
D1 1
D0 D
0: Display OFF 1: Display ON
(b)
Page address set In order to access to the DDRAM for writing or reading display data, both "page address set" and "column address set" instructions are required before accessing. The page address "0" should be used for icon display because the only D0 to D6 is valid. The page address "1" should be used for icon display because the only D0 to D2 is valid. A0 0 A0 0 1 D7 1 D6 0 D5 1 Page 0 1 D4 1 D3 0 D2 0 D1 0 D0 A0
(c)
Column address set As above-mentioned, in order to access to the DDRAM for writing or reading display data, it is necessary to execute both "page address set" and "column address set" before accessing. The 8-bit column address data will be valid when both upper 3-bit and lower 4-bit data are set into the column address register. Once the column address is set, it will automatically increment (+1) whenever the DDRAM will be accessed, so that the DDRAM will be able to be continuously accessed without "column address set" instruction. The column address will stop increment and the page address will not be changed when the last address (40)H is addressed. A0 0 0 A6 0 0 : : 1 D7 0 0 A5 0 0 : : 0 D6 0 0 A4 0 0 : : 0 D5 0 0 A3 0 0 : : 0 D4 1 0 A2 0 0 : : 0 D3 * A3 A1 0 0 : : 0 D2 A6 A2 A0 0 1 : : 0 D1 A5 A1 D0 A4 A0
Upper 4-bit Lower 4-bit
Column address (HEX) 00 01 : : 40
Ver.2003-05-09
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NJU6538
(d) Display data write This instruction writes display data into the selected column address on the DDRAM. The column address automatically increments (+1) whenever the display data is written by this instruction, so that this instruction can be continuously issued without "column address set" instruction. A0 1 D7 * D6 D5 D4 D3 D2 Write data D1 D0
*:Don't Care (e) ADC select This instruction selects segment driver direction. The correspondence between the column address and segment driver direction is shown in Fig.1. Segment Driver Output order is inverse, when this instruction executes, therefore, the placement NJU6538 against the LCD panel becomes easy. A0 0 D D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 D S65 S1
0: Clokwise Output(Normal) S1 1: Counterclockwise Output(Inverse) S65
(f)
Inverse display ON / OFF This instruction inverses the status of turn-on or turn-off of entire LCD pixels. It doesn't change the contents of the DDRAM. A0 0 D D7 1 0: Normal 1: Inverse D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 D
RAM data "1" correspond to "On" RAM data "0" correspond to "On"
(g)
Whole display ON This instruction turns on entire LCD pixels regardless the contents of the DDRAM. It doesn't change the contents of DDRAM. This instruction executed prior to the "Normal or Inverse display On/Off Set" Instruction. A0 0 D D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 D
0: Normal Display 1: Whole Display turns On
(Whole display OFF) (Whole display ON)
-8-
Ver.2003-05-09
NJU6538
(h) Reset This instruction reset the LSI to the following status, however it doesn't change the contents of the DDRAM. Please be careful that it can't be substituted for the reset operation by using of the RESb terminal. Reset status by "reset" instruction: 1. Page address : (0) page 2. Column address : (00)H 3. EVR register : (D3, D2, D1, D0 = "1, 1, 1, 1") 4. Duty select :1/10 Duty 5. General output port(Po0 to Po3) PWM phase / frequency (D1,D0 = "0,0") 6. General output port(Po0 to Po3) PWMEN=0, PWM value (PWM6, PWM 5, PWM 4, PWM 3, PWM 2, PWM 1, PWM 0 = " 0,0,0,0,0,0,0") 7. Set the General output port (Po3) by Po3/S0 terminal The DDRAM is not affected by this initialization. A0 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0
(i)EVR register set E.V.R. resister set instruction adjusts the contrast of the LCD, and selects. One LCD driving voltage VLCD out of 16 voltage-stages by setting E.V.R. register. Set the binary code "0000" when contrast adjustment is unused. A0 0 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D7 0 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D6 0 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D5 1 D4 0 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D3 D2 D1 E.V.R. data D0
VLCD2 terminal level (Typical) V LCD1 0.984V LCD1 0.968V LCD1 0.952V LCD1 0.938V LCD1 0.923V LCD1 0.909V LCD1 0.896V LCD1 0.882V LCD1 0.870V LCD1 0.857V LCD1 0.845V LCD1 0.833V LCD1 0.822V LCD1 0.811V LCD1 0.800V LCD1
Ver.2003-05-09
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NJU6538
(j) Duty select Duty select instruction is which sets LCD driving duty ratio 1/8 or 1/9 or 1/10 duty. A0 0 D2 0 0 0 D7 0 D1 0 0 1 D6 0 D0 0 1 0 D5 1 D4 1 D3 0 D2 D1 Duty D0
Duty ratio 1/8 Duty 1/9 Duty 1/10 Duty
Scan Common COM1 to COM8 (5x7 character + 1-icon ) COM1 to COM9 (5x7 character + 2-icon ) COM1 to COM10 (5x7 character + 3-icon )
(k)
Power save mode set Power save mode reduces the operating current of application using Display Off and selects a terminal condition of Key scan signal output. The terminal, which is set to "L", does not output Key scan signal as shown in following table. A0 0 D7 0 D6 1 D5 0 D4 0 D3 0 Internal OSC. ON Stop Stop Stop D2 0 D1 D0
Power save
Key scanning output terminals
D1
D0
Function
LCD output ON Display Off Display Off Display Off S0 H L L H S1 H L L H
0 0 Normal 0 1 Power save 1 1 0 Power save 2 1 1 Power save 3 *1 No scanning states.
states *1 S2 S3 H H L L L H H H
S4 H H H H
(l)
General output port PWM phase / freqency set General output port PWM phase / frequency set instruction setting PWM phase and PWM frequency. A0 0 D1 0 1 D0 0 1 D7 0 D6 1 D5 0 D4 1 D3 0 D2 0 D1 Phase D0 Frequency
General Output Port PWM phase set 32-steps shift phase PWM output timinng by Po0 to Po1, Po1 to Po2, Po2 to Po3. same phase PWM output timinng by Po0 to Po3. General Output Port PWM frequency set fsys / 128 frequency. (Default) fsys / 256 frequency. (fsys : system clock = fosc / 2)
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Ver.2003-05-09
NJU6538
(m) General output port set. This instruction sets the PWM value outputted from Po0 ~ Po3 terminals. The "General output port select" instruction selects the general output port to output with PWM. The "General output port PWM set" instruction sets the PWM value. The "General output port select instruction" and the "General output port PWM set instruction" is not necessary to continuously perform. Because these instructions are independently.
1. General output port select. This instruction selects the general output port to output with PWM. A0 0 D1 0 0 1 1 D7 0 D0 0 1 0 1 D6 1 D5 1 D4 0 Port Po0 Po1 Po2 Po3 D3 0 D2 0 D1 Port D0
2. General output port PWM set This instruction sets the PWM value outputted from Po0 ~ Po3 terminals. The PWM output setting is available for 128-step at each port output terminals. A0 0 0 D7 1 0 D6 0 1 D5 0 1 D4 0 1 D3
PWMEN PWM3
D2
PWM6 PWM2
D1
PWM5 PWM1
D0
PWM4 PWM0
A) PWMEN 0:Selected general output port is "L" output. 1:Selected general output port outputs PWM depending on PWM data. B) PWM6 to PWM0 PWM value:This register sets the duty value of PWM outputted from the selected general output port. The PWM value set requires twice, which are upper 3-bit and lower 4-bit. The PWM duty is (Register + 1 ) / 128.
Ver.2003-05-09
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NJU6538
(*:Don't Care)
PWMEN PWMEN
PWM 6
PWM 5
PWM 4
PWM 3
PWM 2
PWM 1
PWM 0
PWM 6
PWM 5
PWM 4
PWM 3
PWM 2
PWM 1
PWM 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
PWM DUTY
0
1
* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
* 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
* 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
* 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
* 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0/128 1/128 2/128 3/128 4/128 5/128 6/128 7/128 8/128 9/128 10/128 11/128 12/128 13/128 14/128 15/128 16/128 17/128 18/128 19/128 20/128 21/128 22/128 23/128 24/128 25/128 26/128 27/128 28/128 29/128 30/128 31/128 32/128 33/128 34/128 35/128 36/128 37/128 38/128 39/128 40/128 41/128 42/128 43/128 44/128 45/128 46/128 47/128 48/128 49/128 50/128 51/128 52/128 53/128 54/128 55/128 56/128 57/128 58/128 59/128 60/128 61/128 62/128 63/128 64/128
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
65/128 66/128 67/128 68/128 69/128 70/128 71/128 72/128 73/128 74/128 75/128 76/128 77/128 78/128 79/128 80/128 81/128 82/128 83/128 84/128 85/128 86/128 87/128 88/128 89/128 90/128 91/128 92/128 93/128 94/128 95/128 96/128 97/128 98/128 99/128 100/128 101/128 102/128 103/128 104/128 105/128 106/128 107/128 108/128 109/128 110/128 111/128 112/128 113/128 114/128 115/128 116/128 117/128 118/128 119/128 120/128 121/128 122/128 123/128 124/128 125/128 126/128 127/128 128/128
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Ver.2003-05-09
PWM DUTY
NJU6538
Example ) Set output PWM waveform of Po0 to Po3 terminal, shown below: * PWM phase set D1=0, * PWMEN=1, * (PWM6, PWM 5, PWM 4, PWM 3, PWM 2, PWM 1, PWM 0)=(1,0,0,0,0,0,0)
PWM frequency (fPWM) Po0 1 65 66 128
Po1
1
65 66
128
Po2
1
65 66
128
Po3
1
65 66
32-steps
32-steps
32-steps
(n) General output port / Key scan output select This instruction assigns function of general purpose output port or key scan output to Po3/S0 terminals. A0 0 D D7 1 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 D
0: General output port 1: Keyscan output
Ver.2003-05-09
- 13 -
NJU6538
(3) Input Data Format and Timing Data format is shown below. When the CE terminal goes to "L", I/F is data output. When the CE terminal goes to "H" (rising edge) at SCL terminal "H", I/F is data input.
CE SCL SIO
SIO state Output
*
D7
D6
D5
D4
D3
Input
D2
D1
D0
A0
*
Output
NOTE1) Data fetched at SCL rising edge. NOTE2) A contents change of the instruction and data which were written is fetched by the 9th rising edge of SCL. NOTE3) When the instruction and data which were written are less than 9-bit, they are ignored and is not fetched. NOTE4) When the instruction and data which were written are over 9-bit, the last 9-bit is valid. (4) Power save mode set Power save mode is set by "Power save mode set" instruction. The segment and common output "L" is outputted, the OSC terminal halts an oscillation (it oscillates at the time of key-on), and consumption current is decreased. Power save mode is canceled, when normally set by "Power save mode set" instruction.
(5) Key scan circuit Key scan circuit connects the 5 x 5 key-matrix maximum and reads the data of 25 keys maximum. It chooses the number of keys in key-matrix by "General output port / key scan output select" instruction. It outputs a identified key data to MPU after comparison with two data read from the key-matrix in twice for reliable key operation. If those data are not identified, key data is not outputted. It outputs "L" signal through "SO" terminal as the request after 332T[s] (T=1/fsys=2/fosc,fsys : Internal system clock frequency) when any key is operated. Furthermore, the key scan circuit structures for reducing the external components like as Diodes to prevent circuit short problem.
(5-1) The relation between output data and key matrix The relation between output data and key matrix shows bellow table and sets "1" signal for operated key. In case of 20 keys application, unassigned area for keys from KD1 to KD5 in bellow table take "0" signal. In mode of Power save 1, area for keys from KD1 to KD20 in bellow table take "0" signal. In mode of Power save 2, area from KD1 to KD15 take "0" signal also. The terminals, which are not connected any keys, should be open. K0 K1 K2 K3 K4 S0 KD1 KD2 KD3 KD4 KD5 S1 KD6 KD7 KD8 KD9 KD10 S2 KD11 KD12 KD13 KD14 KD15 S3 KD16 KD17 KD18 KD19 KD20 S4 KD21 KD22 KD23 KD24 KD25
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Ver.2003-05-09
NJU6538
(5-2) Data output timing The data output format shows bellow. The data output mode is set by "L" status of SCL terminal at the rising signal of CE terminal. CE SCL
SIO
*
KD1 KD2
KD24 KD25
PSF
Key data
SIO state
Output
Output
Output
(5-3) Power save flag (PSF) The status of Power save flag is outputted after KD25 in Key data reading. This flag sets "1" signal in mode of Power save in Key data reading and sets "0" in mode of Normal.
(5-4) Timing of Key scan Key scan cycle is 160T[S] (T=1/fsys=2/fosc,fsys : Internal system clock frequency). The data of key scan is a result of comparison with a couple of Key scan for correct judge whether Key On or Off. When the result of comparison is correct (accord), the NJU6538 recognizes Key On and outputs "L" level from SIO terminal after 322T[S] from start of Key scan for a request to read key data out to external MPU. When the SIO terminals outputs "L" signal, the key scan does not operate until end of key data reading by MPU, and scanned key data is kept. When the result of comparison is incorrect (not accord), Key scan operates again if any key is On. Therefore, Key scan may operate incorrectly in case of shorter period of Key on than 322T[S]
Key ON 160T[s] S0 S1 S2 S3 S4 *1 *1 *1 *1 *1 1 2 3 4 5 1 2 3 4 5 *1 *1 *1 *1 *1 T=1/fsys =2/fosc (fsys : Internal system clock frequency) SIO 322T [s]
*1
Instruction set the General output ports or output the Key scan signals (refer (1)Instruction (n)General output port / Key scan select)
Key scan cycle and the timing of Key data read out request are constant in any Power save mode.
Ver.2003-05-09
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NJU6538
(5-5) Normal mode Key scan operates with follows in normal mode. 1, Key scan signal output terminals S0 - S4 output "H" signals when key scan does not operate, and output key scan signals after start of key scan operation. The conditions of key scan signal input terminals K0 - K4 are "L" state with internal pull-down resistances, though "H" signal comes in to K0 - K4 corresponding to the turned on keys. 2, The function of key scan starts twice operations when any key is turned on. It stops when a couple of data by continuously twice key scan operations are accorded and fixed as a correct key status. It operates more 2 times when the key status is not fixed and any keys are still turning on. It repeats again and again until key status is fixed. The correct key status data is stored and newly key scan operation does not start until external MPU reads data out after key status is fixed. 3, When the key status is fixed, SO terminal outputs "L" signal as Key data read out request to MPU. MPU should read key data out at detection of this "L" signal. 4, The Key data read out request signal is released and SO terminal outputs "H" signal after finish of MPU key data read out for newly key scan operation. SIO terminal requires pull up resistor because of Open drain type output. Multiple data of key are output in case of key more input so that MPU should process the data by itself. Key scan example (Normal mode)
Key input 1 Key input 2
T = 1 / fosc
Key scan 322T[s] CE 322T[s] 322T[s]
SCL
Data send Data send Data send
SI
SO
Key data read Key data read request Key data read Key data read request Key data read Key data read request
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Ver.2003-05-09
NJU6538
(5-6) Power save mode Key scan operates with follows in Power save mode. 1, Key scan signal output terminals S0 - S4 output "H", "L" signals by the Power save mode set when key scan does not operate (refer the detail of instructions), and output key scan signals after start of key scan operation. The conditions of key scan signal input terminals K0 - K4 are "L" state with internal pull-down resistances, though "H" signal comes in to K0 - K4 corresponding to the turned on keys. 2, The oscillation circuit function of key scan starts twice operations when any keys on cross points with S0- S4 terminals line and K0 - K4 turned on. It stops when a couple of data by continuously twice key scan operations are accorded and fixed as a correct key status. It operates more 2 times when the key status is not fixed and any keys are still turning on. It repeats again and again until key status is fixed. The correct key status data is stored and newly key scan operation does not start until external MPU reads data out after key status is fixed. 3, When the key status is fixed, SIO terminal outputs "L" signal as Key data read out request to MPU. MPU should read key data out at detection of this "L" signal. 4, The Key data read out request signal is released and SIO terminal outputs "H" signal after finish of MPU key data read out for newly key scan operation. Although Power save mode is not released. SIO terminal requires pull up resistor because of Open drain type output. Multiple data of key are output in case of key more input so that MPU should process the data by itself.
Key scan example (Power save mode) Ex.) D0= "0", D1= "1" (K4="H" power save)
S0 "L" S1 "L" S2 "L" S3 "L" *1 S4 "H"
K0 K1 K2 K3 K4
When some key on these lines are turned on, the oscillation starts and Key scan starts the operation until all of key are turned off.
These diodes are required to recognize key more input of keys on the K4 line when only K4 terminal outputs "H" signal in power save mode as shown above example. In case of no diodes, incorrect key data may read out sometimes by key more input of keys on lines of K0 to K4. T=1/fsys =2/fosc (fsys : Internal system clock frequency) Key input (K4) *1 Key scan 322T[s] CE 322T[s]
SCL
Data send Data send Data send T = 1 / fosc
SI
SO
Key data read Key data read request Ver.2003-05-09 Key data read Key data read request
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NJU6538
(5-7) Key More Input Key scan signal output terminal S0 to S4 output "H" level in state of Key More Input. Although Key state is detected without diodes to prevent unexpected key scan signal flow, non-pressed key data may change pressed key data in triple or more key Input as shown in Fig. 1 and incorrect key data may be output to external MPU. For prevention of miss-recognition by incorrect key data, diodes should be inserted in front of K0 - K4 terminals as shown in Fig. 3 or control program of MPU should ignore the combination of key data miss-recognition. For example, 4 keys and more ON data should be ignored.
S0 S1 S2 S3 S4 K0 K1 K2 K3 K4
Pressed key Miss-recognized key
In case of 3 keys operation in left picture, if S3 terminal outputs "H" signal, this signal goes around on the dotted line and non-pressed key is miss-recognized as pressed key.
Fig. 1 Miss-recognized example by key more input In modes of power save 1 (S0=0, S1=1 / Keys on only S5 line are valid) or power save 2 (S0=0, S1=1 / Keys on only S4 and S5 lines are valid), pay attention about the followings. When Key More Input is operated across the valid line and invalid, non-pressed key is miss-recognized as pressed key. However, Key data on the invalid line is not read out and 4 keys and more operation in the mean time are not ignored by MPU control program as shown in Fig. 2. In this case, diodes operate to prevent miss-recognition as shown in Fig. 3.
S0 S1 S2 S3 S4 K0 K1 K2 K3 K4
Pressed key Miss-recognized key
S0 No active key S1 S2 S3 Active key S4 K0 K1 K2 K3 K4 Miss-recognition prevent diodes
In case of power save 1, MPU control program can not decide ether correct key data or incorrect as shown above because key data on only S4 line is read out to MPU (all of key data on S3 line become to "0".
Fig. 2 Miss-recognition in power save 1
Fig. 3 Connect miss-recognition prevent diodes
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Ver.2003-05-09
NJU6538
(5-8) Key data reading out operation by external MPU (a) Display data writing Display data and an instruction change operate at the rising edge of 9-bit on SCL signal. (b) Key data reading out operation The minimum period from Key in to SIO terminal = "L" is 322T(t1) by key scan operation. When key scan operation performs again for key data fix preventing from noise or bouncing of key, the period from Key in to SIO terminal = "L" is 676T(t1). When the SIO terminal outputs "L", the key scan operation is stopped after execution of key data reading out operation. Therefore, fixed key data is kept until end of key data reading out operation. When key data reading out operation is performed during SO terminal = "H", both of key data from KD1 to KD25 and power save flag (PSF) are not outputted correctly. Key data reading out operation example The flowchart below shows an example of timer interrupt application. When SIO terminal condition is "L" after check of SIO terminal condition at every timer interrupt operation, it is decided as Key In and key data reading out operation is performed. When SIO terminal condition is "H, it is decided as Key Off. For the correct decision of Key Off, the timer interrupt cycle (1/t3) should be expanded over the time added with [period of key scan (676T in case of measure against key bouncing of key) and [period of key data reading out operation (t2)]. In this time, the period of timer interrupt cycle (t3) must be set with enough margins including the range of fosc. Sequence of key data reading out operation
Timer
Yes
SO="L"?
No
Key ON
Key OFF
Key data read out
End of Timer
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NJU6538
Timing chart of key data reading out operation
Key ON Key input t1 SO CE SCL t3 Interrupt Key OFF Key ON Key OFF t3 t3 t3 t2 t1 t2 t1 Key OFF
Decision
t1: Key scan time t2: Key data read time t3: Interrupt cycle *: t3 > t1 + t2
(6) Reset circuit initializes Reset circuit initializes the NJU6538 at Power ON and OFF. It generates reset signal to initialize the system at low VDD less than power down detection voltage (2.0V typical). (6-1) Initial status in reset 1, Stop the oscillation circuit 2, Display Off (Available Serial data transmission) 3, Disable Key scan function 4, Filled "L" data in all of key data buffer " (6-2) The status of output port terminals in Reset Output terminals SEG1 to SEG65 COM1 to COM10 Po0 to Po2 Po3/S0 S1 to S4 SIO
*1 *2
Reset status L L L L *1 H H *2
This terminal operates as segment driver and outputs "L". This terminal consisted of Open-drain output type circuit requires external pull-up resister connect ting to external power source for MPU. I f key data read is executed in power on reset, the read data is fixed as "H".
The reset circuit initializes the LSI to the following status by using of the input 10s(min.) or over "L" level signal into the RESb terminal. The LSI will return to normal operation after about 1.0s(max.) from the rising edge of the rest signal. The "Reset" instruction can't be substituted for the reset operation by using of the RESb terminal. It executes above-mentioned only 7 to 13 items.
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Ver.2003-05-09
NJU6538
(6-3) Reset status using the RESb terminal (default) 1. Serial interface register clear 2. Display off 3. ADC select : D0="0" (Normal mode) 4. Normal Display (Non-inverse display) 5. Whole display off : D0="0" (Normal mode) 6. Power save mode : D1, D0="0, 0" (Normal mode) 7. Page address : 0 page 8. Column address : 00H 9. EVR register : D3, D2, D1, D0="1, 1, 1, 1" 10. Duty select : 1/10 Duty 11. General output port PWM phase and frequency : D1, D0="0, 0" 12. General output port : PWMEN=0 ("L" output), PWM value : D6, D5, D4, D3, D2, D1, D0="0, 0, 0, 0, 0, 0, 0" 13. Po3/S0 terminal : D0=" 0" (Po3)
(6-4) Initialization by Hardware The NJU6538 incorporates reset terminal to initialize the all system. When the "L" level signal input over then 10us(min.) to the RESb terminal, reset sequence is executed. In this time, internal busy during 1us after RESb terminal goes to "H". Reset circuit
RESb
Hardware Reset
System Reset
Power on Reset
(6-5) Power on reset operation When the voltage rising time of power source is over than 1mS, the generated signal of VDET initializes the system of NJU6538 as reset. When the voltage falling time of power source is over than 1ms, the system is also reset. When these voltage rising or falling time of power source are not over than 1ms, the Initialization operation as reset does not operate correctly.
VDD>2.7V
VDD
VDET
VDET
tON>1 ms
tOFF>1 ms
Ver.2003-05-09
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NJU6538
(7) LCD panel drive (7-1) LCD driving voltage generation circuit LCD driving voltage generation circuit generates LCD driving bias voltages VLCD2, V0, V1 and V2. It adjusts the voltage by 8 steps electrical volume from VLCD1 and allots the voltage to VLCD2, V0, V1 and V2 by resistor-voltage-dividing as shown in below. VLCD1, VLCD2, V0, V1 and V2 terminals requires external capacitors for bias voltage stabilization for display quality. These values of capacitors should be fixed in accordance with evaluation in the application.
Power Supply VLCD
Duty ratio Bias
1/8,1/9,1/10 1/4 VLCD2-VSS
Internal NJU6538
E.V.R. (16-steps)
VLCD1 10k VLCD2 10k V0 10k V1 10k V2 VSS
+ + + + +
(Note 1) (Note 1) (Note 1) (Note 1)
VLCD
10k
(Note 1)
Note 1 : Resistor is typical value.
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Ver.2003-05-09
NJU6538
ABSOLUTE MAXIMUM RATINGS
Ta=25C PARAMETER Supply voltage Input terminal voltage SYMBOL VDD max VLCD max VIN1 VIN2 VOUT1 VDD terminal VLCD1 terminal OSC, K0 to K4,CE, SCL, SIO terminal VLCD2, V0 to V2 terminal CONDITIONS RATINGS -0.3 to +7.0 -0.3 to +11.0 -0.3 to VDD+0.3 -0.3 to VLCD+0.3 V UNIT V
SIO terminal -0.3 to +6.0 V OSC, SEG1 to SEG65,COM1 to COM10, -0.3 to VDD+0.3 VOUT2 S1 to S4, Po0 to Po2, Po3 /S0 terminal 1000 Ta=25C QFP100-C2 Power dissipation Pdmax mW 700 Ta=25C QFP100-G1 Storage temperature Tstg -55 to +125 C Operating temperature Topr -40 to +85 C Note 1) All voltage values are specified as VSS=0V. Note 2) If the LSI are used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the erectric characteristics conditions will cause malfunction and poor reliability. Note 3) Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation forthe voltage converter. Output terminal voltage
Ver.2003-05-09
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NJU6538
DC Electrical Characteristics
VDD=2.7 to 5.5V, Ta= - 40 to 85C PARAMETER Power supply (1) Power supply (2) Output voltage Input voltage "H" level input voltage (1) "H" level input voltage (2) "L" level input voltage (1) Hysteresis voltage "H" level input current "L" level input current Pull-up resistance Pull-down resistance Output off-leak current "H" level output voltage (1) "H" level output voltage (2) "L" level output voltage (1) "L" level output voltage (2) "L" level output voltage (3) Driver ON-resistance (COM) Driver ON-resistance (SEG) Oscillation Frequency
SYMBO L NOT E
CONDITION VDD VLCD1 VLCD2 V0 V1 V2 K0 to K4 SCL, SIO, CE K0 to K4, SCL, SIO, CE SCL, SIO, CE SCL, SIO, CE, SCL, SIO, K0 to K4, CE,
MIN 2.7 5.0 4.0 VSS VSS VSS 0.6VDD 0.8VDD 0 VIN = VDD V IN = 0V -5.0 50 50 VDD-1.2 VDD-1.1 VDD-1.0 VDD-0.6 0.2 0.05
TYP
MAX 5.5 10.0 VLCD1 VLCD2 VLCD2 VLCD2 VDD VDD 0.2VDD 5.0
UNIT V V V V V V V A A
VDD VLCD1 VLCD2 V0 V1 V2 VIH(1) VIH(2) VIL(1) VH IIH IIL RPU RPD IOFFH VOH(1) VOH(2) VOL(1) VOL(2) VOL(3) RCOM RSEG fOSC V0
VLCD2x3/4 VLCD2x2/4 VLCD2x1/4
1
0.25VDD
RESb VDD=5.0V, V IN = 0V K0 to K4, VDD=5.0V, VIN = VDD SIO, VO=5.5V VDD=5.0V, Io = -500uA S0 to S4 VDD=3.0V, Io = -250uA VDD=5.0V, Io = -10mA Po0 to Po3 VDD=3.0V, Io = -5mA VDD=5.0V, Io = 25A S0 to S4 VDD=3.0V, Io = 5A VDD=5.0V, Io = 10mA Po0 to Po3 VDD=3.0V, Io = 5mA SIO Io = 1mA Ta=25C, VO=V LCD2,VSS,V0,V2 +Id=1A (COM terminal) Ta=25C, VO=V LCD2,VSS,V1 +Id=1A (SEG terminal) Ta=25C, VDD=5.0V ROSC=150k E.V.R. value "0,0,0,0" V LCD1=8.0V VLCD2-VSS, Ta=25C VLCD1-VLCD2, Ta=25C
150 150
250 250 6.0 VDD-0.2 VDD-0.1
k k A V V
1.5 0.6 1.0 0.6 0.5 40 40
V V V k k
kHz
2 2
38 5.8 3.8 1.8
50 6.0 4.0 2.0 40 10
62 6.2 4.2 2.2
LCD Driving voltage Bleeder resistance E.V.R. resistance Power down detect voltage Reset time Reset "L" pulse width
V1 V2 RB REVR VDET Tr Trw IDD1 IDD2
V k k
0.8 RESb RESb Power save mode VDD=5.5V, Output open fOSC=50kHz, Power save mode VLCD1=10.0V Output open fOSC=50kHz, 1.0 10.0
1.4
2.0
V s s A A A A
100 500 5 1000
Operating current
ILCD1 ILCD2
Note 1) Note 2)
The relation : VLCD1VLCD2V0V1V2VSS must be maintained. RCOM and RSEG are the resistance values between power supply terminals (VSS, VLCD2, or V0, V1, V2) and each common terminal, and supply voltage (VSS, VLCD2, or V0, V1, V2) and each segment terminal respectively, and measured when the current Id is flown on every common and segment terminals at a same time.
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Ver.2003-05-09
NJU6538
AC Characteristics
VDD=2.7 to 5.5V, Ta= - 40 to 85C PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNIT
NOTE
"L" level tWCLL SCL 160 ns clock pulse width "H" level tWCLH SCL 160 ns clock pulse width Data setup time tDS SCL, SIO 160 ns Data hold time tDH SCL, SIO 160 ns CE wait time tCP CE, SCL 160 ns CE setup time tCS CE, SCL 160 ns CE hold time tCH CE, SCL 160 ns CE "L" level width tWCL CE 160 ns SIO output delay time tDC SIO, Rpu=4.7k, CL=10pF 1.5 s 1 SIO rise time tDR SIO, Rpu=4.7k, CL=10pF 1.5 s SCL rise tine tr 15 ns SCL fall time tf 15 ns SO terminal is Open-Drain type output, so that the characteristics of SO terminal are changed by values of pull-up resistance Rpu and CL.
(1) Write operation
CE
tWCLL tWCLH tCH tWCL
SCL
tCP tCS tf tr
SIO
D0 tDS tDH
D1
(2) Key data read operation CE
tCP tCS tWCLH tWCLL tCH
SCL
tr tDC tf tDR D0
SIO
INVALID
Ver.2003-05-09
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NJU6538
Relation between oscillation frequency and LCD frame frequency (1)1/8 duty 1 2 1 line select time(40 T[s]) VLCD2 V0 V1 V2 Vss 3 4 5 6 78 1 2 3
T = 1/fsys = 2/fosc (fsys : Internal system clock frequency)
4
5
6
7
8
1
23
COM1
1frame 1 2 3 4 5 6 78 1 2 3
1frame 4 5 6 7 8 1 23
SEGn
VLCD2 V0 V1 V2 VSS
ON OFF Ex.)fosc=50kHz Frame frequency =1/(40T x duty)=1/(40 x (2/50kHz) x 8)=78.1(Hz)
(2)1/10 duty
T = 1/fsys = 2/fosc (fsys : Internal system clock frequency)
1 line select time(35 T[s]) VLCD2 V0 V1 V2 Vss 1 23 45 6 7 8 9 10 1 23
4
56
7
8 9 10 1
23
COM1
1frame 1 23 45 6 7 8 9 10 1 23
1frame 4567 8 9 10 1 23
SEGn
VLCD2 V0 V1 V2 VSS
ON OFF fosc=50kHz Frame frequency =1/(35T x duty)=1/(35 x (2/50kHz) x 10)=71.4(Hz)
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Ver.2003-05-09
NJU6538
APPLICATION CIRCUIT
VDD VSS
*1
VDD VSS RESb CE SC SIO
COM1 COM10 ---SEG1 ----
7com 65seg matrix +195 icon LCD panel
MPU *2 VLCD *3 *3 *3 *3 *3 VSS
VLCD1 VLCD2 V0 V1 V2
NJU6538
SEG65 General output ports Po0 Po1 Po2 Po3/S0
VSS OSC Po3/S0 S1 S2 S3 S4 5 x5 key matrix *4 K0 K1 K2 K3 K4
*1 *2 *3 *4
The rising time of Power source voltage at Power on and the falling time at Power off must keep over than 1ms because of Voltage detection type Reset circuit operation. SO terminal requires external pull-up resistor connecting to Power source of external MPU because of Open-drain type output. This capacitor for bias voltage stabilization should be connected in accordance with display quality in application. PO3 / S0 terminal is general output ports and Key scan signal output duplicated-function terminals. A function must be selected either Segment output or other.
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
Ver.2003-05-09
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