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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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1:10 LVCMOS Zero Delay Clock Buffer
The MPC9608 is a 3.3 V compatible, 1:10 PLL based zero-delay buffer. With a very wide frequency range and low output skews the MPC9608 is targeted for high performance and mid-range clock tree designs. Features * 1:10 outputs LVCMOS zero-delay buffer * Single 3.3 V supply * Supports a clock I/O frequency range of 12.5 to 200 MHz * Selectable divide-by-two for one output bank * Synchronous output enable control (CLK_STOP) * Output tristate control (output high impedance) * PLL bypass mode for low frequency system test purpose * Supports networking, telecommunications and computer applications * Supports a variety of microprocessors and controllers * Compatible to PowerQuicc I and II * Ambient Temperature Range -40C to +85C * 32-lead Pb-free package available
MPC9608
LOW VOLTAGE 3.3 V LVCMOS 1:10 ZERO-DELAY CLOCK BUFFER
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FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A
Functional Description The MPC9608 uses an internal PLL and an external feedback path to lock its low-skew clock output phase to the reference clock phase, providing virtually zero propagation delay. This enables nested clock designs with near-zero insertion delay. Designs using the MPC9608 as PLL fanout buffer will show significantly lower clock skew than clock distributions developed from traditional fanout buffers. The device offers one reference clock input and two banks of 5 outputs for clock fanout. The input frequency and phase is reproduced by the PLL and provided at the outputs. A selectable frequency divider sets the bank B outputs to generate either an identical copy of the bank A clocks or one half of the bank A clock frequency. Both output banks remain synchronized to the input reference for both bank B configurations. Outputs are only disabled or enabled when the outputs are already in logic low state (CLK_STOP). For system test and diagnosis, the MPC9608 outputs can also be set to high-impedance state by connecting OE to logic high level. Additionally, the device provides a PLL bypass mode for low frequency test purpose. In PLL bypass mode, the minimum frequency and static phase offset specification do not apply. CLK_STOP and OE do not affect the PLL feedback output (QFB) and down stream clocks can be disabled without the internal PLL losing lock. The MPC9608 is fully 3.3 V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines on the incident edge. For series terminated transmission lines, each of the MPC9608 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a 7x7 mm2 32-lead LQFP package.
AC SUFFIX 32 LEAD LQFP PACKAGE-Pb-free CASE 873A
REV 2
(c) Motorola, Inc. 2004
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MPC9608
CCLK
Bank A
QA0
STOP
CCLK
25k
Ref
PLL
00: 100-200 MHz 01: 50-100 MHz 10: 25- 50 MHz
VCO
QA1 QA2 QA3 QA4
Bank B
FB_IN
25k
FB 11:12.5- 25 MHz
F_RANGE[0:1]
25k 2
QB0 QB1
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PLL_EN
25k
/2
QB2 QB3
CLK_STOP
25k
QB4
PLL feedback
BSEL
25k
OE
25k
QFB
Figure 1. MPC9608 Logic Diagram
F_RANGE0
F_RANGE1
CLK_STOP
BSEL
GND
24 VCC QA4 QA3 QA2 GND QA1 QA0 VCC 25 26 27 28 29 30 31 32 1
23
22
21
20
19
18
17 16 15 14 VCC QB4 QB3 QB2 GND QB1 QB0 VCC
MPC9608
GND
13 12 11 10 9 8
VCC
2
3
4
5
6
PLL_EN
GND
VCC
FB_IN
OE
7
CCLK
VCCA
Figure 2. MPC9608 32-Lead Package Pinout (Top View)
2
GND
QFB
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MPC9608
TABLE 1. PIN CONFIGURATION
Pin CCLK FB_IN F_RANGE[0:1] BSEL PLL_EN OE CLK_STOP I/O Input Input Input Input Input Input Input Output Output Supply Supply Supply Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC PLL reference clock signal PLL feedback signal input, connect to a QFB output PLL frequency range select Frequency divider select for bank B outputs PLL enable/disable Output enable/disable (high-impedance tristate) Synchronous clock enable/stop Clock outputs PLL feedback signal output. Connect to FB_IN Negative power supply PLL positive power supply (analog power supply). The MPC9608 requires an external RC filter for the analog power supply pin VCCA. Refer to the Applications Information section for details. Positive power supply for I/O and core Function
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QA0-4, QB0-4 QFB GND VCCA VCC
TABLE 2. FUNCTION TABLE
Control F_RANGE[0:1] BSEL CLK_STOP
OE
Default 00 0 0 0
0
1
PLL frequency range. Refer to Table 3 "Clock frequency configuration for QFB connected to FB_IN" fQB0-4 = fQA0-4 Outputs enabled Outputs enabled (active) fQB0-4 = fQA0-4 / 2 Outputs synchronously stopped in logic low state Outputs disabled (high-impedance state), independent on CLK_STOP. Applying OE = 1 and PLL_EN = 1 resets the device. The PLL feedback output QFB is not affected by OE. Test mode with PLL disabled. CCLK is substituted for the internal VCO output. MPC9608 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Applying OE = 1 and PLL_EN = 1 resets the device.
PLL_EN
0
Normal operation mode with PLL enabled.
TABLE 3. Clock Frequency Configuration for QFB connected to FB_IN
F_RANGE[0] F_RANGE[1] BSEL fREF (CCLK) range [MHz] 100.0 - 200.0 QA0-QA4 Ratio fREF fREF fREF fREF fQA0-4 [MHz] 100.0 - 200.0 Ratio fREF fREF / 2 50.0 - 100.0 50.0 - 100.0 fREF fREF / 2 25.0 - 50.0 25.0 - 50.0 fREF fREF / 2 12.5 - 25.0 12.5 - 25 fREF fREF / 2 QB0-B4 fQB0-4 [MHz] 100.0 - 200.0 50.0 - 25.0 50.0 - 100.0 25.0 - 50.0 25.0 - 50.0 12.5 - 25.0 12.5 - 25.0 6.25 - 12.5 fREF fREF fREF fREF fREF fREF fREF fREF QFB
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
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TABLE 4. GENERAL SPECIFICATIONS
Symbol VTT MM HBM LU CPD CIN Characteristics Output termination voltage ESD protection (Machine model) ESD protection (Human body model) Latch-up immunity Power dissipation capacitance Input capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition
TABLE 5. ABSOLUTE MAXIMUM RATINGSa
Symbol Characteristics Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition VCC VIN VOUT IIN IOUT TS a.
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Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
TABLE 6. DC CHARACTERISTICS (VCC = 3.3 V 5%, TA = -40 to 85C)
Symbol VIH VIL VOH VOL ZOUT IIN ICCA ICCQ a. b. Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Currentb 4.0 1.0 14 - 17 200 8.0 4.0 2.4 0.55 0.30 Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V V V V A mA mA VIN = VCC or GND VCCA Pin All VCC Pins Condition LVCMOS LVCMOS IOH = -24 mAa IOL = 24 mA IOL = 12 mA
Maximum PLL Supply Current Maximum Quiescent Supply Current
The MPC9608 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. Inputs have pull-down resistors affecting the input current.
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MPC9608
TABLE 7. AC CHARACTERISTICS (VCC = 3.3 V 5%, TA = -40 to 85C)a
Symbol fref Characteristics Input reference frequency in PLL modeb F_RANGE = 00 F_RANGE = 01 F_RANGE = 10 F_RANGE = 11 Input reference frequency in PLL bypass modec Output Frequencyd F_RANGE = 00 F_RANGE = 01 F_RANGE = 10 F_RANGE = 11 100 50 25 12.5 0 100 50 25 12.5 2.0 1.0 +175 +1.75% of tPER 80 100 150 45 0.1 50 55 1.0 10 10 150 150 RMS (1 )
f
Min
Typ
Max 200 100 50 25 200 200 100 50 25
Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz ns ns ps ps ps
Condition
fmax
BSEL = 0 BSEL = 0 BSEL = 0 BSEL = 0 0.8 V to 2.0 V PLL Locked
tPW, MIN
Reference Input Pulse Widthe CCLK Input Rise/Fall Time
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tr, tf t()
Propagation Delay (SPO) CCLK to FB_IN fref = 100 MHz and above -175 fref = 12.5 MHz to 100 MHz -1.75% of tPER Output-to-Output Skew Within a bank Bank-to-bank All outputs, inluding QFB Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitter Period Jitter I/O Phase Jitter PLL closed loop bandwidth F_RANGE = 00 F_RANGE = 01 F_RANGE = 10 F_RANGE = 11 7 - 15 2-7 1-3 0.5 - 1.3 10
tSK(o)
DC tr, tf tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() BW
% ns ns ns ps ps ps MHz MHz MHz MHz ms BSEL = 0 BSEL = 0 BSEL = 0 0.55 V to 2.4 V
125
tLOCK a. b. c. d. e. f.
Maximum PLL Lock Time
AC characteristics apply for parallel output termination of 50 to VTT. PLL mode requires PLL_EN = 0 to enable the PLL and zero-delay operation. In bypass mode, the MPC9608 divides the input reference clock. Applies for bank A and for bank B if BSEL = 0. If BSEL = 1, the minimum and maximum output frequency of bank B is divided by two. Calculation of reference duty cycle limits: DCREF, MIN = tPW, MIN * fREF *100% and DCREF, MAX = 100% - DCREF, MIN. For example, at fREF = 100 MHz the input duty cycle range is 20% < DC < 80%. -3 dB point of PLL transfer characteristics.
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APPLICATIONS INFORMATION
Power Supply Filtering The MPC9608 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA (PLL) power supply impacts the device characteristics, for instance I/O jitter. The MPC9608 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA pin for the MPC9608. Figure 3 illustrates a typical power supply filter scheme. The MPC9608 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 4 mA (8 mA maximum), assuming that a minimum of 3.125 V must be maintained on the VCCA pin. The resistor RF shown in Figure 3 "VCCA Power Supply Filter" must have a resistance of 9 - 10 (VCC = 3.3 V) to meet the voltage drop criteria.
RF = 9-10 for VCC = 3.3 V CF = 1 F for VCC = 3.3 V
(isolated power and grounds and fully differential PLL), there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Using the MPC9608 in Zero-delay Applications Nested clock trees are typical applications for the MPC9608. Designs using the MPC9608, as LVCMOS PLL fanout buffer with zero insertion delay, will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9608 clock driver allows for its use as a zero delay buffer. By using the QFB output as a feedback to the PLL the propagation delay through the device is virtually eliminated. The PLL aligns the feedback clock output edge with the clock input reference edge resulting in a near zero delay through the device. The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of Part-to-Part Skew The MPC9608 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9608 are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() . CF
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VCC
RF CF 10 nF
VCCA MPC9608 VCC 33...100 nF
This maximum timing uncertainty consists of 4 components: static phase offset, output skew, feedback board trace delay, and I/O (phase) jitter:
CCLKCommon -t() QFBDevice 1
tPD,LINE(FB)
Figure 3. VCCA Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 3 "VCCA Power Supply Filter", the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9608 has several design features to minimize the susceptibility to power supply noise
tJIT() +tSK(O) +t()
Any QDevice 1
QFBDevice2
tJIT()
Any QDevice 2 Max. skew
+tSK(O) tSK(PP)
Figure 4. MPC9608 maximum device-to-device skew
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MPC9608 Due to the statistical nature of I/O jitter, an RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8. TABLE 8. Confidence Facter CF
CF 1 2 3 4 5 6 Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 IN IN
MPC9608 OUTPUT BUFFER
14
RS = 36
ZO = 50 OutA
MPC9608 OUTPUT BUFFER
14
RS = 36
ZO = 50 OutB0
RS = 36
ZO = 50 OutB1
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The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of -295 ps to 295 ps1 relative to CCLK: tSK(PP) = tSK(PP) = [-100 ps...100 ps] + [-150 ps...150 ps] + [(15 ps . -3)...(15 ps . 3)] + tPD, LINE(FB) [-295 ps...295 ps] + tPD, LINE(FB)
Figure 5. Single versus Dual Transmission Lines The waveform plots in Figure 6 "Single versus Dual Line Termination Waveforms" show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9608 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. From the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9608. The output waveform in Figure 6 "Single versus Dual Line Termination Waveforms" shows a step in the waveform. This step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = Z0 = RS = R0 = VL = = VS ( Z0 / (RS + R0 + Z0)) 50 || 50 36 || 36 14 3.0 ( 25 / (18 + 17 + 25)) 1.31 V
Driving Transmission Lines The MPC9608 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC / 2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9608 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 5 "Single versus Dual Transmission Lines" illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the MPC9608 clock driver is effectively doubled due to its capability to drive multiple lines.
At the load end the voltage will double to 2.6 V due to the near unity reflection coefficient. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns).
1. Skew data are designed targets and pending device specifcations.
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3.0 2.5 VOLTAGE (V) 2.0
OutA tD = 3.8956
OutB tD = 3.9386
MPC9608 OUTPUT BUFFER
14
RS = 22
ZO = 50
In
1.5 1.0 0.5
RS = 22
ZO = 50
14 + 22 || 22 = 50 || 50 25 = 25 Figure 7. Optimized Dual Line Termination
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0
2
4
6 8 10 TIME (nS)
12
14
Figure 6. Single versus Dual Waveforms Since this step is well above the threshold region, it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 7 "Optimized Dual Line Termination" should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC9608 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 8. CCLK MPC9608 AC test reference for VCC = 3.3 V
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MPC9608
VCC VCC / 2 GND VCC VCC / 2 GND FB_IN CCLK
VCC VCC / 2 GND VCC VCC / 2 GND
tSK(O)
The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device.
t()
Figure 9. Output-to-output Skew tSK(O)
Figure 10. Propagation delay (tPD, static phase offset) test reference
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VCC VCC / 2 GND
CCLK
tP T0 DC = tP/T0 x 100%
The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage.
FB_IN
TJIT() = |T0 - T1 mean|
The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles.
Figure 11. Output Duty Cycle (DC)
Figure 12. I/O Jitter
TN
TN + 1
TJIT(CC) = |TN -TN + 1|
T0
TJIT(PER) = |TN - 1/f0|
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs.
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles.
Figure 13. Cycle-to-cycle Jitter
Figure 14. Period Jitter
VCC = 3.3 V 2.4 0.55 tF tR
CLK_STOP CCLK
VCC VCC / 2 GND VCC VCC / 2 GND
ts Figure 15. Output Transition Time Test Reference
tH
Figure 16. Setup and Hold Time (ts, tH) Test Reference
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OUTLINE DIMENSIONS
4X
6 D1
PIN 1 INDEX
0.20 H
A-B D e/2 3 A, B, D
D1/2
32 25
1
E1/2 A 6 E1
DETAIL G 8
B E E/2 4
F
F
17
DETAIL G
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08-mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION: 0.07-mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1-mm AND 0.25-mm FROM THE LEAD TIP.
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7
9
D D 4
D/2
4X
0.20 C
A-B D
H
28X
e
32X
0.1 C
SEATING PLANE
C
DETAIL AD
PLATING BASE METAL
b1 c c1
b
8X
5
8
(1)
R R2 R R1
0.20
M
C A-B D
SECTION F-F
A
A2
0.25
GAUGE PLANE
A1
(S) (L1)
L
DETAIL AD
DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 q q1 R1 R2 S
MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.30 0.40 0.09 0.20 0.09 0.16 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.50 0.70 1.00 REF 0 7 12 REF 0.08 0.20 0.08 --0.20 REF
FA SUFFIX LQFP PACKAGE AC SUFFIX LQFP PACKAGE-Pb-free CASE 873A-02 ISSUE A
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MPC9608
NOTES
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