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| E2G1054-18-62 Semiconductor MD56V62800A Semiconductor This version: Jun. 1998 MD56V62800A Pr el im in ar y 4-Bank 2,097,152-Word 8-Bit SYNCHRONOUS DYNAMIC RAM DESCRIPTION The MD56V62800A is a 4-bank 2,097,152-word 8-bit synchronous dynamic RAM, fabricated in Oki's CMOS silicon-gate process technology. The device operates at 3.3 V. The inputs and outputs are LVTTL compatible. FEATURES * * * * * * * Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell 4-bank 2,097,152-word 8-bit configuration 3.3 V power supply, 0.3 V tolerance Input : LVTTL compatible Output : LVTTL compatible Refresh : 4096 cycles/64 ms Programmable data transfer mode - CAS latency (1, 2, 3) - Burst length (1, 2, 4, 8, full page) - Data scramble (sequential, interleave) * Burst read single bit write capability * CBR auto-refresh, Self-refresh capability * Package: 54-pin 400 mil plastic TSOP (Type II) (TSOPII54-P-400-0.80-K) (Product : MD56V62800A-xxTA) xx indicates speed rank. PRODUCT FAMILY Family MD56V62800A-8 MD56V62800A-10 Max. Frequency 125 MHz 100 MHz Access Time (Max.) tAC2 10 ns 9 ns tAC3 6 ns 9 ns 1/28 Semiconductor PIN CONFIGURATION (TOP VIEW) VCC DQ1 VCCQ NC DQ2 VSSQ NC DQ3 VCCQ NC DQ4 VSSQ NC VCC NC WE CAS RAS CS A13/BA0 A12/BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 MD56V62800A 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 VSS 53 DQ8 52 VSSQ 51 NC 50 DQ7 49 VCCQ 48 NC 47 DQ6 46 VSSQ 45 NC 44 DQ5 43 VCCQ 42 NC 41 VSS 40 NC 39 DQM 38 CLK 37 CKE 36 NC 35 A11 34 A9 33 A8 32 A7 31 A6 30 A5 29 A4 28 VSS 54-Pin Plastic TSOP (II) (K Type) Pin Name CLK CS CKE A0 - A11 A12, A13 RAS CAS WE Function System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Pin Name DQM DQi VCC VSS VCCQ VSSQ NC Function Data Input/Output Mask Data Input/Output Power Supply (3.3 V) Ground (0 V) Data Output Power Supply (3.3 V) Data Output Ground (0 V) No Connection Note: The same power supply voltage must be provided to every VCC pin and VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin. 2/28 Semiconductor MD56V62800A PIN DESCRIPTION CLK CS CKE Fetches all inputs at the "H" edge. Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE and DQM. Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Address Row & column multiplexed. Row address: RA0 - RA11 Column address: CA0 - CA8 A12, A13 (BA1, BA0) RAS CAS WE DQM DQi Masks the read data of two clocks later when DQM is set "H" at the "H" edge of the clock signal. Masks the write data of the same clock when DQM is set "H" at the "H" edge of the clock signal. Data inputs/outputs are multiplexed on the same pin. Functionality depends on the combination. For details, see the function truth table. Bank Access pins. These pins are dedicated to select one of 4 banks. 3/28 Semiconductor BLOCK DIAGRAM MD56V62800A CLK CKE CLOCK BUFFER Command Decoding Logic Command Buffers Control Logic A0 A13 Address Buffers Mode Register Latency & Burst controller Column Address Latches & Counter Column Decoders Sense Amplifiers CS RAS CAS WE DQM Row Address Latches & Refresh Counter Row Decoders Word Drivers Memory Cells BANK A BANK B BANK C BANK D Input Buffers Input Data Register DQ1 - DQ8 Output Data Register Output Buffers 4/28 Semiconductor MD56V62800A ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS VCC Supply Voltage Storage Temperature Power Dissipation Short Circuit Current Operating Temperature Symbol VIN, VOUT VCC, VCCQ Tstg PD* IOS Topr Rating -0.5 to VCC + 0.5 -0.5 to 4.6 -55 to 150 1 50 0 to 70 (Voltages referenced to VSS) Unit V V C W mA C *: Ta = 25C Recommended Operating Conditions Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC, VCCQ VIH VIL Min. 3.0 2.0 VCC - 2.0 Typ. 3.3 -- -- (Voltages referenced to VSS = 0 V) Max. 3.6 VCC + 2.0 0.8 Unit V V V Capacitance (VCC = 3.3 V, Vbias = 1.4 V, Ta = 25C, f = 1 MHz) Parameter Input Capacitance (CLK) Input Capacitance (CKE, CS, RAS, CAS, WE, DQM, A0 - A13) Input/Output Capacitance (DQ1 - DQ8) Symbol CCLK CIN COUT Min. 2.5 2.5 4 Max. 4 5 6.5 Unit pF pF pF 5/28 Semiconductor DC Characteristics Condition Parameter Symbol Bank -- -- -- -- One Bank Active CKE -- -- -- -- CKE VIH Others IOH = -2 mA IOL = 2 mA -- -- tCC = min tRC = min No Burst tCC = min tRC = min tRRD = min No Burst tCC = min tCC = min -- CKE VIH, CS VIH CKE VIH CKE VIH tCC = min -- tCC = min tCC = min tRC = min tCC = min -- CKE VIL tCC = min -- 2 -- 2 -- 60 -- 6 -- -8 Min. 2.4 -- -5 -5 -- Max. -- 0.4 5 5 125 Version MD56V62800A Output High Voltage VOH Output Low Voltage Input Leakage Current Output Leakage Current VOL ILI ILO ICC1 Average Power Supply Current (Operating) Unit Note -10 Min. Max. 2.4 -- V -- -5 -5 -- 0.4 5 5 115 V mA mA mA 1, 2 ICC1D Both Banks Active CKE VIH -- 175 -- 165 mA 1, 2 Power Supply Current (Stand by) ICC2 Both Banks Precharge CKE VIH CKE VIL -- 30 -- 30 mA 3 Average Power ICC3S Both Banks Active Supply Current (Clock Suspension) Average Power Supply Current (Active Stand by) Power Supply Current (Burst) Power Supply Current (Auto-Refresh) Average Power Supply Current (Self-Refresh) Average Power Supply Current (Power down) ICC3 One Bank Active Both Banks Active One Bank Active Both Banks Precharge Both Banks Precharge 6 mA 2 50 mA 3 ICC4 ICC5 -- 165 -- 155 mA 1, 2 -- 185 -- 185 mA 2 ICC6 CKE 0.2 V 2 mA ICC7 2 mA Notes: 1. Measured with outputs open. 2. The address and data can be changed once or left unchanged during one cycle. 3. The address and data can be changed once or left unchanged during two cycles. 6/28 Semiconductor MD56V62800A Mode Set Address Keys Write Burst Length A9 0 1 Write Burst Length Burst Write Single Bit Write A6 0 0 0 0 1 1 1 1 CAS Latency A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CL Reserved 1 2 3 Reserved Reserved Reserved Reserved 0 1 Burst Type A3 BT Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 0 1 0 1 0 1 0 1 BT = 0 1 2 4 8 BT = 1 1 2 4 8 Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved Notes: 1. A7, A8, A10, A11, A12 and A13 should stay "L" during mode set cycle. 2. When A9 = 1, a burst length for write operation is always 1 regardless of the burst lengths set by A0, A1 and A2. POWER ON SEQUENCE 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200 ms or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply a CBR auto-refresh eight or more times. 5. Enter the mode register setting command. 7/28 Semiconductor AC Characteristics Parameter CL = 3 Clock Cycles Time CL = 2 CL = 1 CL = 3 Access Time from CL = 2 Clock CL = 1 Clock "H" Pulse Time Clock "L" Pulse Time Input Setup Time Input Hold Time Output Low Impedance Time from Clock Output High Impedance Time from Clock Output Hold from Clock RAS Cycle Time RAS Precharge Time RAS Active Time RAS to CAS Delay Time Write Recovery Time RAS to RAS Bank Active Delay Time Refresh Time Power-down Exit Set-up Time Input Level Transition Time CAS to CAS Delay Time (Min.) Clock Disable Time from CKE Data Output High Impedance Time from DQM Data Input Mask Time from DQM Data Input Time from Write Command CL = 3 Data Output High Impedance Time from CL = 2 Precharge Command CL = 1 Active Command Input Time from Mode Register Set Command Input (Min.) Write Command Input Time from Output tAC tCH tCL tSI tHI tOLZ tOHZ tOH tRC tRP tRAS tRCD tWR tRRD tREF tPDE tT lCCD lCKE lDOZ lDOD lDWD tCC Symbol MD56V62800A-8 Min. 8 12 24 -- -- -- 3 3 2 1 3 -- 3 80 30 50 20 8 16 -- tSI + 1 CLK -- 1 1 2 0 0 3 lROH 2 1 lMRD lOWD 3 2 Max. -- -- -- 6 10 22 -- -- -- -- -- 8 -- -- -- 100,000 -- -- -- 64 -- 3 MD56V62800A-10 Min. 10 15 30 -- -- -- 3 3 3 1 3 -- 3 90 30 60 30 10 20 -- tSI + 1 CLK -- 1 1 2 0 0 3 2 1 3 2 Max. -- -- -- 9 9 27 -- -- -- -- -- 8 -- -- -- MD56V62800A Note 1, 2 Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle 3 3, 4 3, 4 3, 4 100,000 -- -- -- 64 -- 3 8/28 Semiconductor Notes : 1. AC measurements assume that tT = 1 ns. 2. The reference level for timing of input signals is 1.4 V. 3. Output load. 1.4 V Z = 50 W Output 50 pF 50 W MD56V62800A 4. The access time is defined at 1.4 V. 5. If tT is longer than 1 ns, then the reference level for timing of input signals is VIH and VIL. 9/28 Semiconductor TIMING WAVEFORM Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CKE CS RAS CAS ADDR A13 A12 A10 DQ WE DQM , , ,, , MD56V62800A 16 17 18 19 tRC tRP tRCD Ra Ca0 Rb Cb0 Ra Rb tOH Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 tAC tOHZ tWR Row Active Read Command Row Active Write Command Precharge Command Precharge Command 10/28 Semiconductor MD56V62800A Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 2, Burst Length = 4 tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK ,,, ,, tCC tCL CKE CS High tHI tSI RAS tSI tHI lCCD CAS tSI tSI tSI ADDR Ra Ca Cb Cc tHI tHI A13 A12 A10 DQ Ra tAC tHI Qa Db Qc tOLZ tSI tOH tOHZ lOWD tHI WE tSI DQM Row Active Write Command Precharge Command Read Command Read Command 11/28 Semiconductor *Notes: MD56V62800A 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CKE and DQM are invalid. 2. When issuing an active, read or write command, the bank is selected by A12 and A13. A12 0 0 1 1 A13 0 1 0 1 Active, read or write Bank A Bank B Bank C Bank D 3. The auto precharge function is enabled or disabled by the A10 input when the read or write command is issued. A10 0 1 0 1 0 1 0 1 A12 0 0 0 0 1 1 1 1 A13 0 0 1 1 0 0 1 1 Operation After the end of burst, bank A holds the idle status. After the end of burst, bank A is precharged automatically. After the end of burst, bank B holds the idle status. After the end of burst, bank B is precharged automatically. After the end of burst, bank C holds the idle status. After the end of burst, bank C is precharged automatically. After the end of burst, bank D holds the idle status. After the end of burst, bank D is precharged automatically. 4. When issuing a precharge command, the bank to be precharged is selected by the A10, A12 and A13 inputs. A10 0 0 0 0 1 A12 0 0 1 1 X A13 0 1 0 1 X Operation Bank A is precharged. Bank B is precharged. Bank C is precharged. Bank D is precharged. All banks are precharged. 5. The input data and the write command are latched by the same clock (Write latency = 0). 6. The output is forced to high impedance by (1 CLK + tOHZ) after DQM entry. 12/28 Semiconductor MD56V62800A Page Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK CKE CS RAS CAS ADDR A13 A12 A10 DQ WE DQM *Notes: , , , ,, , ,, , , , , , 17 18 19 High Bank A Active lCCD Ca0 Cb0 Cc0 Cd0 Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 lOWD tWR *Note2 *Note1 Read Command Read Command Write Command Write Command Precharge Command 1. To write data before a burst read ends, DQM should be asserted three cycles prior to the write command to avoid bus contention. 2. To assert row precharge before a burst write ends, wait tWR after the last write data input. Input data during the precharge input cycle will be masked internally. 13/28 ,,,, , , , Semiconductor MD56V62800A Read & Write Cycle with Auto Precharge @ Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS High RAS tRRD CAS ADDR RAa RDb CAa CDb A13 A12 A10 WE RAa RDb CAS Latency = 2 DQ QAa0 QAa1 QAa2 QAa3 DDb0 DDb1 DDb2 DDb3 A-Bank Precharge Start DQM CAS Latency = 3 DQ QAa0 QAa1 QAa2 QAa3 DDb0 DDb1 DDb2 DDb3 A-Bank Precharge Start tWR DQM Row Active (A-Bank) A Bank Read with Auto Precharge Row Active (D-Bank) D Bank Write with Auto Precharge D Bank Precharge Start Point 14/28 Semiconductor Bank Interleave Random Row Read Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK CKE CS RAS CAS ADDR A13 A12 A10 DQ WE DQM , , , , , ,, MD56V62800A 18 19 High tRC tRRD RAa CAa RCb CCb RAc CAc RAa RCb RAc QAa0 QAa1 QAa2 QAa3 QCb0 QCb1 QCb2 QCb3 QAc0 QAc1 QAc2 QAc3 Row Active (A-Bank) Read Command (A-Bank) Read Command (C-Bank) Read Command (A-Bank) Row Active (C-Bank) Precharge Command (A-Bank) Precharge Command (C-Bank) Row Active (A-Bank) 15/28 Semiconductor MD56V62800A , , ,, , , ,, , 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Bank Interleave Random Row Write Cycle @ CAS Latency = 2, Burst Length = 4 CLK CKE CS High RAS CAS ADDR RAa CAa RBb CBb RAc CAc A13 A12 A10 DQ RAa RBb RAc DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 WE DQM Row Active (A-Bank) Row Active (B-Bank) Write Command (A-Bank) Precharge Command (A-Bank) Write Command (B-Bank) Write Command (A-Bank) Row Active (A-Bank) Precharge Command (A-Bank) Precharge Command (B-Bank) 16/28 Semiconductor Bank Interleave Page Read Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CKE CS RAS CAS ADDR A13 A12 A10 DQ WE DQM *Note: , ,,, , , MD56V62800A 16 17 18 19 High *Note1 RAa CAa RCb CCb CAc CCd CAe RAa RCa QAa0 QAa1 QAa2 QAa3 QCb0 QCb1 QCb2 QCb3 QAc0 QAc1 QCd0 QCd1 QAe0 QAe1 lROH Row Active (A-Bank) Row Active (C-Bank) Read Command (C-Bank) Precharge Command (A-Bank) Read Command (A-Bank) Read Command (C-Bank) Read Command (A-Bank) Read Command (A-Bank) 1. CS is ignored when RAS, CAS and WE are high at the same cycle. 17/28 , ,, ,, , , , , , Semiconductor MD56V62800A Bank Interleave Page Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS High RAS CAS ADDR RBa CBa RDb CDb CBc CDd A13 A12 A10 DQ RBa RDb DBa0 DBa1 DBa2 DBa3 DDb0 DDb1 DDb2 DDb3 DBc0 DBc1 DDd0 WE DQM Row Active (B-Bank) Row Active (D-Bank) Write Command (D-Bank) Write Command (B-Bank) Write Command (D-Bank) Write Command (B-Bank) Precharge Command (All Banks) 18/28 Semiconductor MD56V62800A , , , , , Bank Interleave Random Row Read/Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS High RAS CAS ADDR RAa CAa RCb CCb RAc CAc A13 A12 A10 DQ RAa RCb RAc QAa0 QAa1 QAa2 QAa3 DCb0 DCb1 DCb2 DCb3 QAc0 QAc1 QAc2 QAc3 WE DQM Row Active (A-Bank) Row Active (C-Bank) Write Command (C-Bank) Read Command (A-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Row Active (A-Bank) 19/28 Semiconductor MD56V62800A Bank Interleave Page Read/Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR A13 A12 A10 DQ WE DQM ,, ,,, , , CAa0 CDb0 CAc0 QAa0 QAa1 QAa2 QAa3 DDb0 DDb1 DDb2 DDb3 QAc0 QAc1 QAc2 QAc3 Read Command (A-Bank) Write Command (D-Bank) Read Command (A-Bank) 20/28 Semiconductor MD56V62800A Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 *Note1 *Note1 CKE CS RAS CAS ADDR Ra Ca Cb Cc A13 A12 A10 DQ WE Ra *Note2 tOHZ Qa0 Qa1 Qa2 Qb0 Qb1 Dc0 Dc2 tOHZ *Note3 DQM Row Active Read Command CLOCK Suspension Read Command CLK *Notes: , , , , , , ,, , , , Read DQM Read DQM Write Command Write DQM CLOCK Suspension Write DQM 1. When Clock Suspension is asserted, the next clock cycle is ignored. 2. When DQM is asserted, the read data after two clock cycles is masked. 3. When DQM is asserted, the write data in the same clock cycle is masked. 21/28 Semiconductor Read Interruption by Precharge Command @ Burst Length = 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 MD56V62800A CLK CKE CS RAS CAS ADDR A13 A12 A10 WE CAS Latency = 2 DQ DQM CAS Latency = 3 DQ DQM ,, ,,, ,, ,, , 14 15 16 17 18 19 High Ra Ca Ra Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 IROH Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 IROH Row Active Read Command Precharge Command 22/28 , , , ,, Semiconductor MD56V62800A Power Down Mode @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tSI *Note1 tPDE *Note2 tSI CKE CS tSI RAS CAS ADDR Ra Ca A13 A12 A10 DQ Ra Qa0 Qa1 Qa2 WE DQM Row Active Power-down Entry Power-down Exit Clock Suspention Entry Clock Suspention Exit Read Command Precharge Command *Notes: 1. When all banks are in precharge state, and if CKE is set low, then the MD56V62800A enters power-down mode and maintains the mode while CKE is low. 2. To release the circuit from power-down mode, CKE has to be set high for tPDE (tSI + 1 CLK) or more. 23/28 Semiconductor Self Refresh Cycle 0 1 2 CLK CKE CS RAS CAS ADDR A13 A12 A10 DQ WE DQM , ,,, ,, ,, MD56V62800A tRC tSI Ra BS BS Ra Hi - Z Hi - Z Self Refresh Entry Self Refresh Exit Row Active 24/28 Semiconductor Mode Register Set Cycle 0 1 2 3 4 5 6 MD56V62800A Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 CLK CKE CS RAS CAS ADDR DQ WE DQM ,, , ,, , High High lMRD tRC key Ra Hi - Z Hi - Z MRS New Command Auto Refresh Auto Refresh 25/28 Semiconductor MD56V62800A FUNCTION TRUTH TABLE (Table 1) (1/2) Current State1 CS RAS CAS WE BA Idle H L L L L L L L Row Active H L L L L L L Read H L L L L L L L Write H L L L L L L L Read with Auto Precharge H L L L L L L Write with Auto Precharge H L L L L L L X H H H L L L L X H H H L L L X H H H H L L L X H H H H L L L X H H H H L L X H H H H L L X H H L H H L L X H L L H H L X H H L L H H L X H H L L H H L X H H L L H L X H H L L H L X H L X H L H L X X H L H L X X H L H L H L X X H L H L H L X X H L H L X X X H L H L X X X X BA BA BA BA X L X X BA BA BA BA X X X BA BA BA BA BA X X X BA BA BA BA BA X X X BA BA X BA X X X BA BA X BA X ADDR X X X CA RA A10 X OP Code X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 X RA, A10 X X X X CA, A10 X RA, A10 X NOP NOP ILLEGAL 2 ILLEGAL 2 Row Active NOP 4 Auto-Refresh or Self-Refresh 5 Mode Register Write NOP NOP Read Write ILLEGAL 2 Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Term Burst Term Burst, start new Burst Read Term Burst, start new Burst Write ILLEGAL 2 Term Burst, execute Row Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Term Burst Term Burst, start new Burst Read Term Burst, start new Burst Write ILLEGAL 2 Term Burst, execute Row Precharge ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL Action 26/28 Semiconductor MD56V62800A FUNCTION TRUTH TABLE (Table 1) (2/2) Current State1 CS RAS CAS WE BA Precharge H L L L L L L Write Recovery H L L L L L L Row Active H L L L L L L Refresh H L L L L Mode Register Access H L L L L ABBREVIATIONS RA = Row Address CA = Column Address Notes: X H H H L L L X H H H L L L X H H H L L L X H H L L X H H H L X H H L H H L X H H L H H L X H H L H H L X H L H L X H H L X X H L X H L X X H L X H L X X H L X H L X X X X X X X H L X X X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X X X X X X X X X X ADDR X X X CA RA A10 X X X X CA RA A10 X X X X CA RA A10 X X X X X X X X X X X NOP --> Idle after tRP NOP --> Idle after tRP ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 NOP 4 ILLEGAL NOP NOP ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL NOP --> Row Active after tRCD NOP --> Row Active after tRCD ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL NOP --> Idle after tRC NOP --> Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL Action BA = Bank Address AP = Auto Precharge NOP = No OPeration command 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of lCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle. 27/28 Semiconductor MD56V62800A FUNCTION TRUTH TABLE for CKE (Table 2) Current State (n) CKEn-1 Self Refresh H L L L L L L Power Down H L L L L L L All Banks Idle (ABI) 6 CKEn X H H H H H L X H H H H H L H L L L L L L L L H L H L CS RAS CAS WE X H L L L L X X H L L L L X X H L L L L L L X X X X X X X H H H L X X X H H H L X X X H H H L L L X X X X X X X H H L X X X X H H L X X X X H H L H L L X X X X X X X H L X X X X X H L X X X X X H L X L H L X X X X X ADDR X X X X X X X X X X X X X X X X X X X X X X X X X X X INVALID Action Exit Self Refresh --> ABI Exit Self Refresh --> ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down --> ABI Exit Power Down --> ABI ILLEGAL ILLEGAL ILLEGAL 6 NOP (Continue power down mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table 1 Begin Clock Suspend Next Cycle Enable Clock of Next Cycle Continue Clock Suspension H H H H H H H H L Any State Other than Listed Above H H L L Note: 6. Power-down and self refresh can be entered only when all the banks are in an idle state. 28/28 |
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