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Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 FEATURES * High speed parallel latches * Live insertion/extraction permitted * Extra data width for wide address/data * Power-up 3-State * Power-up reset * Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors paths or buses carrying parity * Output capability: +64mA/-32mA * Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17 * ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model DESCRIPTION The MB2841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. The MB2841 consists of two sets of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (nLE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the nLE High-to-Low transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable (nOE) is Low. When nOE is High the output is in the High-impedance state. QUICK REFERENCE DATA SYMBOL tPLH tPHL CIN COUT ICCZ PARAMETER Propagation delay nDx to nQx Input capacitance Output capacitance Total supply current CONDITIONS Tamb = 25C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC VO = 0V or VCC; 3-State Outputs disabled; VCC = 5.5V TYPICAL 3.5 4 7 120 UNIT ns pF pF A ORDERING INFORMATION PACKAGES 52-pin Plastic Quad Flat Pack (PQFP) TEMPERATURE RANGE -40C to +85C ORDER CODE MB2841BB DRAWING NUMBER 1418B PIN CONFIGURATION GND 1OE 1Q3 1Q2 1Q1 1Q0 1D0 1D1 1D2 1D3 1LE Vcc Vcc LOGIC SYMBOL 45 52 51 1Q4 1Q5 1Q6 GND 1Q7 1Q8 1Q9 2Q0 2Q1 1 2 3 4 5 6 7 8 9 50 49 48 47 46 45 44 43 42 41 40 39 1D4 38 1D5 37 1D6 36 1D7 35 1D8 44 42 41 39 38 37 36 35 34 1D0 1D1 1D2 1D3 1D4 1D5 1D6 46 47 1LE 1OE 1D7 1D8 1D9 MB2841 52-pin PQFP 34 1D9 33 2D0 32 2D1 31 2D2 30 GND 29 2D3 28 2D4 27 2D5 21 20 2Q2 10 2Q3 11 2Q4 12 2Q5 13 14 15 16 2Q6 2Q7 Vcc 17 18 19 20 2Q8 2Q9 2OE GND 21 22 23 24 25 2LE 2D9 2D8 2D7 2D6 26 Vcc August 24, 1993 E E E 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 48 33 49 32 50 31 51 29 1 28 2 27 3 25 5 24 6 23 7 22 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2LE 2OE 2D7 2D8 2D9 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 8 9 10 11 12 13 15 16 18 19 1 853-1668 10619 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 PIN DESCRIPTION PIN NUMBER 45, 44, 42, 41, 39, 38, 37, 36, 35, 34, 33, 32, 31, 29, 28, 27, 25, 24, 23, 22 48, 49, 50, 51, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 18, 19 47, 20 46, 21 4, 17, 30, 43 14, 26, 40, 52 SYMBOL 1D0 - 1D9 2D0 - 2D9 1Q0 - 1Q9 2Q0 - 2Q9 1OE, 2OE 1LE, 2LE GND VCC Data inputs Data outputs Output enable inputs (active-Low) Latch enable inputs (active rising edge) Ground (0V) Positive supply voltage FUNCTION LOGIC SYMBOL (IEEE/IEC) 47 46 EN C1 20 21 EN C1 45 44 42 41 39 38 37 36 35 34 1D 48 49 50 51 1 2 3 5 6 7 33 32 31 29 28 27 25 24 23 22 1D 8 9 10 11 12 13 15 16 18 19 FUNCTION TABLE INPUTS nOE L L L L H H= h= L= l= = NC= X= Z= nLE H H X nDx L H l h X OUTPUTS nQ0 - nQ9 L H L H Z Transparent Latched High impedance Hold OPERATING MODE L L X NC High voltage level High voltage level one set-up time prior to the High-to-Low LE transition Low voltage level Low voltage level one set-up time prior to the High-to-Low LE transition High-to-Low LE transition No change Don't care High impedance "off" state August 24, 1993 2 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 LOGIC DIAGRAM nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7 nD8 nD9 D D D D D D D D D D L Q L Q L Q L Q L Q L Q L Q L Q L Q L Q nLE nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 nQ9 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 DC output diode current DC output voltage3 VO < 0 output in Off or High state output in Low state VI < 0 CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 128 -65 to 150 UNIT V mA V mA V mA C DC output current Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER Min VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level Input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 -40 4.5 0 2.0 0.8 -32 64 5 +85 LIMITS Max 5.5 VCC V V V V mA mA ns/V C UNIT August 24, 1993 3 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C MIN VIK Input clamp voltage VCC = 4.5V; IIK = -18mA VCC = 4.5V; IOH = -3mA; VI = VIL or VIH VOH High-level output voltage VCC = 5.0V; IOH = -3mA; VI = VIL or VIH VCC = 4.5V; IOH = -32mA; VI = VIL or VIH VOL VRST II IOFF IPU/PD IOZH IOZL ICEX IO ICCH ICCL ICCZ ICC Additional supply current per input pin2 Quiescent supply current Low-level output voltage Power-up output voltageNO TAG Input leakage current Power-off leakage current Power-up/down 3-State output current4 3-State output High current 3-State output Low current Output High leakage current Output current1 VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IO = 1mA; VI = GND or VCC VCC = 5.5V; VI = GND or 5.5V VCC = 0.0V; VO or VI 4.5V VCC = 2.1V; VO = 0.5V; VI = GND or VCC; V OE = Don't care VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND -50 2.5 3.0 2.0 TYP -0.9 2.9 3.4 2.4 0.42 0.13 0.01 5.0 5.0 5.0 -5.0 5.0 -70 120 56 120 0.5 0.55 0.55 1.0 100 50 50 -50 50 -180 250 76 250 1.5 -50 MAX -1.2 2.5 3.0 2.0 0.55 0.55 1.0 100 50 50 -50 50 -180 250 76 250 1.5 Tamb = -40C to +85C MIN MAX -1.2 V V V V V V A A A A A A mA A mA A mA UNIT NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V 10% a transition time of up to 100sec is permitted. AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM MIN tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay nDx to nQx Propagation delay nLE to nQx Output enable time to High and Low level Output disable time from High and Low level 2 1 4 5 4 5 1.5 1.7 2.4 2.9 1.3 2.3 1.0 1.5 Tamb = +25oC VCC = +5.0V TYP 3.1 3.5 4.2 4.6 3.1 4.0 3.3 3.2 MAX 4.4 4.7 5.7 6.0 4.2 5.2 4.6 4.5 Tamb = -40 to +85oC VCC = +5.0V 0.5V MIN 1.5 1.7 2.4 2.9 1.3 2.3 1.0 1.5 MAX 5.0 5.3 6.5 6.7 4.9 5.9 5.1 5.0 ns ns ns ns UNIT August 24, 1993 4 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Min ts(H) ts(L) th(H) th(L) tw(H) Setup time, High or Low nDx to nLE Hold time, High or Low nDx to nLE nLE pulse width High 3 3 1 2.0 1.5 0.5 0.5 2.9 Tamb = +25oC VCC = +5.0V Typ 0.8 0.4 -0.3 -0.7 1.9 Max Tamb = -40 to +85oC VCC = +5.0V 0.5V Min 2.0 1.5 0.5 0.5 2.9 Max ns ns ns UNIT AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V nDx INPUT nLE VM VM VM tw(H) tPHL VM VM tPLH tPLH tPHL nQx VM VM nQx OUTPUT VM VM nDx VM ts(H) nLE VM Waveform 3. Data Setup and Hold Times nOE VM tPZH VM tPHZ VOH -0.3V 0V nQx VM Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. August 24, 1993 EEEEEEEEEE E EEEEEEEEEE E EEEEEEEEEE E EEEEEEEEEE E EEEEEEEEEE E VM VM VM th(H) ts(L) th(L) VM Waveform 1. Propagation Delay, Latch Enable Input to Output, and Enable Pulse Width EEE EEE EEE EEE EEE Waveform 2. Propagation Delay for Data to Outputs nOE VM tPZL VM tPLZ nQx VM VOL +0.3V Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level 5 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 TEST CIRCUIT AND WAVEFORM VCC 7.0V VIN PULSE GENERATOR RT D.U.T CL RL VOUT RL 90% NEGATIVE PULSE VM 10% tTHL (tF) tTLH (tR) 90% tW VM 10% 90% AMP (V) 0V tTLH (tR) tTHL (tF) 90% VM 10% tW 0V AMP (V) Test Circuit for 3-State Outputs POSITIVE PULSE 10% VM SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open VM = 1.5V Input Pulse Definition DEFINITIONS RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS FAMILY Amplitude MB 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns August 24, 1993 6 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 6 5 4 tPLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nDx to nQx 5 4 MAX 3 Offset in ns 4.5VCC 5.5VCC MIN 2 1 0 -1 -2 Adjustment of tPLH for Load Capacitance and # of Outputs Switching nDx to nQx 20 switching 10 switching 1 switching ns 3 2 1 0 -55 -35 -15 5 25 45 65 85 105 125 0 50 100 150 200 C tPHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nDx to nQx pF Adjustment of tPHL for Load Capacitance and # of Outputs Switching nDx to nQx 7 6 5 4 3 2 1 0 -55 -35 5 4 MAX Offset in ns 3 2 1 0 -1 -2 20 switching 10 switching 1 switching 4.5VCC 5.5VCC MIN ns -15 5 25 45 65 85 105 125 0 50 100 150 200 C tPLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nLE to nQx pF Adjustment of tPLH for Load Capacitance and # of Outputs Switching nLE to nQx 5 4 MAX Offset in ns 3 2 1 0 -1 -2 20 switching 10 switching 1 switching 8 7 6 5 4 3 2 1 -55 -35 4.5VCC 5.5VCC MIN ns -15 5 25 45 65 85 105 125 0 50 100 150 200 C pF August 24, 1993 7 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 8 7 tPHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nLE to nQx 5 4 MAX 3 Offset in ns 2 1 0 Adjustment of tPHL for Load Capacitance and # of Outputs Switching nLE to nQx 20 switching 10 switching 6 1 switching ns 5 4 3 2 -55 -35 -15 5 25 45 65 85 105 125 MIN 4.5VCC 5.5VCC -1 -2 0 50 100 150 200 C tPZH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx pF Adjustment of tPZH for Load Capacitance and # of Outputs Switching nOE to nQx 6 5 5 4 MAX 3 20 switching 10 switching Offset in ns 4 4.5VCC ns 3 5.5VCC 2 MIN 1 0 -55 -35 -15 5 25 45 65 85 105 125 -1 -2 0 50 100 150 2 1 0 1 switching 200 C tPZL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx pF Adjustment of tPZL for Load Capacitance and # of Outputs Switching nOE to nQx 7 6 5 5 4 MAX 3 Offset in ns 2 1 0 20 switching 10 switching ns 4 3 2 1 -55 -35 -15 5 25 45 65 85 105 4.5VCC 5.5VCC 1 switching MIN -1 -2 125 0 50 100 150 200 C pF August 24, 1993 8 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 6 5 4 tPHZ vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx MAX 8 7 6 5 4.5VCC Offset in ns 4 3 2 1 0 Adjustment of tPHZ for Load Capacitance and # of Outputs Switching nOE to nQx 20 switching 10 switching 1 switching ns 3 2 1 0 -55 -35 -15 5 25 45 65 85 105 5.5VCC MIN -1 -2 -3 125 0 50 100 150 200 C tPLZ vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx pF Adjustment of tPLZ for Load Capacitance and # of Outputs Switching nOE to nQx 6 5 6 5 MAX 4 Offset in ns 3 2 1 0 -1 -2 4 ns 3 2 1 0 -55 -35 -15 5 25 45 65 85 105 125 4.5VCC 5.5VCC 20 switching 10 switching 1 switching MIN 0 50 100 150 200 C tTLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching 9 7 3 5 ns 2 4.5VCC 5.5VCC Offset in ns 3 1 -1 0 -55 -35 -15 5 25 45 65 85 105 125 -3 0 50 pF Adjustment of tTLH for Load Capacitance and # of Outputs Switching 4 20 switching 10 switching 1 switching 1 100 150 200 C pF August 24, 1993 9 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 4 tTHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching Adjustment of tTHL for Load Capacitance and # of Outputs Switching 5 4 3 Offset in ns 20 switching 3 4.5VCC 5.5VCC 2 1 0 -1 10 switching 1 switching ns 2 1 0 -55 -35 -15 5 25 45 65 85 105 125 -2 0 50 100 150 200 C pF 4.0 3.5 3.0 2.5 Volts 2.0 1.5 1.0 0.5 0 0 VOHV and VOLP vs Load Capacitance VCC = 5V, VIN = 0 to 3V 125C 25C -55C 6 5 4 3 Volts 2 1 0 125C 25C -55C -1 -2 -3 VOHP and VOLV vs Load Capacitance VCC = 5V, VIN = 0 to 3V 125C 25C -55C 125C 25C -55C 50 100 150 200 0 50 100 150 200 pF pF August 24, 1993 10 |
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