View KS9287_1261061.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DIGITAL SIGNAL PROCESSOR
KS9287
KS9287
PRELIMINARY DATA SHEET
1999.6.7
1
DIGITAL SIGNAL PROCESSOR
KS9287
INTRODUCTION
The KS9287 is a Digital Signal Processor for VCD and Hi-Fi CD players. It has enhanced the picture quality of VCD. This IC, when compared to the existing product, has vastly improved its performance in the following areas. -- -- -- -- -- Frame Sync Detect Error Correcting Code Ability CLV Performance DPLL Capture Range EFM Signal Compensation
FEATURES
* * * * * * * * * * * * * EFM data demodulation Enhanced Frame sync detection/protection/insertion Error Correction (C1: double correction, C2: double correction / quadruple correction) Interpolation Subcode Data serial output Enhanced CLV servo controller Enhanced DPLL MICOM Interface Digital Audio Out Built-in 16 K SRAM 2x Playback Capability 5 V +/- 10% Single Power Supply CMOS Process
ORDERING INFORMATION
Device KS9287 Package 80-QFP-1420C Operating Temperature -20 C ~ +75 C
2
DIGITAL SIGNAL PROCESSOR
KS9287
BLOCK DIAGRAM
S0S1 SBCK SBDT
Subcode Sync Detector
Subcode Out
Subcode-Q Register
SQDT SQCK
EFMI
APDO
EFM Phase Detector
Shift Register
EFM Demodulator
VCOI CNTVOL DPFIN DPFOUT DPDO
DPLL
Fsync Detector Protector Insertor
ECC
SMEF SMON SMDP SMDS LOCK
CLV Servo
16K SRAM
XIN XOUT
X'tal Timing Generator
Address Generator
8bit data bus
MCK MDAT MLT
Micom Interface
Tracking Counter
Interpolator
TEST
Mode Selector
Digital Out
XTALSEL,DPLL, CDROM, SRAM, DSPEED
TRCNT
/ISTAT
DATX
C2PO, SADT, BCK, LRCH, WDCH
3
DIGITAL SIGNAL PROCESSOR
KS9287
PIN CONFIGURATION
DSPEED TRCNT /ISTAT SMON WBCK TEST1
65
VCOO
SMDS
SMDP
APDO
DSVO
67
SMEF
LOCK
VCOI
80
79
78
77
76
75
74
73
72
71
70
69
68
EFMI
66
VDD
VDDA DPDO DPFIN DPFOUT CNTVOL VSSA DATX XIN XOUT WDCH LRCH SADT VSS BCK C2PO TIM2 EFMFLAG UDTFLAG FSYNC EFMZ V34M TEST0 RBCK EMPH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SRAM CDROM DPLL XTALSEL /CS /WE C16M C4M /JIT ULKFS FSDW VSS /PBCK FLAG5 FLAG4 FLAG3 FLAG2 FLAG1 RD0 RD1 RD2 RD3 RD4 RD5
KS9287
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RESET
SQOK
SQEN
SQCK
MUTE
MDAT
SQDT
SBCK
SBDT
LKFS
S0S1
MCK
VDD
MLT
RD7
RD6
4
DIGITAL SIGNAL PROCESSOR
KS9287
PIN DESCRIPTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name VDDA DPDO DPFIN DPFOUT CNTVOL VSSA DATX XIN XOUT WDCH LRCH SADT VSS BCK C2PO TIM2 EFMFLAG UDTFLAG FSYNC EFMZ V34M TEST0 RBCK EMPH LKFS S0S1 RESET SQEN SQCK SQDT SQOK SBCK I/O O I O I O I O O O O O O O O O O O O I I O O O I I I/O O O I Analog VDD Charge pump output for Digital PLL Filter input for Digital PLL Filter output for Digital PLL VCO control voltage for Digital PLL Analog Ground Digital Audio Serial Output X'tal oscillator input X'tal oscillator output Word clock output of 48 bits/Slot (88.2 kHz) Channel clock output of 48 bits/Slot (44.1 kHz) Serial audio data output of 48 bits/Slot (MSB first) Digital Ground Bit clock output of 48 bits/Slot (2.1168 MHz) C2 Pointer for Serial audio data Normal or Double speed control output 8 to14 demodulation error flag Undesiable T Flag (Lower 3T signal in EFM signal) Detected Frame Sync EFM signal demodulated NRZI Internal VCO clock (34.5744MHz) Test input (H: Test, L: Normal) Read base clock Emphasis output (H: Emphasis On, L: Emphasis Off) The Lock Status output of frame sync Output of subcode sync signal (S0+S1) System reset at "L" SQCK control signal (H: External clock, L: Internal clock) Subcode-Q data bit clock Serial output of Subcode-Q data The CRC check result signal output of Subcode-Q Subcode data bit clock Description
5
DIGITAL SIGNAL PROCESSOR
KS9287
PIN DESCRIPTION (Continued)
No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name SBDT VDD MUTE MLT MDAT MCK RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 /PBCK VSS FSDW ULKFS /JIT C4M C16M /WE /CS XTALSEL DPLL CDROM SRAM I/O O I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I Subcode data serial output Digital VDD Mute control input ("H": Mute ON) Latch Signal Input from MICOM Serial data input from MICOM Serial data transfering clock input from MICOM SRAM data I/O port (MSB) SRAM data I/O port 6 SRAM data I/O port 5 SRAM data I/O port 4 SRAM data I/O port 3 SRAM data I/O port 2 SRAM data I/O port 1 SRAM data I/O port 0 (LSB) Monitoring output for ECC (RA0) Monitoring output for ECC (RA1) Monitoring output for ECC (RA2) Monitoring output for ECC (RA3) Monitoring output for ECC (RA4) VCO/2 clock output (4.3218 MHz) (RA5) Digital ground Frame Sync protection Window (RA6) Frame sync protection status (RA7) Display of either RAM overflow or underflow for 4 frame jitter margin (RA8) 4.2336 MHz signal output (RA9) 16.9344 MHz signal output (RA10) Write enable signal for external SRAM Chip select signal for external SRAM Mode Selection1 (H: 33.8688 MHz, L: 16.9344 MHz) Mode Selection2 (H: APLL, L: DPLL) Mode Selection3 (H: CD-ROM, L: CDP) Mode selection4 (H: External SRAM, L: Internal SRAM) Description
6
DIGITAL SIGNAL PROCESSOR
KS9287
PIN DESCRIPTION (Continued)
No. 65 66 67 68 69 70 Pin Name TEST1 EFMI DSVO /ISTAT TRCNT LOCK I/O I I O O I O Description TEST input terminal (GND connection) EFM signal input Digital sum value output The internal status output Tracking counter input signal Output signal of LKFS condition sampled PBFR/16 (if LKFS is "H", LOCK is "H", if LKFS is sampled "L" at least 8 times by PBFR/16, LOCK is "L") Write frame clock (Lock : 7.35 kHz) LPF time constant control of the spindle servo error signal ON/OFF control signal for spindle servo Digital VDD Spindle Motor drive (Rough control in the SPEED mode, Phase control in the PHASE mode) Spindle Motor drive (Velocity control in the PHASE mode) VCO output VCO input (8.6436MHz when locked by WBCK) Double speed mode select (H: Normal, L: 2 times) Analog PLL charge pump output
71 72 73 74 75 76 77 78 79 80
WBCK SMEF SMON VDD SMDP SMDS VCOO VCOI DSPEED APDO
O O O O O O I I O
7
DIGITAL SIGNAL PROCESSOR
KS9287
ABSOLUTE MAXIMUM RATINGS
Item Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Symbol VDD VI VO TOPR TSTG Min -0.3 -0.3 -0.3 -20 -40 Typ - - - - - Max 7.0 7.0 7.0 75 125 Unit V V V C C
ELECTRICAL CHARACTERISTICS
DC Characteristics (VDD = 5 V, VSS = 0 V, Ta = 25 C) Item 'H' Input Voltage1 'L' Input Voltage1 'H' Input Voltage2 'L' Input Voltage2 'H' Output Voltage1 'L' Output Voltage1 'H' Output Voltage2 'L' Output Voltage2 'H' Output Voltage3 'L' Output Voltage3 Input Leakage Current1 Symbol VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 ILKG1 Condition - - - - IOH=-1mA IOL=1mA IOH=-1mA IOL=1mA IOH=-1mA IOL=1mA VI=0~VDD Min 0.7VDD - 0.8VDD VDD-0.5 0 VDD-0.5 0 VDD-0.5 0 -5 Typ - - - - - - - - - - - Max - 0.3VDD - 0.2VDD VDD 0.4 VDD 0.4 VDD 0.4 5 Unit V V V V V V V V V V A All Tri-state output All input (except XIN, VCOI) XIN, VCOI SMEF, SMDP, SMDS, APDO, DPDO All bi-direction All bi-direction, MLT, MCK, MDT All output pins Related pins All input
Input Leakage Current2 Three State Output Leakage Current
ILKG2 IOLKG
VI=0~VDD VO=0~VDD
-10 -5
- -
10 5
A A
8
DIGITAL SIGNAL PROCESSOR
KS9287
AC Characteristics (1) When pulse is input to XI pin (VDD=5V, VSS=0V, Ta=25C) Item 'H' Level Pulse Width 'H' Level Pulse Width Pulse Frequency Input 'H' Level Input 'L' Level Rising & Falling Time Symbol TWH TWL TCK VIH VIL tR,tF Min 13 13 26 VDD-1.0 Typ Max 0.8 10 Unit ns ns ns V V ns
TCK tWH tWL VIH VIH X 0.9 VDD / 2 VIL X 0.1 VIL tR tF
(2) MCK, MDAT, MLT, TRCNT (VDD=5V, VSS=0V, Ta=25C) Item Clock Frequency Clock Pulse Width Setup Time Hold Time Delay Time Latch Pulse Width TRCNT, SQCK Frequency TRCNT, SQCK Pulse Width Symbol fCK1 tWCK1 tSU tH tD tW fCK2 tWCK2 Min 500 300 300 300 1000 500 Typ Max 1 1 Unit MHz ns ns ns ns ns MHz ns
9
DIGITAL SIGNAL PROCESSOR
KS9287
1/fCK1 tWCK1 tWCK1
MCK MDAT MLT
tSU tH tD tW
TRCNT SQCK
tWCK2 1/fCK2
tWCK2
SQDT
tSU tH
10
DIGITAL SIGNAL PROCESSOR
KS9287
FUNCTIONAL DESCRIPTION
MICOM INTERFACE Data input from MICOM is received in MDAT, and transmitted by MCK. This signal is stored in the Control Register by MLT. The Timing diagram for this process is shown in Figure 1 .
MDAT MCK MLT Register (9X ~ FX) Valid D0 D1 D2 D3 D4 D5 D6 D7
MDAT MCK
D0
D1
D2
D3
D4
o o
D11
D12
D13
D14
D15
MLT Register (88XX ~ 8DXX) Valid
Figure 1. MICOM Data Input Timing Diagam Table 1. Control Register and Data
Register CNTL-Z CNTL-S CNTL-L CNTL-U CNTL-W CNTL-C CNTL-D Name Data control Frame sync protect, attenuation control Tracking counter (lower) Tracking counter (upper) CLV control CLV-mode Double-speed Address D7~D4 1001 (9X) 1010 (AX) 1011 (BX) 1100 (CX) 1101 (DX) 1110 (EX) 1111 (FX) Data D3 ZCMT FSEM TRC3 TRC7 D2 HIPD FSEL TRC2 TRC6 WB D1 NCLV WSEL TRC1 TRC5 WP D0 CRCQ ATTM TRC0 TRC4 GAIN /ISTAT Pin HI-Z HI-Z /complete /count HI-Z /(Pw 64) DS2 HI-Z
CLV MODE DS1
11
DIGITAL SIGNAL PROCESSOR
KS9287
Register CNTL-F CNTL-T CNTL-E CNTL-H
Name Function control EFM Signal control Frame Sync detection control DPLL, monitor pin control
Address D11~D8 10001000 (88X) 10001011 (8BX) 10001100 (8CX) 10001101 (8DX)
Data D7
CDROM
D6
IIS
D5
D4
ERA OFF
D3
C1PNT
D2
SADT SW
D1
WDCH SEL1 VSEL
D0
WDCH SEL0 DSV INV
/ISTAT Pin HI-Z HI-Z HI-Z HI-Z
FSMD1
VCON
FWSEL
FSMD0
DUMB3
DUMB2
RBSEL
DUMB1
DUMB0
RES8
-
-
-
12
DIGITAL SIGNAL PROCESSOR
KS9287
Detail Description of Control Register 1. CNTL-Z ($9X) This register carries out the following functions: audios zero cross mute, phase pin control, phase servos control signal management, and the decision whether or not to include SQOK data in SQDT. Bit Identifier ZCMT 3 ZCMT Zero cross mute 0 1 HIPD Zero cross mute is OFF Zero cross mute is ON 2 HIPD 1 NCLV 0 CRCQ
Phase pin control 0 1 Phase operates normally Phase goes from low to Hi-Z by LKFS
NCLV
Phase servos control 0 1 Phase Servo controlled by Frame Sync Phase Servo controlled by Base Counter
CRCQ 0 1 SQDT output not including SQOK SQDT = SQOK, when SOS1 is "H".
2. CNTL-S ($AX) This register sets the frame sync protection and attenuation. FWSEL of CNTL-D is added to define window size. . Bit Identifier FSEM, FSEL 3 FSEM 2 FSEL 1 WSEL 0 ATTM
Frame sync protection 0 0 1 1 0 1 0 1 2 4 8 13
13
DIGITAL SIGNAL PROCESSOR
KS9287
FWSEL, WSEL Frame Sync protection window size 0 0 1 1 ATTM, MUTE 0 1 0 1
+/- 3T +/- 7T +/- 13T +/- 26T
Control the Frame Sync attenuation 0 0 1 1 0 1 0 1 0 dB - dB -12 dB -12 dB
3. CNTL-L, U ($BX, $CX) When the number of tracks to be counted is input from MICOM, the CNTL-L, or CNTL-U register loads the data into the tracking counter. This tracking counter is used for improving track jump characteristics. When the number of tracks to be jumped is input from MICOM, the track number is loaded from MLTs positive edge to the register. If CNTL-L is selected, /COMPLETE signal is output to the /ISTAT pin, and if CNTL-U is selected, /COUNT signal is output. The Timing Diagrams of the tracking counters are Figure-2 and Figure-3.
MLT CNTL-L, CNTL-U TRCNT /ISTAT =(/count) /ISTAT =(/complete)
N
N
N
N
N
N
Figure 2. Tracking Counter Timing Diagram
14
DIGITAL SIGNAL PROCESSOR
KS9287
MDAT MLT CNTL State CNTL State CNTL-L /complete CNTL-U /count CNTL-C /(PW > 64) Other Mode Hi-Z
Figure 3. /ISTAT Output Signal According to the CNTL Register
4. CNTL-W ($DX) Bit Identifier WB This register sets the CLV-Servos control period and gain.. 3 2 1 0 - WB WP GAIN
Bottom Hold period control in Speed-Mode 0 1 XTFT/32 XTFR/16
WP
Peak Hold period control in Speed-Mode 0 1 XTFR/4 XTFR/2
GAIN
SMDS Gain control in Speed-Mode 0 1 - 12 dB 0 dB
5. CNTL-C ($EX) This register sets the CLV-Servos operating Mode. Bit Identifier CM3 ~ CM0 3 CM3 2 CM2 1 CM1 0 CM0
Operating Mode control 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 1 1 0 0 0 0 1 0 0 Forward Reverse Speed Phase XPHSP Stop
15
DIGITAL SIGNAL PROCESSOR
KS9287
6. CNTL-D ($FX) This register sets the normal speed and double speed mode.. Bit Identifier DS1, DS0 3 Speed control 0 1 0 1 Normal Speed Double Speed (2X) 2 1 DS1 0 DS0
7. CNTL-F ($88XX) This register sets the ECC, Interpolation, communication protocol control mode. Bit Identifier 7 CDROM 6 5 4 ERA OFF 3 C1PNT 2 SADT SW 1 WDCH SEL1 0 WDCH SEL0
CDROM
Set the interpolation function On/Off 0 1 CD-DA mode (Interpolation ON)
CD-ROM mode (Interpolation OFF)
ERAOFF
Set the Erasure Correcting Feature while in Error Correcting Mode. 0 1 Erasure Correction On Erasure Correction Off
C1PNT
Set the C1 Flag Information after the C1 error correcion . 0 1 C1 flag set C1 flag reset
SADTSW
Set the Data communication protocal. 0 1 48 bits/slot mode 64 bits/slot mode
WDCHSEL1, WDCHSEL0 Set the WDCH clock mode. 0 1 88.2KHz 176.4KHz
16
DIGITAL SIGNAL PROCESSOR
KS9287
8.CNTL-M ($8AXX) This register sets the frequency error equation in CLV-P mode Bit Identifier CLVSW 7 CLVSW 6 5 4 3 2 1 0 -
Set the frequency error equation 0 1 ((tHW - 279t) + 1) * 32 (tHW - 560t) * 32
8. CNTL-T ($8BXX) This register sets the EFM Function control mode. Bit Identifier VCON 7 VCON 6 5 4 3 2 1 VSEL 0 DSVINV
Set the EFM signal compensation function mode. 0 1 Compensation OFF Compensation ON
VSEL
Select the EFM signal latck clock. 0 1 4.3218MHz 8.6436MHz
DSVINV
Set the DSV inversion output . 0 1 DSV DSV inverted
9. CNTL-E ($8CXX) This register is used for setting the RBCK output and Frame Sync protection window size. Bit Identifier RBSEL 7 RBSEL 6 FWSEL 5 4 3 2 1 0 -
FSMD1 FSMD0
Set the RBCK output 0 1 RBCK/4 RBCK
17
DIGITAL SIGNAL PROCESSOR
KS9287
FWSEL, WSEL Frame Sync protection window size (Refer to WSEL of CNTL-S register) 0 0 1 1 FSMD1, FSMD0 Set the Frame Sync Detection mode 0 0 1 1 0 1 0 1 Pattern mode detect Period mode detect Compensation mode detect Mixed mode detect (only 22T) 0 1 0 1
+/- 3T +/- 7T +/- 13T +/- 26T
12. CNTL-H ($8DXX) This register sets the Digital PLLs Processing Mode and Monitoring pin output Mode. Bit Identifier RES8 7 RES8 6 5 4 3 DUMB3 2 DUMB2 1 DUMB1 0 DUMB0
PLCK Resolution when 2X speed 0 1 PLCK = VCO * 6 PLCK = VCO * 8
DUMB3, DUMB2, DUMB1, DUMB0 Set the Monitoring Pin Output Mode 0 1 Monitoring pin output disable Monitoring pin output enable
- DUMB3 : DSVO, APDO - DUMB2 : C4M - DUMB1 : C16M - DUMB0 : EFMFLAG, UDTFLAG, EFMZ, V34M, FSYNC, FLAG5 ~ FLAG1, /PBCK, FSDW, ULKFS, /JIT
18
DIGITAL SIGNAL PROCESSOR
KS9287
EFM DEMODULATION The EFM block is composed of the following parts: EFM demodulator to demodulate the EFM signal read from the disc, EFM phase detector, and the control signal generator.
1) EFM Phase Detector The EFM signal input from the Disc includes 2.1609 MHz components. To detect the phase of this signal, a Bit Clock (/PBCK) of 4.3218 MHz is used. PBCK detects the phase of the EFM signals Edge, and sends the results to the APD0 pin.
VCOI PBCK EFMI EFMD
APDO
c
e
e
(1) When theEFM signal is slower than the VCO signal (2) When the EFM signal is locked to the VCO signal (3) When the EFM signal is faster than the VCO signal. Figure 4. EFM Phase Detector Timing Diagram 2) EFM Demodulation The modulated 14 channel bit data is demodulated into 8-bit data. There are two types of demodulated data: subcode data and audio data. Subcode data is input into the subcode handling block, and the audio data is stored in the internal SRAM, and its errors are corrected. 3) Frame Sync Detect/Protect/Insert * Frame Sync Detect Data is composed of units of frame, and a frame is composed of frame sync, subcode data, audio data, and redundancy data. This IC detects frame sync to maintain synchronization, and there are three detection methods (refer to CNTL-E Command): (1) Pattern Detect Method (2) Period Detect Method (3) Compensation Detect Method: Combination of the methods above * Frame Sync Protect/Insert There are some cases in which frame sync is not detected, or detected it from other data which does not include frame sync, due to disc error or jitter. In these cases, the frame sync must be protected and inserted. To protect frame sync, a window is made by WSEL of the CNTL-S register. The frame sync entering this window is considered valid data, and the frame sync which leaves this window is ignored. If frame sync is not detected within the frame sync protect window, insert instead the frame sync made in the internal counter. If frame sync is inserted continuously, reaching the number of frames set by FSEM and FSEL of the CNTL-S register, the following occurs: ULKFS becomes H, the frame sync protect window is ignored, and the frame sync detected next is accepted unconditionally. When a frame sync is accepted, the ULKFS signal becomes L, and accepts the frame sync detected within the window (refer to below Table).
19
DIGITAL SIGNAL PROCESSOR
KS9287
LKFS 1
ULKFS 1
Comment Play back frame sync and the generated sync coincide. 1) The play back frame sync and the generated frame sync do not coincide, but PBFR sync is detected from within the window selected by WEL. 2) PBFR sync and XTFR sync do not coincide, and are not detected from within the window selected by WSEL. Sync insert is carried out. 1) Immediately after the following situation: Frame sync is not detected within the window, so frame is inserted in the amount set by CNTL-S registers FSEM and FSEL. 2) If PBFR sync is still undetected after 1).
0
1
0
0
ECC When disc data is damaged, it is corrected using the ECC (Error Correcting Code) block. It uses the CIRC (Cross Interleaved Reed-Solomon Code), correcting up to 2 errors when C1(32, 28), and up to 4 erasures when C2(28, 24). Error correction handles the data in units of 8-bit 1 symbol. The ECC block has Pointer handling function, and can generate a C1 pointer in C1 correction, and a C2 pointer in the C2 correction. The C1 and C2 pointers output a flag about the ECC-handled data to mark it as error data. This Flag information signal is input into the interpolator, and used for handling the error data. Also, the Error correcting results can be monitored using the FALF5 ~ FLAG1 pins. Table 2. Error Correction Monitoring Flag Results Mode C1 No error C1 1 error Correction C1 2 error Correction C1 No Correction C2 No error C2 1 error Correction C2 2 error Correction C2 3 error Correction C2 4 error Correction C2 No Correction C2 No Correction
Note:
FLAG5 0 0 0 0 1 1 1 1 1 1 1
FLAG4 0 0 0 1 0 0 0 0 0 1 1
FLAG3 0 0 0 1 0 0 0 0 1 1 1
FLAG2 0 0 1 1 0 0 1 1 0 1 1
FLAG1 0 1 0 1 0 1 0 1 0 0 1
Remark C1 Correction start C1 flag set C2 Correction start C1 flag copy C2 flag set
When carrying out forward or backward fast search, MICOM must give the Attenuation, or the MUTE command to the DSP IC. If not, an error can occur when carrying out erasure correction during fast search.
20
DIGITAL SIGNAL PROCESSOR
KS9287
CLV SERVO CNTL-C, E, G1, G2, and G3 registers are selected to control the CLV (Constant Linear Velocity) servo using the data input from MICOM. Also, the design is such that the servo control is stable when setting the speed. When setting the speed, the /(Pw64) signal can be detected from the /ISTAT pin only if the CNTL-D register is first set before the CNTL-C register is selected. 1) Forward This mode rotates the spindle motor in the forward direction. The related output pin status are as follows. SMDP H 2) Reverse This mode rotates the spindle motor in the reverse direction. The related output pin status are as follows. SMDP L SMDS Hi-Z SMEF L SMON H SMDS Hi-Z SMEF L SMON H
3) Speed-mode This mode is used for rough control of the spindle motor when the track jump or EFM phase is unlocked. If one period of VCO is T, the pulse width of the frame sync is 22T. There are some cases in which the signal detected in the EFM signal is larger than 22T because of disc noise. If you do not eliminate this signal, the correct frame sync cannot be detected. In that case, the EFM signals pulse width is detected using the period of the peak hold clock RBCK/2 or RBCK/4. Also, detect the EFM signals pulse width using the period of the bottom hold clock RBCK/16 or RBCK/32. SMDP H: Accelerate L: Decelerate Hi-Z: Maintain 5) Phase-Mode This mode controls the EFM phase. It detects and outputs to the SMDP pin, the WBCK/4 and RBCKs phase difference, when in CLV Normal Control mode and when CNTL-Z registers NCLV is "L" (refer to Figure-5). If VCO/ 2s signal period is T, the amount of time during which WBCK is "H" is called t HW, and FRSLP is "0", "H" is output from WBCKs negative edge to the SMDS pin during (tHW - 279T) +1 x 32 or (tHW - 560T) x 32 and "L" is output until the next WBCKs negative edge (refer to Figure 5). SMDP H: Accelerate L: Decelerate Hi-Z: Maintain SMDS H/L SMEF L SMON H SMDS Hi-Z SMEF L SMON H
21
DIGITAL SIGNAL PROCESSOR
KS9287
6) Stop This mode stops the spindle motor. SMDP L SMDS Hi-Z SMEF L SMON L
1) SPEED mode P22T N22T SMDP deceleration
under 22 t = 22 t
acceleration
over 22 t
2) PHASE mode - Phase Error Signal
RBCK/4 WBCK/4 DOWN UP SMDP
- Frequency Error Signal CLV_SW = 0 : Frequency Error Signal = ( tHW - 279 t ) + 1* 32
tHW 287 t tHW 294 t
WBCK SMDS
288t 512 t
CLV_SW = 1 : Frequency Error Signal = ( tHW - 560 t ) * 36
tHW 570 t tHW 580 t
WBCK SMDS
360 t 720 t
Figure 5. SMDS, SMDP Output Timing Diagram in Normal Control Mode
22
DIGITAL SIGNAL PROCESSOR
KS9287
SUBCODE The subcode sync signals S0 and S1 are detected in the Subcode sync block. S1 is detected one frame after S0 is detected. At this time, S0+S1 signal is output to the S0S1 pin, and when the S0S1 signal is H, the S0S1 signal is output to the SDAT pin. Out of the data input into the EFMI pin, the 14-bit subcode data is EFM demodulated to 8bit (P, Q, R, S, T, U, V, W) subcode data, synchronized with the WBCK signal , and output to SDAT by the SBCK clock. Out of the 8 subcode data, only Q data is stored in the 80 shift registers by the WBCK signal. If the CRC result is error, L is output to the SQCK pin, and if not, H is output. If the CNTL-Z registers CRCQ is H, the CRC result is output to the SQDT pin from when the S0 and S1 are H to SQCKs negative edge. The Subcode blocks timing diagram is as follows: 1) The Timing Relation of SQCK, SQDT and S0S1 when SQEN=H * If subcode-Q datas CRCQ is H, the SQOK signal is output to SQDT according to the SQCK, and if CRCQ is L, the SQOK signal is not output to SQDT..
S0S1
o o o o
SQOK(n) Q4 Q3 Q2 Q1 Q8 Q7 Q6 Q5
SQOK
SQCK SQDT
(CRCQ=1)
o o o o
Q80
Q79
Q78
Q77
SQCK(n+1)
Q4
Q3
SQDT
(CRCQ=0)
0
Q4
Q3
Q2
Q1
Q8
Q7
Q6
Q5
Q80
Q79
Q78
Q77
0
Q4
Q3
Figure 6. Subcode-Q Timing Diagram 1 2) The Timing Relation of SQCK, SQDT, and S0S1 when SQEN=H
SQCK S0S1
o o o o
Q97 SQOK Q1 Q2 Q3 Q4 Q5 Q6
SQOK
SQDT
o o
Q93
Q94
Q95
Q96
Q97
SQOK
Q1
Q2
Figure 7. Subcode-Q Timing Diagram 2
23
DIGITAL SIGNAL PROCESSOR
KS9287
3) Timing Relation of SDAT and SBCK
WBCK a SBCK 1 2 3 4 5 6 7 8
SDAT
b
Q
R
S
T
U
V
W
C
a) After PBFR goes negative edge, SBCK is set to L for about 10 us. b) If S0S1 is L, subcode P is output, and if S0S1 is H, S0S1 is output. c) If there are more than 7 pulses input into the SBCK pin, the subcode data P, Q, R, S, T, U, V, and W data are output repeatedly.
Figure 8. Subcode-Q Data Output Timing Diagram 3
24
DIGITAL SIGNAL PROCESSOR
KS9287
INTERPOLATION / MUTE Interpolator If a burst error occurs on the disc, sometimes data cannot be corrected even if you carry out the ECC process. The Interpolator block uses the ECCs C2 pointer to interpolate the data. The audio data is input into the Data bus in the following order: for each L/R-ch: 8-bit C2 point, lower data 8-bit, and upper data 8-bit. If C2P0 pin is H, and one error has occurred, the average value interpolation is carried out, and if 3 consecutive errors occurred, the previous value hold interpolation is carried out. For one period of LRCH, if LRCH is L, R-ch data is output, and if H, L-ch data is output. Please refer to Figure 7 for the Interpolator blocks Timing Chart.
A B C H G D E F I J
C2 Pointer
B : Average value Interpolation F , E , D : Previous value Hold Interpolation G : Average value Interpolation Figure 9. Interpolation Method Mute/Attenuation The audio data can be muted or weakened by the ATTM signal of the MUTE pin and CNTL-S register. * Zero Cross Mute The audio data is muted when the CNTL-Z registers ZCMT is H, mute is H, and the upper 6 bits of audio data are all H. *Muting The audio data is in Muting is the CNTL-Z registers ZCMT is L and the Mute pin is H. *Attenuation Audio signal is weakened by the CNTL-Z registers ATTM and Mute signal.
25
KS9287
LRCH
1 2 24 25
48
1
BCK WDCH SADT R-CH (MSB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L-CH (MSB) 15 14 13 12 11 10 9 8
7
6
5
4
3
2
1
0
For 64 bits/slot
LRCH
1 2 16 24 25 32
BCK WDCH
DIGITAL SIGNAL PROCESSOR
SADT
L-CH (LSB) 0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R-CH (LSB) 0
1
2
Figure 10. Serial Audio Data Output Timing Diagram
For 48 bits/slot
26
DIGITAL SIGNAL PROCESSOR
KS9287
DIGITAL AUDIO OUT This block serially outputs 2 channel and 16-bit data with the digital audio interface format as reference. 1) Digital audio interface format for CD
191 R
0L
0R
1L
1R
190 L
190 R
191L
191R
0L
-R
T 192 T
0L: L-ch format including the block sync preamble 1L ~ 191L: L-ch format including the L-ch sync preamble 0R ~ 191R: R-ch format including the R-ch sync preamble
1 LRCH
Left Channel Right Channel
Preamble
Modulated "0" 8-bit
Modulated 16-bit audio data
V
U
C
P
control signal
Figure 11. Digital Audio Out Format * Preamble The Preamble is used to distinguish the datas block and L/R ch data . 8.4672 MHz L-ch. sync (except block sync) R-ch. sync
Block sync (L-ch.) Figure 12. Preamble Signal
27
DIGITAL SIGNAL PROCESSOR
KS9287
* Control Signal (1) Validity bit: shows the presence of error in 16-bit audio data: "H"=error, "L"=valid data (2) User definable bit: subcode data out
SOS1
PBFR
SBCK
SBDT
Sync Pattern
P
Q
R
S
T
U
V
W
Figure 13. Digital Audio Data Out Timing Diagram (3) Channel status bit: subcode-Qs upper 4-bit data output, shows number of channels, pre-emphasis, copy, CDPcategory, etc.
SOS1
SQDT
ID0 ID1 COPY EMPH
PBFR
Figure 14. Channel Status Data Out Timing Diagram (4) Parity Bit: makes even parity
28
DIGITAL SIGNAL PROCESSOR
KS9287
DIGITAL PLL This IC has a built-in analog PLL and a digital PLL to generate a stable channel clock needed during EFM signal demodulation. Figure-15 shows the DPLL application.
Frequency Synthesizer X'tal
Phase Comparator Low Pass Filter Voltage Cotrolled Oscillator
1/N Devider
Digital Main PLL
EFMI
Figure 15. Application Diagram of Digital PLL
/PBCK
29

▲Up To Search▲

Price & Availability of KS9287

	To Download KS9287 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .