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PD - 94336c
IP1001
Full Function Synchronous Buck Power Block
Integrated Power Semiconductors, Control IC & Passives
Features
* * * * * * * * * * 3.3V to 12V input voltage1 20A maximum load capability, with no derating up to TPCB = 90C 5 bit DAC settable, 0.925V to 2V output voltage range 2 Configurable down to 3.3Vin & up to 3.3Vout with simple external circuit 3 200kHz or 300kHz nominal switching frequency Optimized for very low power losses Over & undervoltage protection Adjustable lossless current limit Internal features minimize layout sensitivity * Very small outline 14mm x 14mm x 3mm
IP1001 Power Block
Description The IP1001 is a fully optimized solution for high current synchronous buck applications requiring up to 20A. The IP1001 is optimized for single-phase applications, and includes a full function fast transient response PWM control, with an optimized power semiconductor chip-set and associated passives, achieving benchmark power density. Very few external components are required, including output inductor, input & output capacitors. Further range of operation to 3.3Vin can be achieved with the addition of a simple external boost circuit, and operation up to 3.3Vout can be achieved with a simple external voltage divider. iPOWIR technology offers designers an innovative board space-saving solution for applications requiring high power densities. iPOWIR technology eases design for applications where component integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat transfer and component selection. IP1001 Internal Block Diagram
VIN D0 D1 5 Bit D2 DAC D3 D4 ENABLE PGOOD ILIM FREQ VDD
PWM & Driver
VSW
SGND
GNDS
VFS
VF PGND
* Although, all of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR block, proper layout techniques should be applied for the design of the power supply board. There are no concerns about unwanted shutdowns common to switching power supplies, if operated as specified. The iPOWIR block will function normally, but not optimally without any additional input decoupling capacitors. Input decoupling capacitors should be added at Vin pin for stable and reliable long term operation. No additional bypassing is required on the Vdd pin. See layout guidelines in datasheet for more detailed information.
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IP1001
Parameter VIN to PGND VDD to PGND VFS VF D0-D4 PGOOD to PGND ENABLE to PGND ILIM FREQ Output RMS Current Block Temperature
All specifications @ 25C (unless otherwise specified)
Absolute Maximum Ratings
Symbol Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -40 Typ Max 16.0 6.0 VDD+0.3 VDD+0.3 VDD+0.3 6.0 6.0 VDD+0.3 VDD+0.3 20 125 Units Conditions
V
TBLK
A C
Recommended Operating Conditions
Parameter Supply Voltage Input Voltage Range 1 Output RMS Current from VSW 4 Output Voltage Range 2 Symbol VDD VIN IoutVSW VOUT Min 4.5 3.3 0.925 Typ Max 5.5 12 20 2.0 Units V A V
DAC Setting see VID code, Table1.
Conditions
With 4.5VElectrical Specifications @ VDD = 5V & TPCB 0C - 90C (Unless otherwise specified)
Parameter Power Loss Over Current Shutdown Soft Start Time Output Voltage Accuracy VF Input Resistance Frequency VDD Undervoltage Lockout Output Undervoltage Shutdown Threshold Output Undervoltage Protection Blanking Time Output Overvoltage Shutdown Threshold at VF PGOOD Trip Threshold PGOOD Leakage Current PGOOD Output Low Voltage Logic Input High Voltage Logic Input Low Voltage PGOOD FREQ Symbol PLOSS Min -2 2.4 Typ 3.1 25 1.8 181 200 300 4.2 0.8 20 2.25 VDAC -5% 1 Max 3.9 2 0.4 0.8 Units W A ms % k kHz V V ms V V A V V V
ENABLE going high on start-up See OVP note in Design Guidelines At VF PGOOD output high Forced to 5.5V Isink = 1mA D0-D4, Enable D0-D4, Enable freq pin connected to VDD freq pin floating 200mV hysteresis All DAC codes T BLK = -40C to 125C
Conditions
300kHz, 12VIN, 1.3Vout, 20A VIN=12V, VOUT=1.3V, FREQ=300KHz, RLIM =340k
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IP1001
Electrical Specifications (continued)
Parameter VDD Operating Current VDD Quiescent Current VIN Quiescent Current ILIM to SGND Internal Resistance Symbol IVDD IQVDD IQVIN Min Typ 25 600 300 Max 1 Units mA A mA k Conditions
Enable High, 300kHz Shutdown mode Enable Low, VIN = 12V Measured ILIM pin to SGND
Notes : 1 For Vin less than 4.5V requires external 5VDD supply. 2 Can be modified to operate up to 3.3VOUT, outside of DAC settable range. See Design Guidelines on how to set 3 4
output voltage greater than 2V. See design guidelines. See Fig. 5 for Recommended Operating Area
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IP1001
Guaranteed Performance Curves
5.0 4.5 4.0
Output Current (A)
VIN = 12V VOUT = 1.3V TBLK=125C fsw set to 300kHZ Maximum
22 20 18 16 14 12 10 8 6 4 2 0
VIN = 12V VOUT = 1.3V fsw set to 300kHZ
Power Loss (W)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0
Safe Operating Area
Typical
2
4
6
8
10
12
14
16
18
20
0
10
20
30
40
50
60
70
80
90 100 110 120 130
Output Current (A)
PCB Temperature (C)
Fig 1. Power Loss vs Current
Fig 2. Safe Operating Area (SOA) vs TPCB
Adjusting the Power Loss and SOA curves for different operating conditions
To make adjustments to the power loss curves in Fig. 1, multiply the normalized value obtained from the curves in Figs. 3, or 4 by the value indicated on the power loss curve in Fig. 1. If multiple adjustments are required, multiply all of the normalized values together, then multiply that product by the value indicated on the power loss curve in Fig. 1. The resulting product is the final power loss based on all factors. To make adjustments to the SOA curve in Fig. 2, determine the maximum allowed PCB temperature in Fig. 2 at the required operating current. Then, add the correction temperature from the normalized curves in Figs. 3 or 4 to find the final maximum allowable PCB temperature. When multiple adjustments are required, add all of the temperatures together, then add the sum to the PCB temperature indicated on the SOA graph to determine the final maximum allowable PCB temperature based on all factors. Note: If input voltage <5Vin nominal operation is required then first see Fig. 5 for maximum current capability limit. Operating Conditions for the examples below: Output Current = 20A Output Voltage = 2.5V Adjusting for Maximum Power Loss: (Fig. 1) (Fig. 3) (Fig. 4) Maximum power loss =5 W Normalized power loss for output voltage 1.14 Normalized power loss for input voltage 0.89 Adjusted Power Loss = 5W x 0.89 x 1.14 5.07W Adjusting for SOA Temperature: (Fig. 2) (Fig. 3) (Fig. 4) SOA PCB Temperature = 90C Normalized SOA PCB Temperature for output voltage -4.5C Normalized SOA PCB Temperature for input voltage 4C Adjusted SOA PCB Temperature = 90C + 4C -4.5C 89.5C Input Voltage = 7V
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IP1001
Typical Performance Curves
1.36 1.30 V IN = 12V IOUT = 20A f sw set to 300kHz TBLK = 125C -13 -11 -9 -6 -4 -2 0 2 4 3.3
1.00 0.97 V OUT = 1.3V IOUT = 20A f sw set to 300kHz TBLK = 125C
0 1 2 3 4 5 6 3 4 5 6 7 8 9 10 11 12
SOA PCB Temperature Adjustmentltage (C)
SOA PCB Temperature Adjustmentltage (C)
Power Loss (Normalized)
Power Loss (Normalized)
1.24 1.18 1.12 1.06 1.00 0.94 0.88 0.9
0.94 0.91 0.89 0.86 0.83
1.3
1.7
2.1
2.5
2.9
Output Voltage (V)
Input Voltage (V)
Fig 3. Normalized Power Loss vs VOUT
25
Fig 4. Normalized Power Loss vs VIN
20
Load Current (A)
VIN = 5V to 12V 200kHz/300kHz VIN = 3.3V, 200kHz
15
10
For 200kHz frequency setting there will be a 10% power loss reduction and a positive PCB temperature adjustment of 3C.
5
0 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
Output Voltage (V)
Fig 5. Recommended Operating Area
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IP1001
D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT VOLTAGE(V) 2.00 1.95 1.90 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 Shutdown* 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 Shutdown*
* Shutdown : Upon receipt of the shutdown code (per VID code table above), both FETs are turned OFF and the output is discharged as the undervoltage protection is activated.
Table 1. VID Code Table2 2
Current Limit Resistor Rlim in kOhms
900 800 700 600 500 400 300 200 100 0 6 11 16 21 26 31 36 Typical Current Limit Setting in Amps
Fig 6. Overcurrent adjustment settings using RLIM 6 www.irf.com
IP1001
Pin N am e V IN Ball D esignator A 9-A 12, B9-B12, C 9C 14, D 9-D 14, E 9-E 16, F9-F16, G9-G 16 A 1, A 6-A7, A 13-A 15, B1, B6-B7, B13-B16, C 3, C 6-C 7, C 15-C 16, D 3-D 4, D6, D 15-D 16 E 3-E6, F1-F5, G 1-G 5, H1-H5, J1-J2, J6-J8, K 6-K 8, L6-L8, M 6-M 8, N 4-N 5, N7-N 8, P4-P5, P7-P8, R6-R8, S6-S8 H9-H14, J11-J14, K 11K 14, L11-L14, N 11N 14, M 11-M 14, P11P14, R11-R14, S11-S14 H15-H16, J15-J16, K 9K 10, K15-K 16, L9L10, L15-L16, M 9M 10, M 15-M 16, N 9N 10, N15-N 16, P9-P10, P15-P16, R9-R10, R15R16, S9-S10, S15-S16 R4-R5, S4-S5 A 2-A 3, B2-B3 E1 R3, S3 R2, S2 R1, S1 C 1-C 2 D 1-D 2 P1-P2 N 1-N 2 M 1-M 2 L1-L2 K 1-K 2 A 5, B5, C 5 A 4, B4 Pin D escription In put voltage conn ection n ode.
NC
N o electrical conn ection .
V SW
O utput inductor conn ection n ode.
PG N D
Pow er groun d.
V DD SG N D GNDS E N A BLE NC PG O O D VF V FS D0 D1 D2 D3 D4 ILIM FRE Q
C on trol Power con n ection n ode Sign al groun d. Rem ote G roun d Sen se Pin. C onn ect to PG N D for V O U T > 2V C om m an ds output O N or O FF. A ctive floatin g (in tern ally pulled h igh). W h en logic low, th e syn chron ous M O SFET is turn ed O N. N o electrical conn ection , intern ally pulled high, m ust leave floatin g. Internally pulled-up to V D D . O utput voltage feed back local sen se. O utput voltage rem ote sen se feedback sign al. For greater than 2V O UT , disconn ect from rem ote load an d conn ect to V F .
V ID code settin g D /A inputs. Internally pulled high.
C urrent lim it thresh old setting pin. See ILIM curve for extern al resistor values. Switch in g frequen cy selector pin. Floating selects 300kHz, tied to V D D selects 200kHz.
Table 2. Pin Description www.irf.com 7
IP1001
Average VDD Current Average VDD Voltage
A V
Average Input Current Average Input Voltage
A
PIN = VIN Average x IIN Average PDD = VDD Average x IDD Average POUT = VOUT Average x IOUT Average PLOSS = (PIN + PDD) - POUT
DC
DC
V
VDD
VIN
VO VSW
VOS
Average Output Current
A
PGOOD
D4 D3 D2 D1 D0 FREQ ENABLE ILIM
Averaging Circuit
IP1001
V
Average Output Voltage
VF
VFS
SGND
PGND
GNDS
Fig 7. Power loss test circuit
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IP1001
SGND FREQ NC VF NC VFS GNDS NC NC NC NC NC NC NC NC NC NC NC NC NC D4 D3 D2 D1 D0 NC NC NC NC NC NC NC NC NC NC NC VDD NC NC PGND VSW PGND ILIM NC NC NC NC VIN NC NC NC NC
PGOOD ENABLE
Fig 8. Recommended PCB Footprint (Top View) www.irf.com 9
IP1001
IP1001 User's Design Guidelines
The IP1001 is a 20A power block that consists of optimized power semiconductors, PWM control and its associated passive components. It is based on a synchronous buck topology and offers an optimized solution where space, efficiency and noise caused by stray parasitics are of concern. The IP1001 components are integrated in a ball grid array (BGA) package where the electrical and thermal conduction is accomplished through solder balls. FUNCTIONAL DESCRIPTION VIN The standard IP1001 operating input voltage range is 5V to 12V. The input voltage can also be easily configured to run at voltages down to 3.3V. FREQ The PWM control is pseudo current mode. The ESR of the output filter capacitor is used for current sensing and the output voltage ripple developed across the ESR provides the PWM ramp signal. IP1001 offers two switching frequency settings, 200kHz and 300kHz. At a given setting the switching frequency will remain relatively constant independent of load current. VDD (+5V bias) An external 5V bias supply is required to operate the IP1001. In applications where input voltages are lower than 4.5V, and where 5V is not available, a special boost circuit is required to supply VDD with 5V (as shown in the reference design). Soft Start, VDD Undervoltage Lockout When VDD rises above 4.2V a soft start is initiated by ramping the maximum allowable current limit. The ramp time is typically 1.8ms. An external capacitor can be added across the current limit resistor from ILIM to PGND to provide up to 5ms ramp time. Select the capacitor according to the 10nf/ms rule. PGOOD The PGOOD comparator constantly monitors VF for undervoltage. A 5% drop in output voltage can cause PGOOD to go low. PGOOD pin is internally pulledup to VDD through a 100K, 5% resistor. If it is desired to use the PGOOD signal to enable another stage using IP1001, then it is recommended to filter and buffer PGOOD to prevent transients appearing at the output from pulling PGOOD low. OVP (Output Overvoltage Protection) If the overvoltage trip 2.25V threshold is reached, the OVP is triggered, the circuit is shutdown and the bottom FET is latched on discharging the output filter capacitor. Pulling ENABLE low resets the latch. The overvoltage trip threshold is scaled accordingly, if output voltages greater than 2V are set through voltage dividers. UVP (Output Undervoltage Protection) The Output Undervoltage Protection trip threshold is fixed at 0.8V. If ENABLE is pulled up and VF is below 0.8V for a duration of 10-20ms, the PWM will be in a latched state, with the bottom FET latched on, and will not restart until ENABLE is recycled. DAC Converter (D0-D4) The output voltage is programmed through a 5-bit DAC (see the VID code in table 1). The output voltage can be programmed from 0.925V to 2V. To eliminate external resistors, the DAC pins are internally pulled up. To set for output voltages above 2V, the DAC must be set to 2V and a resistor divider, R3 & R4 (see Fig 10.), is used. The values of the resistors are selected using equation 1.
Equation 1 : Vout = VF
x
(1 + R3/R4)
where VF is equal to the DAC setting and R4 is recommended to be ~1k
ENABLE Low High High High Bottom FET ON OFF Switching ON Mode Shutdown Shutdown PW M (Running) Fault Fault latch set by OVP or UVP. This mode will sustain until V DD is cycled or ENABLE is reset. DAC code = X1111, Both FETs are turned OFF. Com me nts
Table 3 - IP1001 Operating Truth Table 10 www.irf.com
IP1001
DESIGN PROCEDURE Inductor Selection The inductor is selected according to the following expression. L = VOUT x (1-D) / (fsw x IL) where, D = V
OUT
A 470F POSCAP capacitor has a maximum 35m of ESR which provides 9.7kHz zero frequency. The ESR zero frequency must be set below 12kHz. This value is calculated assuming the capacitor datasheet maximum ESR value. Example: To determine the amount of capacitance to meet a 30mVp-p output ripple, with 4A inductor current ripple requirement. The calculated ESR will be = 30mV/4A = 7.5m. This will require 5 x 470uF POSCAP capacitors. The total ESR will result in a 9.7kHz zero frequency. For stable operation: * Set the resonant frequency fo of the output inductor and capacitor between 2kHz and 4kHz. The resonant frequency is calculated using the following expression: fo = 1/ (2 x (LC))
/V
IN
VOUT is the output voltage in Volts, fsw is the switching frequency in kHz, IL is the output inductor ripple current. The inductor value should be selected from 0.8H to 2.0H range. Output Capacitor Selection Use tantalum or POSCAP type capacitors for IP1001. Selection of the output capacitors depends on several factors. * Low effective ESR for ripple and load transient requirements. * Stability. To support the load transients and to stay within a specified voltage dip V due to the transients, ESR selection should satisfy the following equation: RESR V/I where, I is the transient load step If output voltage ripple is required to be maintained at specified levels then, the following expression should be used to select the output capacitors. RESR Vp-p / IL where, Vp-p is the peak to peak output voltage ripple. The value of the output capacitor ESR zero frequency also determines stability. The value of the ESR zero frequency is calculated by the expression: RESR = 1 / (2 x fESR x COUT)
* Select the output inductor value between 0.8H
to 2.0H and the output capacitance between 1880F (4x 470F) and 5600F (12x470F)
* Set the minimum output ripple voltage to be greater than 0.5% of the output voltage. Select the capacitor by ESR and by voltage rating rather than capacitance.
External Input Capacitor Selection The switching currents impose RMS current requirements on the input capacitors. The following expression allows the selection of the input capacitors, based on the input RMS current: IRMS = ILOAD where, D = VOUT/VIN
x
( D x (1-D))
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IP1001
Application Issues Setting VOUT above 2V In certain applications where the output voltage is required to be set higher than the maximum DAC code setting of 2V, it is possible to use an external resistive voltage divider which, for accuracy, needs to have 1% or better tolerance. The switching frequency should be set at 200kHz by connecting the FREQ pin to VDD. Also, the output voltage should never be set higher than 3.3V with a VIN minimum of 5V, or 2.5V with a VIN minimum of 3.3V. The DAC code should be set to 2V and the following equation used to select the resistors: VOUT = VF
x
(1 + R3/R4)
See the reference design for reference designators. Note that the impedance at VF is 180K 35%. It is recommended that R3 be calculated assuming a value of 1k for R4. Connect VFS to VF and GNDS to PGND. Duty Cycle D = VOUT / VIN >50% For duty cycles >50% the switching frequency should be set at 200kHz. 300kHz switching frequency can be selected if the output is less than 2V and the duty cycle is <50%. For duty cycles >50%, add external compensation ramp from the Vsw terminal of the IP1001 device as shown in the reference design through R9 resistor and C21 capacitor (Fig 10a.). For optimum performance maintain a RC time constant of approximately 5s.
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IP1001
Layout Guidelines
For stable and noise free operation of the whole power system it is recommended that the designer uses to the following guidelines. 1. Follow the layout scheme presented in Fig.9. Make sure that the output inductor L1 is placed as close to the IP1001 as possible to prevent noise propagation that can be caused by switching of power at the switching node VSW, to sensitive circuits. 2. Provide a mid-layer solid ground with connections to the top layer through vias. The two PGND pads of the IP1001 also need to be connected to the same ground plane through vias. 3. Do not connect SGND pins of the IP1001 to PGND. 4. To increase power supply noise immunity, place input and output capacitors close to one another, as shown in the layout diagram. This will provide short high current paths that are essential at the ground terminals. 5. Although there is a certain degree of V IN bypassing inside the IP1001, the external input decoupling capacitors should be as close to the device as possible. 6. In situations where the load is located at an appreciable distance from the IP1001 block, it is recommended that at least one or two capacitors be placed close to the IP1001 to derive the V F signal. 7. The VF connection to the output capacitors should be as short as possible and should be routed as far away from noise generating traces as possible. 8. VFS & GNDS pins need to be connected at the load for remote sensing. If remote sensing is not used connect VFS to VF and GNDS to PGND. 9. Refer to IR application note AN-1029 to determine what size vias and what copper weight and thickness to use when designing the PCB.
IP1001 Block
Input Caps (CIN)
VIN
Input Terminal
PGND PGND VSW
Output Caps (COUT) Load Terminal
VOUT
Output Inductor (L1)
Fig 9. IP1001 suggested layout
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IP1001
IP1001 Reference Design
The schematics in Fig.10a & 10b and complete Bill of Materials in Table 4 are provided as a reference design to enable a preliminary evaluation of IP1001. They represent a simple method of applying the IP1001 solution in a synchronous buck topology. Fig. 10a shows the implementation for <5V IN nominal applications, and Fig. 10b shows the implementation for 5V IN - 12V IN nominal applications. The connection pins are provided through the solder balls on the bottom layer of the package. A total power supply solution is presented with the addition of inductor L1 and the output capacitors C11-C14. Input capacitors C1-C10 are for bypassing in the 5VIN - 12VIN application, but only C1-C3 are required for <5VIN applications (refer to the BOM for values). Switches 1-5 of SW1 are used to program the output voltage. Refer to the VID table provided in this datasheet for the code that corresponds to the desired output voltage. Resistors R2 & R4 need to be removed for operation at standard VID levels (0.925V - 2.0V, leave R3 = 0). Switch 8 of SW1 enables the output when floating (internally pulled high). The 5V VDD power terminal and input power terminals are provided as separate inputs. They can be connected together if the application requires only 5V nominal input voltage. The reference design also offers a higher output voltage option for greater than 2.0V, up to 3.3V. For output voltages above 2V, the DAC setting must be set to 2V, and then select resistors R3 & R4 per Equation 1 on page 10 for the desired output voltage. Remove R5 and connect VF to VFS through R2, where R2=0. In this case, GNDS should be referenced to PGND. Tighter regulation can be achieved by using resistors with less than 1% tolerance. For Vin < 5V and Vout > 2V, the frequency select pin (FREQ) must be set to 200kHz (connected to VDD). For applications with VIN < 5V and where there is no auxiliary 5V available, connections JP2 and JP3 must be provided in order to enable the boost circuit. This will provide 5V VDD necessary for the IP1001 internal logic to function. The boost circuit will convert 3.3V input voltage to 5V, to power the VDD, and will provide enough power to supply the internal logic for up to five IP1001 power blocks. 14 www.irf.com
IP1001
1 2 3 4
1
U2
FB LBI LBO REF OUT LX GND SHDN
Optional
8 7 6 5
L2 22H C20 1F
1
C17 10F
C18 10F
JP3
2
C19 0.1F R8 100K
MAX1675
JP2
VIN
1
JP1
3.3-4.5V
2
2
C1 C2 C3 100uF 100uF 100uF 6.3V 6.3V 6.3V TP1
+5V
U1
VDD VIN
VSW
L1 1.06uH
VO
VOS
TP4
VOUT
R1
0
TP3
PGOOD
+5V
1 2 3 4 5 6 7 8
SW1
C11 C12 C13 C14 470uF 470uF 470uF 470uF 6.3V 6.3V 6.3V 6.3V
PGND
C16 0.1F
D1 10MQ040N
PGND
16 15 14 13 12 11 10 9
D4 D3 D2 D1 D0 FREQ ENABLE
IP1001 IP1001
R9 91K C21 47pF
R3 R4
TP5 R5 R6 0
ILIM
R7 340K, 1%
VF
R2
VFS GNDS
SGND
PGND
TP2
Fig 10a. - Reference Design Schematic For <4.5VIN
VIN
5-12V
C1 10uF 25V TP1
+5V
C2 10uF 25V
C3 10uF 25V
C4 10uF 25V
C5 10uF 25V
C6 10uF 25V
C7 10uF 25V
C8 10uF 25V
C9 C10 10uF 10uF 25V 25V
U1
VDD VIN
VSW
L1 1.06uH
VO
VOS
TP4
VOUT
R1
0
TP3
PGOOD
+5V
1 2 3 4 5 6 7 8
SW1
C11 C12 C13 C14 470uF 470uF 470uF 470uF 6.3V 6.3V 6.3V 6.3V
PGND
C16 0.1F
D1 10MQ040N
PGND
16 15 14 13 12 11 10 9
D4 D3 D2 D1 D0 FREQ ENABLE
IP1001
R3 R4
TP5 R5 R6 0
ILIM
R7 340K, 1%
VF
R2
VFS GNDS
SGND
PGND
TP2
Fig 10b. - Reference Design Schematic For 5VIN - 12VIN Nominal www.irf.com 15
IP1001
IRDCIP1001-A (For operation <4.5VIN)
Designator Value C1, C3, C5 100uF C2, C4, C6, C7, C8, C9, C10, C15 C11, C12, C13, C14 470uF C16, C19 0.100uF C17, C18 10.0uF C20 1.00uF C21 47.0pF D1 40V JP1, JP2, JP3 JP1-1, JP2-1, JP3-1 L1 1.06uH L2 22uH R1 0 R2 R3 R4 R5 R6 R7 R8 R9 SW1 TP1, TP3 TP2, TP4, TP5 U1 U2 0 340k 100k 91k Part Type Capacitor, 6.3V, 20%, X5R Not Installed Capacitor, 6.3V, 20%, Tantalum Capacitor, 50V, 10%, X7R Capacitor, 16V, 10%, X5R Capacitor, 10V, 10%, X7R Capacitor, 50V, 5%, C0G Schottky Diode, 40V, 2.1A Test Point Shunt Inductor, 16A, 20%, Ferrite Inductor, 0.68A, 20%, Ferrite Resistor, 0 Jumper For <2Vout, Not installed For >2Vout, Resistor, 0 Jumper For <2Vout, Resistor, 0 Jumper For >2Vout see formula for value For <2Vout, Not installed For >2Vout recommend 1k see formula for detail For <2Vout, Resistor, 0 Jumper For >2Vout, Not installed Resistor, 0 Jumper Resistor, 340k , 1% 340k sets for 20A limit. See ILIM formula for other values Resistor, 100k , 5% Resistor, 91k , 5% 8-position DIP switch Not Installed Test Point Power Block IC, Step-Up DC-DC Converter, 0.5A Footprint 1812 7343 1206 1210 0805 1206 D-64 SMT SMT 2716 SMT SMT SMT 1206 1206 1206 Mfr. Mfr. P/N TDK C4532X5R0J107MT Sanyo 6TPB470M Novacap 1206B104K500N TDK C3225X5R1C106KT MuRata GRM40X7R105K010 MuRata GRM42-6C0G470J050A International Rectifier 10MQ040N Samtec TSW-102-07-LS Samtec SNT-100-BKT Panasonic ETQP6F1R1BFA Sumida CR43-220 Isotek Corp SMT-R000 Panasonic ROHM ERJ-8GEY0R00 MCR18EZHF3403 MCR18EZHJ104 MCR18EZHJ913 SD08H0SK 1502-2 IP1001 MAX1675EUA
1206 ROHM 1206 ROHM SMT C&K Components Keystone SSBGA International Rectifier 14mmx14mm 8uMAX Maxim
IRDCIP1001-B (For operation 5VIN to 12VIN)
Designator Value Part Type Capacitor, 25V, 10%, X5R Capacitor, 6.3V, 20%, Tantalum Capacitor, 50V, 10%, X7R Not Installed Schottky Diode, 40V, 2.1A Not Installed Not Installed Inductor, 16A, 20%, Ferrite Not Installed Resistor, 0 Jumper For <2Vout, Not installed For >2Vout, Resistor, 0 Jumper For <2Vout, Resistor, 0 Jumper For >2Vout see formula for value For <2Vout, Not installed For >2Vout recommend 1k see formula for detail For <2Vout, Resistor, 0 Jumper For >2Vout, Not installed Resistor, 0 Jumper Resistor, 340k , 1% 340k sets for 20A limit. See ILIM formula for other values Not Installed 8-position DIP switch Test Point Not Installed Power Block Not Installed Footprint 1812 7343 1206 D-64 SMT 2716 SMT SMT SMT 1206 1206 1206 SMT Mfr. MuRata Sanyo Novacap International Rectifier Panasonic Isotek Corp Panasonic ROHM C&K Components Keystone Mfr. P/N GRM43-2X5R106K25A 6TPB470M 1206B104K500N 10MQ040N ETQP6F1R1BFA SMT-R000 ERJ-8GEY0R00 MCR18EZHF3403 SD08H0SK 1502-2 IP1001 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 10.0uF C11 C12 C13 C14 C16 C15, C17, C18, C19, C20, C21 D1 JP1, JP2, JP3 JP1-1, JP2-1, JP3-1 L1 L2 R1 R2 R3 R4 R5 R6 R7 R8, R9 SW1 TP1 TP2 TP4 TP5 TP3 U1 U2 470uF 0.100uF 40V 1.06uH 0 0 340k -
SSBGA International Rectifier 14mmx14mm -
Table 4 - Reference Design Bill of Materials 16 www.irf.com
IP1001
0.15 [.006] C 2X 6 14.00 [.551] B A
5 BALL A1 CORNER ID
C 0.45 [.0177] 0.35 [.0138]
0.12 [.005] C
14.00 [.551] NOTES: 1. 2. 3. 4. 5 6 7 DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. CONTROLLING DIMENSION: MILLIMETER SOLDER BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. PRIMARY DATUM C (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY. SOLDER BALL DIAMETER IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, IN A PLANE PARALLEL TO DATUM C.
TOP VIEW
0.15 [.006] C 2X 6
218X O
0.55 [.0216] 0.45 [.0178]
7
0.15 [.006] 0.08 [.003]
CAB C
0.40 [.016] 4X BOTTOM VIEW
0.80 [.032] 30X
(4X 1.0 [.039])
2.66 [.1047] 2.46 [.0969] 3.11 [.1224] 2.81 [.1107] SIDE VIEW
Mechanical Drawing
Refer to the following application notes for detailed guidelines and suggestions when implementing iPOWIR Technology products: AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifier's iPOWIR Technology BGA Packages This paper discusses the assembly considerations that need to be taken when mounting iPOWIR BGA's on printed circuit boards. This includes soldering, pick and place, reflow, inspection, cleaning and reworking recommendations. AN-1029: Optimizing a PCB Layout for an iPOWIR Technology Design This paper describes how to optimize the PCB layout design for both thermal and electrical performance. This includes placement, routing, and via interconnect suggestions. AN-1030: Applying iPOWIR Products in Your Thermal Environment This paper explains how to use the Power Loss and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. www.irf.com 17
IP1001
0123 XXXX IP1001
TOP
Part Marking
0123 XXXX IP1001
0123 XXXX IP1001
24mm
20mm
FEED DIRECTION
NOTES: 1. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Tape & Reel Information
Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.03/02 18 www.irf.com

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