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| TECHNICAL DATA IN74LV138 3-to-8 line decoder/demultiplexer; inverting The IN74LV138 is a low-voltage Si-gate CMOS device and is pin and function compatible 74HCT138. The74LV138 accepts three binary weighted address inputs (A 0,A 1,A 2) and when enabled,provide 8 - mutually exclusive active LOW outputs (Y0 to Y7). The "138" features three enable inputs: two active LOW (CS2,CS3 and one active HIGH (CS1).Every output will be HIGH untess CS2, and CS3 are LOW and CS1 is HIGH. * * * * * * Optimized for Low Voltage applications:1.2 to 3.6 V Demultiplexing capability Multiple input enabte for easy expansion Ideal for memory chip select decoding Active LOW mutually exclusive outputs Output capability: standard 16 1 16 1 D SUFFIX SOIC N SUFFIX PLASTIC ORDERING INFORMATION IN74LV138N Plastic IN74LV138D SOIC TA = -40 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs CS1 CS2 CS3 XXH XHX LXX PIN 16 =VCC PIN 8 = GND H H H H H H H H L L L L L L L L L L L L L L L L A2 A1 A0 XXX XXX XXX LLL LLH LHL LHH HLL HLH HHL HHH Outputs Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 H H H HHHHH H H H HHHHH H H H HHHHH L H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H H H H H H H H H H H H H H LHHH HLHH HHLH HHHL H = high level (steady state) L = low level (steady state) X = don't care INTEGRAL 1 IN74LV138 MAXIMUM RATINGS Symbol VCC IIK IOK IO ICC Tstg PD * Value -0.5 to +7.0 20 50 25 50 -65 to +150 750 500 260 C VI< - 0.5 or VI> Vcc+0.5V VO< - 0.5 or VO> Vcc+0.5V -0.5A TL * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/C from 70 to 125C SOIC Package: : - 8 mW/C from 70 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VO TA tr, t f DC supply voltage DC input voltage, DC output voltage Operating ambient temperature range in free air Input rise and fall times except for Schmitt-trigger inputs Vcc= 1.0 ? 2.0A Vcc= 2.0 ? 2.7A Vcc= 2.7 ? 3.6A Vcc= 3.6 ? 5.5A Parameter Min 1.0 0 0 -40 0 0 0 Max 5.5 VCC VCC +125 500 200 100 50 Unit V V V C ns/B This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. INTEGRAL 2 IN74LV138 DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions VCC, A 25C min VIH High-level input voltage 1.2 2.0 2.7 to 3.6 4.5 to 5.5 1.2 2.0 2.7 to 3.6 4.5 to 5.5 -I0=100A VIH or VIL 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 1.2 2.0 3.0 3.0 4.5 5.5 5.5 0.9 1.4 2.0 0.7 Vcc 1.85 2.55 2.85 3.45 4.35 5.35 2.48 3.70 max 0.3 0.6 0.8 0.3 Vcc Guaranteed Limit io -40C to 85C min 0.9 1.4 2.0 0.7 Vcc 1.8 2.5 2.8 3.4 4.3 5.3 2.40 3.60 max 0.3 0.6 0.8 0.3 Vcc io -40C to 125C min 0.9 1.4 2.0 0.7 Vcc 1.8 2.5 2.8 3.4 4.3 5.3 2.20 3.50 max 0.3 0.6 0.8 0.3 Vcc A Unit VIL Low -level input voltage A VOH High-level output voltage A VIH or VIL -IO=6.0 mA -IO=12.0 mA VOL Low-level output VIH or VIL voltage I0=100A B 0.15 0.15 0.15 0.33 0.40 0.1 8.0 0.2 0.2 0.2 0.40 0.55 1.0 80 0.2 0.2 0.2 0.50 0.65 1.0 160 B VIH or VIL IO=6.0 mA IO=12.0 mA II ICC Input leakage current Quiescent supply current VCC or GND VCC or GND IO=0 B - - - ieA ieA INTEGRAL 3 IN74LV138 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tLH = tHL = 2.5 nc, VIL=0B, VIH=VCC) Symbol Parameter VCC V 25C min tPLH, t PHL Propagation delay, input A to output Y (Figures 1) 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 max 150 33 23 19 14 170 35 26 21 17 170 35 26 21 17 7.0 Guaranteed Limit io -40C to 85C min max 150 36 26 21 16 170 39 29 23 19 170 39 29 23 19 io -40C to 125C min max 180 44 33 26 20 200 49 36 29 24 200 49 36 29 24 ns Unit tPLH, t PHL Propagation delay , CS1 to output Y (Figures 2) Output transition time, CS2 or CS3 to output Y (Figures 3) - - - ns tPLH, t PHL - - - ns CIN Input capacitance 5.0 O=+25 iN pF Power dissipation capacitance (per enabled output) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Typical @25C,VCC=5.5 V 90 pF tr INPUT A Vcc 50% GND OUTPUT Y INPUT CS1 90% 50% 10% tf Vcc GND tPHL OUTPUT Y 50% tPLH tPHL 90% 50% 10% tPLH Figure 1. Switching Waveforms Figure 2. Switching Waveforms INTEGRAL 4 IN74LV138 tr INPUT CS2,CS3 90% 50% 10% Vcc GND DEVICE UNDER TEST OUTPUT C * TEST POINT tPHL OUTPUT Y 90% 50% 10% tPLH L * Includes all prode and jig capacitance Figure 3. Switching Waveforms Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM INTEGRAL 5 IN74LV138 INTEGRAL 6 IN74LV138 CHIP PAD DIAGRAM 1.4+-0.03 Chip marking LV138 15 14 13 12 11 10 16 01 Y 02 (0,0) 03 X 04 05 09 08 07 06 Location of marking (mm): left lower corner x = 0.950, y = 1.175; Thickness of chip:0.46 0.02 mm PAD LOCATION Pad Pad Name X No. 01 AO 0.118 02 A1 0.118 03 A2 0.395 04 CS2 0.709 05 CS3 0.877 06 CS1 1.191 07 Y7 1.191 08 GND 1.191 09 Y6 1.191 10 Y5 1.084 11 Y4 0.798 12 Y3 0.640 13 Y2 0472 14 Y1 0.314 15 Y0 0.131 16 Vcc 0.118 Note: Pad location is given as per passivation layer Y 0.429 0.115 0.115 0.115 0.115 0.115 0.283 0.441 0.599 1.111 1.111 1.111 1.111 1.111 1.111 0.597 Pad size (mm) 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 INTEGRAL 1.33+-0.03 7 IN74LV138 INTEGRAL 8 |
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