DUAL CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT
IDT82V2082
FEATURES:
* * * * * * Dual channel T1/E1/J1 long haul/short haul line interfaces Supports HPS (Hitless Protection Switching) for 1+1 protection without external relays Receiver sensitivity exceeds -36 dB@772KHz and -43 dB@1024 KHz Programmable T1/E1/J1 switchability allowing one bill of material for any line condition Single 3.3 V power supply with 5 V tolerance on digital interfaces Meets or exceeds specifications in - ANSI T1.102, T1.403 and T1.408 - ITU I.431, G.703, G.736, G.775 and G.823 - ETSI 300-166, 300-233 and TBR12/13 - AT&T Pub 62411 Software programmable or hardware selectable on: - Wave-shaping templates for short haul and long haul LBO (Line Build Out) - Line terminating impedance (T1:100 , J1:110 , E1:75 /120 ) - Adjustment of arbitrary pulse shape - JA (Jitter Attenuator) position (receive path or transmit path) - Single rail/dual rail system interfaces - B8ZS/HDB3/AMI line encoding/decoding Active edge of transmit clock (TCLK) and receive clock (RCLK) Active level of transmit data (TDATA) and receive data (RDATA) Receiver or transmitter power down High impedance setting for line drivers PRBS (Pseudo Random Bit Sequence) generation and detection with 215-1 PRBS polynomials for E1 - QRSS (Quasi Random Sequence Signals) generation and detection with 220-1 QRSS polynomials for T1/J1 - 16-bit BPV (Bipolar Pulse Violation) /Excess Zero/PRBS or QRSS error counter - Analog loopback, Digital loopback, Remote loopback and Inband loopback Cable attenuation indication Adaptive receive sensitivity Non-intrusive monitoring per ITU G.772 specification Short circuit protection and internal protection diode for line drivers LOS (Loss Of Signal) & AIS (Alarm Indication Signal) detection JTAG interface Supports serial control interface, Motorola and Intel Non-Multiplexed interfaces and hardware control mode Package: IDT82V2082: 80-pin TQFP -
*
* * * * * * * *
DESCRIPTION:
The IDT82V2082 can be configured as a dual channel T1, E1 or J1 Line Interface Unit. In receive path, an Adaptive Equalizer is integrated to remove the distortion introduced by the cable attenuation. The IDT82V2082 also performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and detects and reports the LOS conditions. In transmit path, there is an AMI/B8ZS/HDB3 encoder, Waveform Shaper and LBOs. There is one Jitter Attenuator, which can be placed in either the receive path or the transmit path. The Jitter Attenuator can also be disabled. The IDT82V2082 supports both Single Rail and Dual Rail system interfaces. To facilitate the network maintenance, a PRBS/QRSS generation/detection circuit is integrated in the chip, and different types of loopbacks can be set according to the applications. Four different kinds of line terminating impedance, 75 , 100 , 110 and 120 are selectable on a per channel basis. The chip also provides driver short-circuit protection and internal protection diode and supports JTAG boundary scanning. The chip can be controlled by either software or hardware. The IDT82V2082 can be used in LAN, WAN, Routers, Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices, CSU/DSU equipment, etc.
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2003 Integrated Device Technology, Inc. All rights reserved.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
July 2004
DSC-6229/5
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
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FUNCTIONAL BLOCK DIAGRAM
LOSn
LOS/AIS Detector B8ZS/ HDB3/AMI Decoder PRBS Detector IBLC Detector Data and Clock Recovery Adaptive Equalizer
One of the Two Identical Channels
RCLKn RDn/RDPn CVn/RDNn
Jitter Attenuator
Data Slicer
Receiver Internal Termination Analog Loopback
RTIPn RRINGn
Remote Loopback
Digital Loopback Waveform Shaper/LBO Line Driver Transmitter Internal Termination
TCLKn TDn/TDPn TDNn
B8ZS/ HDB3/AMI Decoder PRBS Generator IBLC Generator TAOS Clock Generator
Jitter Attenuator
TTIPn TRINGn
Software Control Interface
Register Files
Pin Control
JTAG TAP
G.772 Monitor
TRST TCK TMS
INT CS SDO SCLK R/W/WR/SDI RD/DS/SCLKE A[5:0] D[7:0]
MODE[1:0] TERMn RXTXM[1:0] PULSn[3:0] EQn PATTn[1:0] JA[1:0] MONTn LPn[1:0] THZ RCLKE RPDn RST
TDI TDO
VDDIO VDDD VDDA VDDT VDDR
MCLK
Figure-1 Block Diagram
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TABLE OF CONTENTS
1 2 3 IDT82V2082 PIN CONFIGURATIONS .......................................................................................... 8 PIN DESCRIPTION ....................................................................................................................... 9 FUNCTIONAL DESCRIPTION .................................................................................................... 17 3.1 CONTROL MODE SELECTION ....................................................................................... 17 3.2 T1/E1/J1 MODE SELECTION .......................................................................................... 17 3.3 TRANSMIT PATH ............................................................................................................. 17 3.3.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 17 3.3.2 ENCODER ............................................................................................................. 17 3.3.3 PULSE SHAPER .................................................................................................... 17 3.3.3.1 Preset Pulse Templates .......................................................................... 17 3.3.3.2 LBO (Line Build Out) ............................................................................... 18 3.3.3.3 User-Programmable Arbitrary Waveform ................................................ 18 3.3.4 TRANSMIT PATH LINE INTERFACE..................................................................... 22 3.3.5 TRANSMIT PATH POWER DOWN ........................................................................ 23 3.4 RECEIVE PATH ............................................................................................................... 23 3.4.1 RECEIVE INTERNAL TERMINATION.................................................................... 23 3.4.2 LINE MONITOR ...................................................................................................... 24 3.4.3 ADAPTIVE EQUALIZER......................................................................................... 25 3.4.4 RECEIVE SENSITIVITY ......................................................................................... 25 3.4.5 DATA SLICER ........................................................................................................ 25 3.4.6 CDR (Clock & Data Recovery)................................................................................ 25 3.4.7 DECODER .............................................................................................................. 25 3.4.8 RECEIVE PATH SYSTEM INTERFACE ................................................................ 25 3.4.9 RECEIVE PATH POWER DOWN........................................................................... 25 3.4.10 G.772 NON-INTRUSIVE MONITORING ................................................................ 26 3.5 JITTER ATTENUATOR .................................................................................................... 27 3.5.1 JITTER ATTENUATION FUNCTION DESCRIPTION ............................................ 27 3.5.2 JITTER ATTENUATOR PERFORMANCE ............................................................. 27 3.6 LOS AND AIS DETECTION ............................................................................................. 28 3.6.1 LOS DETECTION ................................................................................................... 28 3.6.2 AIS DETECTION .................................................................................................... 29 3.7 TRANSMIT AND DETECT INTERNAL PATTERNS ........................................................ 30 3.7.1 TRANSMIT ALL ONES ........................................................................................... 30 3.7.2 TRANSMIT ALL ZEROS......................................................................................... 30 3.7.3 PRBS/QRSS GENERATION AND DETECTION.................................................... 30 3.8 LOOPBACK ...................................................................................................................... 30 3.8.1 ANALOG LOOPBACK ............................................................................................ 30 3.8.2 DIGITAL LOOPBACK ............................................................................................. 30 3.8.3 REMOTE LOOPBACK............................................................................................ 30 3.8.4 INBAND LOOPBACK.............................................................................................. 32 3.8.4.1 Transmit Activate/Deactivate Loopback Code......................................... 32 3.8.4.2 Receive Activate/Deactivate Loopback Code.......................................... 32
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3.9
3.10 3.11
3.12
3.13 3.14 3.15 3.16 4
3.8.4.3 Automatic Remote Loopback .................................................................. 32 ERROR DETECTION/COUNTING AND INSERTION ...................................................... 33 3.9.1 DEFINITION OF LINE CODING ERROR ............................................................... 33 3.9.2 ERROR DETECTION AND COUNTING ................................................................ 33 3.9.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 34 LINE DRIVER FAILURE MONITORING ........................................................................... 34 MCLK AND TCLK ............................................................................................................. 35 3.11.1 MASTER CLOCK (MCLK) ...................................................................................... 35 3.11.2 TRANSMIT CLOCK (TCLK).................................................................................... 35 MICROCONTROLLER INTERFACES ............................................................................. 36 3.12.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 36 3.12.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 36 INTERRUPT HANDLING .................................................................................................. 37 5V TOLERANT I/O PINS .................................................................................................. 37 RESET OPERATION ........................................................................................................ 37 POWER SUPPLY ............................................................................................................. 37
PROGRAMMING INFORMATION .............................................................................................. 38 4.1 REGISTER LIST AND MAP ............................................................................................. 38 4.2 REGISTER DESCRIPTION .............................................................................................. 40 4.2.1 GLOBAL REGISTERS............................................................................................ 40 4.2.2 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 41 4.2.3 JITTER ATTENUATION CONTROL REGISTER ................................................... 41 4.2.4 TRANSMIT PATH CONTROL REGISTERS........................................................... 42 4.2.5 RECEIVE PATH CONTROL REGISTERS ............................................................. 44 4.2.6 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 46 4.2.7 INTERRUPT CONTROL REGISTERS ................................................................... 49 4.2.8 LINE STATUS REGISTERS ................................................................................... 52 4.2.9 INTERRUPT STATUS REGISTERS ...................................................................... 54 4.2.10 COUNTER REGISTERS ........................................................................................ 55 HARDWARE CONTROL PIN SUMMARY .................................................................................. 56 IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 58 6.1 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 59 6.2 JTAG DATA REGISTER ................................................................................................... 59 6.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 59 6.2.2 BYPASS REGISTER (BR)...................................................................................... 59 6.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 59 6.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 59 TEST SPECIFICATIONS ............................................................................................................ 62 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 74 8.1 SERIAL INTERFACE TIMING .......................................................................................... 74 8.2 PARALLEL INTERFACE TIMING ..................................................................................... 75
5 6
7 8
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LIST OF TABLES
Table-1 Table-2 Table-3 Table-4 Table-5 Table-6 Table-7 Table-8 Table-9 Table-10 Table-11 Table-12 Table-13 Table-14 Table-15 Table-16 Table-17 Table-18 Table-19 Table-20 Table-21 Table-22 Table-23 Table-24 Table-25 Table-26 Table-27 Table-28 Table-29 Table-30 Table-31 Table-32 Table-33 Table-34 Table-35 Table-36 Table-37 Table-38 Table-39 Table-40 Table-41 Table-42 Table-43 Table-44 Table-45 Table-46 Pin Description ................................................................................................................ 9 Transmit Waveform Value For E1 75 ........................................................................ 19 Transmit Waveform Value For E1 120 ...................................................................... 19 Transmit Waveform Value For T1 0~133 ft................................................................... 19 Transmit Waveform Value For T1 133~266 ft............................................................... 20 Transmit Waveform Value For T1 266~399 ft............................................................... 20 Transmit Waveform Value For T1 399~533 ft............................................................... 20 Transmit Waveform Value For T1 533~655 ft............................................................... 20 Transmit Waveform Value For J1 0~655 ft ................................................................... 21 Transmit Waveform Value For DS1 0 dB LBO.............................................................. 21 Transmit Waveform Value For DS1 -7.5 dB LBO ......................................................... 21 Transmit Waveform Value For DS1 -15.0 dB LBO ....................................................... 21 Transmit Waveform Value For DS1 -22.5 dB LBO ....................................................... 22 Impedance Matching for Transmitter ............................................................................ 22 Impedance Matching for Receiver ................................................................................ 23 Criteria of Starting Speed Adjustment........................................................................... 27 LOS Declare and Clear Criteria for Short Haul Mode ................................................... 28 LOS Declare and Clear Criteria for Long Haul Mode.................................................... 29 AIS Condition ................................................................................................................ 29 Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 30 EXZ Definition ............................................................................................................... 33 Interrupt Event............................................................................................................... 37 Global Register List and Map........................................................................................ 38 Per Channel Register List and Map .............................................................................. 39 ID: Device Revision Register ........................................................................................ 40 RST: Reset Register ..................................................................................................... 40 GCF: Global Configuration Register ............................................................................. 40 INTCH: Interrupt Channel Indication Register............................................................... 40 TERM: Transmit and Receive Termination Configuration Register .............................. 41 JACF: Jitter Attenuation Configuration Register ........................................................... 41 TCF0: Transmitter Configuration Register 0 ................................................................. 42 TCF1: Transmitter Configuration Register 1 ................................................................. 42 TCF2: Transmitter Configuration Register 2 ................................................................. 43 TCF3: Transmitter Configuration Register 3 ................................................................. 43 TCF4: Transmitter Configuration Register 4 ................................................................. 43 RCF0: Receiver Configuration Register 0..................................................................... 44 RCF1: Receiver Configuration Register 1..................................................................... 45 RCF2: Receiver Configuration Register 2..................................................................... 46 MAINT0: Maintenance Function Control Register 0...................................................... 46 MAINT1: Maintenance Function Control Register 1...................................................... 47 MAINT2: Maintenance Function Control Register 2...................................................... 47 MAINT3: Maintenance Function Control Register 3...................................................... 47 MAINT4: Maintenance Function Control Register 4...................................................... 48 MAINT5: Maintenance Function Control Register 5...................................................... 48 MAINT6: Maintenance Function Control Register 6...................................................... 48 INTM0: Interrupt Mask Register 0 ................................................................................. 49
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
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Table-47 Table-48 Table-49 Table-50 Table-51 Table-52 Table-53 Table-54 Table-55 Table-56 Table-57 Table-58 Table-59 Table-60 Table-61 Table-62 Table-63 Table-64 Table-65 Table-66 Table-67 Table-68 Table-69 Table-70 Table-71 Table-72 Table-73 Table-74 Table-75
INTM1: Interrupt Masked Register 1 ............................................................................. INTES: Interrupt Trigger Edge Select Register ............................................................. STAT0: Line Status Register 0 (real time status monitor)............................................. STAT1: Line Status Register 1 (real time status monitor)............................................. INTS0: Interrupt Status Register 0 ................................................................................ INTS1: Interrupt Status Register 1 ................................................................................ CNT0: Error Counter L-byte Register 0......................................................................... CNT1: Error Counter H-byte Register 1 ........................................................................ Hardware Control Pin Summary ................................................................................... Instruction Register Description .................................................................................... Device Identification Register Description..................................................................... TAP Controller State Description .................................................................................. Absolute Maximum Rating ............................................................................................ Recommended Operation Conditions ........................................................................... Power Consumption...................................................................................................... DC Characteristics ........................................................................................................ E1 Receiver Electrical Characteristics .......................................................................... T1/J1 Receiver Electrical Characteristics...................................................................... E1 Transmitter Electrical Characteristics ...................................................................... T1/J1 Transmitter Electrical Characteristics.................................................................. Transmitter and Receiver Timing Characteristics ......................................................... Jitter Tolerance ............................................................................................................. Jitter Attenuator Characteristics .................................................................................... JTAG Timing Characteristics ........................................................................................ Serial Interface Timing Characteristics ......................................................................... Non-Multiplexed Motorola Read Timing Characteristics ............................................... Non-Multiplexed Motorola Write Timing Characteristics ............................................... Non-Multiplexed Intel Read Timing Characteristics ...................................................... Non-Multiplexed Intel Write Timing Characteristics ......................................................
50 51 52 53 54 55 55 55 56 59 59 60 62 62 63 63 64 65 66 67 68 69 71 73 74 75 76 77 78
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LIST OF FIGURES
Figure-1 Figure-2 Figure-3 Figure-4 Figure-5 Figure-6 Figure-7 Figure-8 Figure-9 Figure-10 Figure-11 Figure-12 Figure-13 Figure-14 Figure-15 Figure-16 Figure-17 Figure-18 Figure-19 Figure-20 Figure-21 Figure-22 Figure-23 Figure-24 Figure-25 Figure-26 Figure-27 Figure-28 Figure-29 Figure-30 Figure-31 Figure-32 Figure-33 Figure-34 Figure-35 Figure-36 Block Diagram ................................................................................................................. 2 IDT82V2082 TQFP80 Package Pin Assignment ............................................................ 8 E1 Waveform Template Diagram .................................................................................. 17 E1 Pulse Template Test Circuit ..................................................................................... 18 DSX-1 Waveform Template .......................................................................................... 18 T1 Pulse Template Test Circuit ..................................................................................... 18 Receive Path Function Block Diagram .......................................................................... 23 Transmit/Receive Line Circuit ....................................................................................... 24 Monitoring Receive Line in Another Chip ...................................................................... 24 Monitor Transmit Line in Another Chip .......................................................................... 24 G.772 Monitoring Diagram ............................................................................................ 26 Jitter Attenuator ............................................................................................................. 27 LOS Declare and Clear ................................................................................................. 28 Analog Loopback .......................................................................................................... 31 Digital Loopback ............................................................................................................ 31 Remote Loopback ......................................................................................................... 31 Auto Report Mode ......................................................................................................... 33 Manual Report Mode ..................................................................................................... 34 TCLK Operation Flowchart ............................................................................................ 35 Serial Microcontroller Interface Function Timing ........................................................... 36 JTAG Architecture ......................................................................................................... 58 JTAG State Diagram ..................................................................................................... 61 Transmit System Interface Timing ................................................................................ 69 Receive System Interface Timing ................................................................................. 69 E1 Jitter Tolerance Performance .................................................................................. 70 T1/J1 Jitter Tolerance Performance .............................................................................. 70 E1 Jitter Transfer Performance ..................................................................................... 72 T1/J1 Jitter Transfer Performance ................................................................................ 72 JTAG Interface Timing .................................................................................................. 73 Serial Interface Write Timing ......................................................................................... 74 Serial Interface Read Timing with SCLKE=1 ................................................................ 74 Serial Interface Read Timing with SCLKE=0 ................................................................ 74 Non-Multiplexed Motorola Read Timing ........................................................................ 75 Non-Multiplexed Motorola Write Timing ........................................................................ 76 Non-Multiplexed Intel Read Timing ............................................................................... 77 Non-Multiplexed Intel Write Timing ............................................................................... 78
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
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1
IDT82V2082 PIN CONFIGURATIONS
DS / RD / SCLKE / PATT10
R/W / WR / SDI / LP21
SCLK / PATT11
D7 / PULS13
D6 / PULS12
D5 / PULS11
D4 / PULS10
D3 / PULS23
D2 / PULS22
D1 / PULS21
D0 / PULS20
A1 / PATT21
A0 / PATT20
SDO / LP20
43
60
59
58
57
56
55
54
53
52
51
50
49
48
47 46
45
44
42
VDDT1 TRING1 TTIP1 GNDT1 GNDR1 RRING1 RTIP1 VDDR1 VDDA IC REF GNDA VDDR2 RTIP2 RRING2 GNDR2 GNDT2 TTIP2 TRING2 VDDT2
41
INT / LP10
A4 / RPD2
A2 / RPD1
CS / LP11
A5 / EQ2
A3 / EQ1
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
40 39 38 37 36 35 34 33
VDDIO GNDIO TCLK1 TDP1 / TD1 TDN1 RCLK1 RDP1 / RD1 RDN1 / CV1 LOS1 VDDD MCLK GNDD LOS2 RDN2 / CV2 RDP2 / RD2 RCLK2 TDN2 TDP2 / TD2 TCLK2 RST
IDT82V2082
32 31 30 29 28 27 26 25 24 23 22 21
17
18
19
10
11
12
13
14
15
TRST
TCK
TDI
IC
VDDIO
16
TDO
GNDIO
RCLKE
TMS
TERM2
MODE1
MODE0
TERM1
MONT2
RXTXM1
Figure-2 IDT82V2082 TQFP80 Package Pin Assignment
8
RXTXM0
MONT1
THZ
JA1
JA0
20
1
2
3
4
5
6
7
8
9
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
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2
PIN DESCRIPTION
Table-1 Pin Description
Name TTIP1 TTIP2 TRING1 TRING2 Type Analog Output Pin No. 63 78 62 79
1
Description TTIPn /TRINGn: Transmit Bipolar Tip/Ring for Channel 1~2 These pins are the differential line driver outputs and can be set to high impedance state globally or individually. A logic high on THZ pin turns all these pins into high impedance state. When THZ bit (TCF1, 03H...)2 is set to `1', the TTIPn/TRINGn in the corresponding channel is set to high impedance state. In summary, these pins will become high impedance in the following conditions: * THZ pin is high: all TTIPn/TRINGn enter high impedance; * THZn bit is set to 1: the corresponding TTIPn/TRINGn become high impedance; * Loss of MCLK: all TTIPn/TRINGn pins become high impedance;* * Loss of TCLKn: the corresponding TTIPn/TRINGn become HZ (exceptions: Remote Loopback; Transmit internal pattern by MCLK); * Transmitter path power down: the corresponding TTIPn/TRINGn become high impedance; * After software reset; pin reset and power on: all TTIPn/TRINGn enter high impedance. RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 1~2 These signals are the differential receiver inputs.
RTIP1 RTIP2 RRING1 RRING2 TD1/TDP1 TD2/TDP2 TDN1 TDN2
Analog Input
67 74 66 75
I
37 23 36 24
TDn: Transmit Data for Channel 1~2 When the device is in single rail mode, the NRZ data to be transmitted is input on this pin. Data on TDn pin is sampled into the device on the active edge of TCLKn and is encoded by AMI, HDB3 or B8ZS line code rules before being transmitted. In this mode, TDNn should be connected to ground. TDPn/TDNn: Positive/Negative Transmit Data When the device is in dual rail mode, the NRZ data to be transmitted for positive/negative pulse is input on these pins. Data on TDPn/TDNn pin is sampled into the device on the active edge of TCLKn. The active polarity is also selectable. Refer to TRANSMIT PATH SYSTEM INTERFACE for details.The line code in dual rail mode is as follows: TDPn 0 0 1 1 TDNn 0 1 0 1 Output Pulse Space Positive Pulse Negative Pulse Space
TCLK1 TCLK2
I
38 22
TCLKn: Transmit Clock for Channel 1~2 This pin inputs 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode transmit clock. The transmit data at TDn/TDPn or TDNn is sampled into the device on the active edge of TCLKn. If TCLKn is missing3 and the TCLKn missing interrupt is not masked, an interrupt will be generated.
Notes: 1. The footprint `n' (n = 1~2) represents one of the two channels. 2. The name and address of the registers that contain the preceding bit. Only the address of channel 1 register is listed, the rest addresses are represented by `...'. Users can find these omitted addresses in the Register Description section. 3. TCLKn missing: the state of TCLKn continues to be high level or low level over 70 MCLK cycles.
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Table-1 Pin Description (Continued)
Name RD1/RDP1 RD2/RDP2 CV1/RDN1 CV2/RDN2 Type O Pin No. 34 26 33 27 Description RDn: Receive Data output for Channel 1~2 In single rail mode, this pin outputs NRZ data. The data is decoded according to AMI, HDB3 or B8ZS line code rules. CVn: Code Violation indication In single rail mode, the BPV/CV errors in received data stream will be reported by driving the CVn pin to high level for a full clock cycle. B8ZS/HDB3 line code violation can be indicated if the B8ZS/HDB3 decoder is enabled. When AMI decoder is selected, bipolar violation will be indicated. In hardware control mode, the EXZ, BPV/CV errors in received data stream are always monitored by the CVn pin if single rail mode is chosen. RDPn/RDNn: Positive/Negative Receive Data output for Channel 1~2 In dual rail mode, these pins output the re-timed NRZ data when CDR is enabled, or directly outputs the raw RZ slicer data if CDR is bypassed. Active edge and level select: Data on RDPn/RDNn or RDn is clocked with either the rising or the falling edge of RCLKn. The active polarity is also selectable. Refer to RECEIVE PATH SYSTEM INTERFACE for details. RCLK1 RCLK2 O 35 25 RCLKn: Receive Clock output for Channel 1~2 This pin outputs 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode receive clock. Under LOS conditions with AIS enabled (bit AISE=1), RCLKn is derived from MCLK. In clock recovery mode, this signal provides the clock recovered from the RTIPn/RRINGn signal. The receive data (RDn in single rail mode or RDPn and RDNn in dual rail mode) is clocked out of the device on the active edge of RCLKn. If clock recovery is bypassed, RCLKn is the exclusive OR (XOR) output of the dual rail slicer data RDPn and RDNn. This signal can be used in applications with external clock recovery circuitry. MCLK I 30 MCLK: Master Clock input A built-in clock system that accepts selectable 2.048MHz reference for E1 operating mode and 1.544MHz reference for T1/ J1 operating mode. This reference clock is used to generate several internal reference signals: * Timing reference for the integrated clock recovery unit. * Timing reference for the integrated digital jitter attenuator. * Timing reference for microcontroller interface. * Generation of RCLKn signal during a loss of signal condition. * Reference clock to transmit All Ones, all zeros, PRBS/QRSS pattern as well as activate or deactivate Inband Loopback code if MCLK is selected as the reference clock. Note that for ATAO and AIS, MCLK is always used as the reference clock. * Reference clock during Transmit All Ones (TAO) condition or sending PRBS/QRSS in hardware control mode. The loss of MCLK will turn TTIP/TRING into high impedance status. LOSn: Loss of Signal Output for Channel 1~2 These pins are used to indicate the loss of received signals. When LOSn pin becomes high, it indicates the loss of received signal in channel n. The LOS pin will become low automatically when valid received signal is detected again. The criteria of loss of signal are described in 3.6 LOS AND AIS DETECTION. REF: reference resister An external resistor (3k, 1%) is used to connect this pin to ground to provide a standard reference current for internal circuit.
LOS1 LOS2
O
32 28
REF
I
71
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Table-1 Pin Description (Continued)
Name MODE1 MODE0 Type I Pin No. 9 10 Description MODE[1:0]: operation mode of control interface select The level on this pin determines which control mode is used to control the device as follows: MODE[1:0] 00 01 10 11 * * * RCLKE I 11 Control Interface mode Hardware interface Serial Microcontroller Interface Motorola non-multiplexed Intel non-multiplexed
The serial microcontroller interface consists of CS, SCLK, SCLKE, SDI, SDO and INT pins. SCLKE is used for the selection of the active edge of SCLK. The parallel non-multiplexed microcontroller interface consists of CS, A[5:0], D[7:0], DS/RD, R/W/WR and INT pins. (Refer to 3.12 MICROCONTROLLER INTERFACES for details) Hardware interface consists of PULSn[3:0], THZ, RCLKE, LPn[1:0], PATTn[1:0], JA[1:0], MONTn, TERMn, EQn, RPDn, MODE[1:0] and RXTXM[1:0] (n=1, 2).
RCLKE: the active edge of RCLKn select In hardware control mode, this pin selects the active edge of RCLKn * L= update RDPn/RDNn on the rising edge of RCLKn * H= update RDPn/RDNn on the falling edge of RCLKn In software control mode, this pin should be connected to GNDIO. RXTXM[1:0]: Receive and transmit path operation mode select In hardware control mode, these pins are used to select the single rail or dual rail operation modes as well as AMI or HDB3/ B8ZS line coding: * 00= single rail with HDB3/B8ZS coding * 01= single rail with AMI coding * 10= dual rail interface with CDR enabled * 11= slicer mode (dual rail interface with CDR disabled) In software control mode, these pins should be connected to ground. CS: Chip Select In serial or parallel microcontroller interface mode, this is the active low enable signal. A low level on this pin enables serial or parallel microcontroller interface. LP11/LP10: Loopback mode select for channel 1 When the chip is configured by hardware, this pin is used to select loopback operation modes for channel 1(Inband Loopback is not provided in hardware control mode) * 00= no loopback * 01= analog loopback * 10= digital loopback * 11= remote loopback
RXTXM1 RXTXM0
I
14 15
CS
I
42
LP11
INT
O
41
INT: Interrupt Request In software control mode, this pin outputs the general interrupt request for all interrupt sources. If INTM_GLB bit (GCF, 20H) is set to `1', all the interrupt sources will be masked. These interrupt sources can be masked individually via registers (INTM0, 13H...) and (INTM1, 14H...). The interrupt status is reported via the registers (INTCH, 21H), (INTS0, 18H...) and (INTS1, 19H...). Output characteristics of this pin can be defined to be push-pull (active high or active low) or open-drain (active low) by setting bits INT_PIN[1:0] (GCF, 20H)
LP10
I
LP11/LP10: Loopback mode select for channel 1 See above LP11.
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name SCLK Type I Pin No. 46 Description SCLK: Shift Clock In serial microcontroller interface mode, this signal is the shift clock for the serial interface. Configuration data on SDI pin is sampled on the rising edge of SCLK. Configuration and status data on SDO pin is clocked out of the device on the rising edge of SCLK if SCLKE pin is low, or on the falling edge of SCLK if SCLKE pin is high. In parallel non-multiplexed interface mode, this pin should be connected to ground. PATT11/PATT10: Transmit pattern select for channel 1 In hardware control mode, this pin selects the transmit pattern * 00 = normal * 01= All Ones * 10= PRBS * 11= transmitter power down I 45 SCLKE: Serial Clock Edge Select In serial microcontroller interface mode, this signal selects the active edge of SCLK for outputting SDO. The output data is valid after some delay from the active clock edge. It can be sampled on the opposite edge of the clock. The active clock edge which clocks the data out of the device is selected as shown below: SCLKE Low High SCLK Rising edge is the active edge. Falling edge is the active edge.
PATT11
SCLKE
DS
DS: Data Strobe In Motorola parallel non-multiplexed interface mode, this signal is the data strobe of the parallel interface. In a write operation (R/W = 0), the data on D[7:0] is sampled into the device. In a read operation (R/W = 1), the data is driven to D[7:0] by the device. RD: Read Strobe In Intel parallel non-Multiplexed interface mode, the data is driven to D[7:0] by the device during low level of RD in a read operation. PATT11/PATT10: Transmit pattern select for channel 1 See above PATT11. I 44 SDI: Serial Data Input In serial microcontroller interface mode, this signal is the input data to the serial interface. Configuration data at SDI pin is sampled by the device on the rising edge of SCLK. R/W: Read/Write Select In Motorola parallel non-multiplexed interface mode, this pin is low for write operation and high for read operation. WR: Write Strobe In Intel parallel non-multiplexed interface mode, this pin is asserted low by the microcontroller to initiate a write cycle. The data on D[7:0] is sampled into the device in a write operation. LP21/LP20: loopback mode select for channel 2 When the chip is configured by hardware, this pin is used to select loopback operation modes for channel 2(Inband Loopback is not provided in hardware control mode) * 00= no loopback * 01= analog loopback * 10= digital loopback * 11= remote loopback
RD
PATT10 SDI
R/W
WR
LP21
12
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name SDO Type O Pin No. 43 Description SDO: Serial Data Output In serial microcontroller interface mode, this signal is the output data of the serial interface. Configuration or Status data at SDO pin is clocked out of the device on the rising edge of SCLK if SCLKE pin is low, or on the falling edge of SCLK if SCLKE pin is high. In parallel non-multiplexed interface mode, this pin should be left open. LP21/LP20: loopback mode select for channel 2 See above LP21. 54 D7: Data Bus bit7 In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground through a 10 k resistor. PULS1[3:0]: these pins are used to select the following functions for channel 1 in hardware control mode: * T1/E1/J1 mode * Transmit pulse template * Internal termination impedance (75/120/100/110) Refer to 5 HARDWARE CONTROL PIN SUMMARY for details. Note that PULS13 to PULS10 determine the T1/E1/J1 mode of common block. 53 D6: Data Bus bit6 In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground through a 10 k resistor. See above. 52 D5: Data Bus bit5 In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground through a 10 k resistor. See above. 51 D4: Data Bus bit4 In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground through a 10 k resistor. See above. 50 D3: Data Bus bit3 In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground through a 10 k resistor. PULS2[3:0]: these pins are used to select the following functions for channel 2 in hardware control mode:* * T1/E1/J1 mode * Transmit pulse template * Internal termination impedance (75/120/100/110) Refer to 5 HARDWARE CONTROL PIN SUMMARY for details. 49 D2: Data Bus bit2 In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground through a 10 k resistor. See above 48 D1: Data Bus bit1 In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground through a 10 k resistor. See above 47 D0: Data Bus bit0 In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground through a 10 k resistor. See above. 13
LP20 D7
I I/O
PULS13
I
D6
I/O
PULS12 D5
I I/O
PULS11 D4
I I/O
PULS10 D3
I I/O
PULS23
I
D2
I/O
PULS22 D1
I I/O
PULS21 D0
I I/O
PULS20
I
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name A5 Type I Pin No. 60 Description A5: Address Bus bit5 In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground. EQ2: Equalizer on/off for receiver2 in hardware control mode 0= short haul (10dB) 1= long haul (36dB for T1/J1, 43 dB for E1) I 59 A4: Address Bus bit4 In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground. RPD2: Power down control for receiver2 in hardware control mode 0= receiver 2 normal operation 1= receiver 2 power down I 58 A3: Address Bus bit3 In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground. EQ1: Equalizer on/off for receiver1 in hardware control mode 0= short haul (10dB) 1= long haul (36dB for T1/J1, 43 dB for E1) I 57 A2: Address Bus bit2 In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground. RPD1: Power down control for receiver1 in hardware control mode 0= receiver 1 normal operation 1= receiver 1 power down I 56 A1: Address Bus bit1 In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground. PATT21/PATT20: Transmit pattern select for channel 2 In hardware control mode, this pin selects the transmit pattern 00 = normal 01= All Ones 10= PRBS 11= transmitter power down I 55 A0: Address Bus bit 0 In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground. See above I 13 12 TERMn: Selects internal or external impedance matching for channel 1 and channel 2 in hardware control mode 0 = ternary interface with internal impedance matching network 1 = ternary interface with external impedance matching network in E1 mode; ternary interface with external impedance matching network for receiver and ternary interface with internal impedance matching network for transmitter in T1/J1 mode. (This applies to ZB die revision only.) In software control mode, this pin should be connected to ground. JA[1:0]: Jitter attenuation position, bandwidth and the depth of FIFO select for channel 1 and channel 2 (only used in hardware control mode) * 00 = JA is disabled * 01= JA in receiver, broad bandwidth, FIFO=64 bits * 10 = JA in receiver, narrow bandwidth, FIFO=128 bits * 11= JA in transmitter, narrow bandwidth, FIFO=128 bits In software control mode, this pin should be connected to ground. See above. 14
EQ2
A4
RPD2
A3
EQ1
A2
RPD1
A1
PATT21
A0
PATT20 TERM1 TERM2
JA1
I
16
JA0
I
17
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Table-1 Pin Description (Continued)
Name MONT2 Type I Pin No. 18 Description MONT2: Receive Monitor gain select for channel 2 In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver: 0= 0dB 1= 26dB In software control mode, this pin should be connected to ground. MONT1: Receive Monitor gain select for channel 1 In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver: 0= 0dB 1= 26dB In software control mode, this pin should be connected to ground. RST: Hardware Reset The chip is forced to reset state if a low signal is input on this pin for more than 100ns. THZ: Transmitter Driver High Impedance Enable This signal enables or disables all transmitter drivers on a global basis. A low level on this pin enables the driver while a high level on this pin places all drivers in high impedance state. Note that the functionality of the internal circuits is not affected by this signal. JTAG Signals TRST I Pullup 1 TRST: JTAG Test Port Reset This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resistor. To ensure deterministic operation of the test logic, TMS should be held high while the signal applied to TRST changes from low to high. For normal signal processing, this pin should be connected to ground. TMS I Pullup I 2 TMS: JTAG Test Mode Select This pin is used to control the test logic state machine and is sampled on the rising edge of TCK. TMS has an internal pullup resistor. TCK: JTAG Test Clock This is the input clock for JTAG. The data on TDI and TMS are clocked into the device on the rising edge of TCK while the data on TDO is clocked out of the device on the falling edge of TCK. When TCK is idle at low state, all the stored-state devices contained in the test logic will retain their state indefinitely. TDO: JTAG Test Data Output This output pin is high impedance normally and is used for reading all the serial configuration and test data from the test logic. The data on TDO is clocked out of the device on the falling edge of TCK. TDI: JTAG Test Data Input This pin is used for loading instructions and data into the test logic and has an internal pull-up resistor. The data on TDI is clocked into the device on the rising edge of TCK. Power Supplies and Grounds VDDIO GNDIO VDDT1 VDDT2 GNDT1 GNDT2 VDDR1 VDDR2 GNDR1 GNDR2 VDDD GNDD VDDA GNDA 7,40 8,39 61 80 64 77 68 73 65 76 31 29 69 72 3.3 V I/O power supply I/O ground 3.3 V power supply for transmitter driver Analog ground for transmitter driver Power supply for receive analog circuit Analog ground for receive analog circuit 3.3V digital core power supply Digital core ground Analog core circuit power supply Analog core circuit ground
MONT1
I
19
RST THZ
I I
21 20
TCK
3
TDO
O
4
TDI
I Pullup
5
15
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Table-1 Pin Description (Continued)
Name IC IC Type Pin No. Others 70 6 IC: Internal Connection Internal Use. This pin should be left open when in normal operation. IC: Internal Connection Internal Use. This pin should be connected to ground when in normal operation. Description
16
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
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3
3.1
FUNCTIONAL DESCRIPTION
CONTROL MODE SELECTION
3.3.2
ENCODER
The IDT82V2082 can be configured by software or by hardware. The software control mode supports Serial Control Interface, Motorola non-Multiplexed Control Interface and Intel non-Multiplexed Control Interface. The Control mode is selected by MODE1 and MODE0 pins as follows:
Control Interface mode 00 01 10 11 Hardware interface Serial Microcontroller Interface. Parallel -non-Multiplexed -Motorola Interface Parallel -non-Multiplexed -Intel Interface
In Single Rail mode, when T1/J1 mode is selected, the Encoder can be selected to be a B8ZS encoder or an AMI encoder by setting T_MD[0] bit (TCF0, 04H...). In Single Rail mode, when E1 mode is selected, the Encoder can be configured to be a HDB3 encoder or an AMI encoder by setting T_MD[0] bit (TCF0, 04H...). In both T1/J1 mode and E1 mode, when Dual Rail mode is selected (bit T_MD[1] is `1'), the Encoder is by-passed. In Dual Rail mode, a logic `1' on the TDPn pin and a logic `0' on the TDNn pin results in a negative pulse on the TTIPn/TRINGn; a logic `0' on TDPn pin and a logic `1' on TDNn pin results in a positive pulse on the TTIPn/TRINGn. If both TDPn and TDNn are high or low, the TTIPn/TRINGn outputs a space (Refer to TDn/TDPn, TDNn Pin Description). In hardware control mode, the operation mode of receive and transmit path can be selected by setting RXTXM1 and RXTXM0 pins on a global basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details. 3.3.3 PULSE SHAPER The IDT82V2082 provides three ways of manipulating the pulse shape before sending it. The first is to use preset pulse templates for short haul application, the second is to use LBO (Line Build Out) for long haul application and the other way is to use user-programmable arbitrary waveform template. In software control mode, the pulse shape can be selected by setting the related registers. In hardware control mode, the pulse shape can be selected by setting PULSn[3:0] pins on a per channel basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details. 3.3.3.1 Preset Pulse Templates For E1 applications, the pulse shape is shown in Figure-3 according to the G.703 and the measuring diagram is shown in Figure-4. In internal impedance matching mode, if the cable impedance is 75 , the PULS[3:0] bits (TCF1, 05H...) should be set to `0000'; if the cable impedance is 120 , the PULS[3:0] bits (TCF1, 05H...) should be set to `0001'. In external impedance matching mode, for both E1/75 and E1/120 cable impedance, PULS[3:0] should be set to `0001'.
* * *
The serial microcontroller Interface consists of CS, SCLK, SCLKE, SDI, SDO and INT pins. SCLKE is used for the selection of active edge of SCLK. The parallel non-Multiplexed microcontroller Interface consists of CS, A[5:0], D[7:0], DS/RD, R/W/WR and INT pins. Hardware interface consists of PULSn[3:0], THZ, RCLKE, LPn[1:0], PATTn[1:0], JA[1:0], MONTn, TERMn, EQn, RPDn, MODE[1:0] and RXTXM[1:0] (n=1, 2). Refer to 5 HARDWARE CONTROL PIN SUMMARY for details about hardware control.
3.2
T1/E1/J1 MODE SELECTION
When the chip is configured by software, T1/E1/J1 mode is selected by the T1E1 bit (GCF, 20H). In E1 application, the T1E1 bit (GCF, 20H) should be set to `0'. In T1/J1 application, the T1E1 bit should be set to `1'. When the chip is configured by hardware, T1/E1/J1 mode is selected by PULSn[3:0] pins on a per channel basis. These pins also determine transmit pulse template and internal termination impedance. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.3
TRANSMIT PATH
The transmit path of each channel of IDT82V2082 consists of an Encoder, an optional Jitter Attenuator, a Waveform Shaper, a set of LBOs, a Line Driver and a Programmable Transmit Termination. 3.3.1 TRANSMIT PATH SYSTEM INTERFACE The transmit path system interface consists of TCLKn pin, TDn/TDPn pin and TDNn pin. In E1 mode, TCLKn is a 2.048 MHz clock. In T1/J1 mode, TCLKn is a 1.544 MHz clock. If TCLKn is missing for more than 70 MCLK cycles, an interrupt will be generated if it is not masked. Transmit data is sampled on the TDn/TDPn and TDNn pins by the active edge of TCLKn. The active edge of TCLKn can be selected by the TCLK_SEL bit (TCF0, 04H...). And the active level of the data on TDn/TDPn and TDNn can be selected by the TD_INV bit (TCF0, 04H...). In hardware control mode, the falling edge of TCLKn and the active high of transmit data are always used. The transmit data from the system side can be provided in two different ways: Single Rail and Dual Rail. In Single Rail mode, only TDn pin is used for transmitting data and the T_MD[1] bit (TCF0, 04H...) should be set to `0'. In Dual Rail Mode, both TDPn pin and TDNn pin are used for transmitting data, the T_MD[1] bit (TCF0, 04H...) should be set to `1'.
17
1 .2 0
1 .0 0
0 .8 0 Normalized Amplitude
0 .6 0
0 .4 0
0 .2 0
0 .0 0
- 0 .2 0
-0 .6
- 0 .4
- 0 .2
0 T im e in U n it In te rv a ls
0 .2
0 .4
0 .6
Figure-3 E1 Waveform Template Diagram
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
3.3.3.3 User-Programmable Arbitrary Waveform
TTIPn
IDT82V2082
TRINGn Note: 1. For RLOAD = 75 (nom), Vout (Peak)=2.37V (nom) 2. For RLOAD =120 (nom), Vout (Peak)=3.00V (nom)
RLOAD
VOUT
When the PULS[3:0] bits are set to `11xx', user-programmable arbitrary waveform generator mode can be used in the corresponding channel. This allows the transmitter performance to be tuned for a wide variety of line condition or special application. Each pulse shape can extend up to 4 UIs (Unit Interval), addressed by UI[1:0] bits (TCF3, 07H...) and each UI is divided into 16 sub-phases, addressed by the SAMP[3:0] bits (TCF3, 07H...). The pulse amplitude of each phase is represented by a binary byte, within the range from +63 to 63, stored in WDAT[6:0] bits (TCF4, 08H...) in signed magnitude form. The most positive number +63 (D) represents the maximum positive amplitude of the transmit pulse while the most negative number -63 (D) represents the maximum negative amplitude of the transmit pulse. Therefore, up to 64 bytes are used. For each channel, a 64 bytes RAM is available. There are twelve standard templates which are stored in an on-chip ROM. User can select one of them as reference and make some changes to get the desired waveform. User can change the wave shape and the amplitude to get the desired pulse shape. In order to do this, firstly, users can choose a set of waveform value from the following twelve tables, which is the most similar to the desired pulse shape. Table-2, Table-3, Table-4, Table-5, Table-6, Table-7, Table-8, Table-9, Table-10, Table-11, Table-12 and Table-13 list the sample data and scaling data of each of the twelve templates. Then modify the corresponding sample data to get the desired transmit pulse shape. Secondly, through the value of SCAL[5:0] bits increased or decreased by 1, the pulse amplitude can be scaled up or down at the percentage ratio against the standard pulse amplitude if needed. For different pulse shapes, the value of SCAL[5:0] bits and the scaling percentage ratio are different. The following twelve tables list these values.
Figure-4 E1 Pulse Template Test Circuit For T1 applications, the pulse shape is shown in Figure-5 according to the T1.102 and the measuring diagram is shown in Figure-6. This also meets the requirement of G.703, 2001. The cable length is divided into five grades, and there are five pulse templates used for each of the cable length. The pulse template is selected by PULS[3:0] bits (TCF1, 05H...).
1.2 1 0.8 Normalized Amplitude 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 250 500 Time (ns) 750 1000 1250
Figure-5 DSX-1 Waveform Template
TTIPn Cable
IDT82V2082
TRINGn Note: RLOAD = 100 5%
RLOAD VOUT
Do the followings step by step, the desired waveform can be programmed, based on the selected waveform template: (1).Select the UI by UI[1:0] bits (TCF3, 07H...) (2).Specify the sample address in the selected UI by SAMP [3:0] bits (TCF3, 07H...) (3).Write sample data to WDAT[6:0] bits (TCF4, 08H...). It contains the data to be stored in the RAM, addressed by the selected UI and the corresponding sample address. (4).Set the RW bit (TCF3, 07H...) to `0' to implement writing data to RAM, or to `1' to implement read data from RAM (5).Implement the Read from RAM/Write to RAM by setting the DONE bit (TCF3, 07H...) Repeat the above steps until all the sample data are written to or read from the internal RAM. (6).Write the scaling data to SCAL[5:0] bits (TCF2, 06H...) to scale the amplitude of the waveform based on the selected standard pulse amplitude When more than one UI is used to compose the pulse template, the overlap of two consecutive pulses could make the pulse amplitude overflow (exceed the maximum limitation) if the pulse amplitude is not set properly. This overflow is captured by DAC_OV_IS bit (INTS1, 19H...), and, if enabled by the DAC_OV_IM bit (INTM1, 14H...), an interrupt will be generated.
Figure-6 T1 Pulse Template Test Circuit For J1 applications, the PULS[3:0] (TCF1, 05H...) should be set to `0111'. Table-14 lists these values. 3.3.3.2 LBO (Line Build Out) To prevent the cross-talk at the far end, the output of TTIPn/TRINGn could be attenuated before transmission for long haul applications. The FCC Part 68 Regulations specifies four grades of attenuation with a step of 7.5 dB. Three LBOs are used to implement the pulse attenuation. The PULS[3:0] bits (TCF1, 05H...) are used to select the attenuation grade. Both Table-14 and Table-15 list these values.
18
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INDUSTRIAL TEMPERATURE RANGES
The following tables give all the sample data based on the preset pulse templates and LBOs in detail for reference. For preset pulse templates and LBOs, scaling up/down against the pulse amplitude is not supported. 1.Table-2 Transmit Waveform Value For E1 75 2.Table-3 Transmit Waveform Value For E1 120 3.Table-4 Transmit Waveform Value For T1 0~133 ft 4.Table-5 Transmit Waveform Value For T1 133~266 ft 5.Table-6 Transmit Waveform Value For T1 266~399 ft 6.Table-7 Transmit Waveform Value For T1 399~533 ft 7.Table-8 Transmit Waveform Value For T1 533~655 ft 8.Table-9 Transmit Waveform Value For J1 0~655 ft 9.Table-10 Transmit Waveform Value For DS1 0 dB LBO 10.Table-11 Transmit Waveform Value For DS1 -7.5 dB LBO 11.Table-12 Transmit Waveform Value For DS1 -15.0 dB LBO 12.Table-13 Transmit Waveform Value For DS1 -22.5 dB LBO
Table-3 Transmit Waveform Value For E1 120
Sample 1 2 3 4 5 6 7 8 9 10 11 12 UI 1 0000000 0000000 0000000 0001111 0111100 0111100 0111100 0111100 0111100 0111100 0111100 0111100 0000000 0000000 0000000 0000000 UI 2 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 UI 3 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 UI 4 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000
Table-2 Transmit Waveform Value For E1 75
Sample 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UI 1 0000000 0000000 0000000 0001100 0110000 0110000 0110000 0110000 0110000 0110000 0110000 0110000 0000000 0000000 0000000 0000000 UI 2 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 UI 3 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 UI 4 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000
13 14 15 16
SCAL[5:0] = 100001 (default), One step change of this value of SCAL[5:0] results in 3% scaling up/down against the pulse amplitude.
Table-4 Transmit Waveform Value For T1 0~133 ft
Sample 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UI 1 0010111 0100111 0100111 0100110 0100101 0100101 0100101 0100100 0100011 1001010 1001010 1001001 1000111 1000101 1000100 1000011 UI 2 1000010 1000001 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 UI 3 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 UI 4 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000
SCAL[5:0] = 100001 (default), One step change of this value of SCAL[5:0] results in 3% scaling up/down against the pulse amplitude.
SCAL[5:0] = 1101101 (default), One step change of this value of SCAL[5:0] results in 2% scaling up/down against the pulse amplitude. 1. In T1 mode, when arbitrary pulse for short haul application is configured, users should write `110110' to SCAL[5:0] bits if no scaling is required.
19
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-5 Transmit Waveform Value For T1 133~266 ft
Sample 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UI 1 0011011 0101110 0101100 0101010 0101001 0101000 0100111 0100110 0100101 1010000 1001111 1001101 1001010 1001000 1000110 1000100 UI 2 1000011 1000010 1000001 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 See Table-4 UI 3 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 UI 4 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000
Table-7 Transmit Waveform Value For T1 399~533 ft
Sample 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UI 1 0100000 0111011 0110101 0101111 0101110 0101101 0101100 0101010 0101000 1011000 1011000 1010011 1001100 1001000 1000110 1000100 UI 2 1000011 1000010 1000001 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 See Table-4 UI 3 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 UI 4 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000
Table-6 Transmit Waveform Value For T1 266~399 ft
Sample 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UI 1 0011111 0110100 0101111 0101100 0101011 0101010 0101001 0101000 0100101 1010111 1010011 1010000 1001011 1001000 1000110 1000100 UI 2 1000011 1000010 1000001 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 See Table-4 UI 3 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 UI 4 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000
Table-8 Transmit Waveform Value For T1 533~655 ft
Sample 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UI 1 0100000 0111111 0111000 0110011 0101111 0101110 0101101 0101100 0101001 1011111 1011110 1010111 1001111 1001001 1000111 1000100 UI 2 1000011 1000010 1000001 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 See Table-4 UI 3 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 UI 4 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000
20
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-9 Transmit Waveform Value For J1 0~655 ft
Sample 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UI 1 0010111 0100111 0100111 0100110 0100101 0100101 0100101 0100100 0100011 1001010 1001010 1001001 1000111 1000101 1000100 1000011 UI 2 1000010 1000001 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 UI 3 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 UI 4 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000
Table-11 Transmit Waveform Value For DS1 -7.5 dB LBO
Sample 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UI 1 0000000 0000010 0001001 0010011 0011101 0100101 0101011 0110001 0110110 0111010 0111001 0110000 0101000 0100000 0011010 0010111 UI 2 0010100 0010010 0010000 0001110 0001100 0001011 0001010 0001001 0001000 0000111 0000110 0000101 0000100 0000100 0000011 0000011 UI 3 0000010 0000010 0000010 0000010 0000010 0000001 0000001 0000001 0000001 0000001 0000001 0000001 0000000 0000000 0000000 0000000 UI 4 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000
SCAL[5:0] = 110110 (default), One step change of this value of SCAL[5:0] results in 2% scaling up/down against the pulse amplitude.
SCAL[5:0] = 010001 (default), One step change of this value of SCAL[5:0] results in 6.25% scaling up/down against the pulse amplitude.
Table-10 Transmit Waveform Value For DS1 0 dB LBO
Sample 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UI 1 0010111 0100111 0100111 0100110 0100101 0100101 0100101 0100100 0100011 1001010 1001010 1001001 1000111 1000101 1000100 1000011 UI 2 1000010 1000001 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 UI 3 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 UI 4 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000
Table-12 Transmit Waveform Value For DS1 -15.0 dB LBO
Sample 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UI 1 0000000 0000000 0000000 0000001 0000100 0001000 0001110 0010100 0011011 0100010 0101010 0110000 0110101 0110111 0111000 0110111 UI 2 0110101 0110011 0110000 0101101 0101010 0100111 0100100 0100001 0011110 0011100 0011010 0010111 0010101 0010100 0010010 0010000 UI 3 0001111 0001101 0001100 0001011 0001010 0001001 0001000 0000111 0000110 0000110 0000101 0000101 0000100 0000100 0000011 0000011 UI 4 0000011 0000010 0000010 0000010 0000010 0000001 0000001 0000001 0000001 0000001 0000001 0000001 0000001 0000000 0000000 0000000
SCAL[5:0] = 110110 (default), One step change of this Value results in 2% scaling up/down against the pulse amplitude.
SCAL[5:0] = 001000 (default), One step change of the value of SCAL[5:0] results in 12.5% scaling up/down against the pulse amplitude.
21
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-13 Transmit Waveform Value For DS1 -22.5 dB LBO
Sample 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UI 1 0000000 0000000 0000000 0000000 0000001 0000011 0000111 0001011 0001111 0010101 0011001 0011100 0100000 0100011 0100111 0101010 UI 2 0101100 0101110 0110000 0110001 0110010 0110010 0110010 0110001 0110000 0101110 0101100 0101001 0100111 0100100 0100010 0100000 UI 3 0011110 0011100 0011010 0011000 0010111 0010101 0010100 0010011 0010001 0010000 0001111 0001110 0001101 0001100 0001010 0001001 UI 4 0001000 0000111 0000110 0000101 0000101 0000100 0000100 0000011 0000011 0000010 0000010 0000010 0000001 0000001 0000001 0000001
to `1', the internal impedance matching circuit will be disabled. In this case, the external impedance matching circuit will be used to realize the impedance matching. For T1/J1 mode, the external impedance matching circuit for the transmitter is not supported. Figure-8 shows the appropriate external components to connect with the cable for one channel. Table-14 is the list of the recommended impedance matching for transmitter. In hardware control mode, TERMn pin can be used to select impedance matching for both receiver and transmitter on a per channel basis. If TERMn pin is low, internal impedance network will be used. If TERMn pin is high, external impedance network will be used in E1 mode, or external impedance network for receiver and internal impedance network for transmitter will be used in T1/J1 mode. (This applies to ZB die revision only). When internal impedance network is used, PULSn[3:0] pins should be set to select the specific internal impedance in the corresponding channel. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details. The TTIPn/TRINGn can also be turned into high impedance globally by pulling THZ pin to high or individually by setting the THZ bit (TCF1, 05H...) to `1'. In this state, the internal transmit circuits are still active. In hardware control mode, TTIPn/TRINGn pins can be turned into high impedance globally by pulling THZ pin to high. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details. Besides, in the following cases, TTIPn/TRINGn will also become high impedance: * Loss of MCLK; * Loss of TCLKn (exceptions: Remote Loopback; Transmit internal pattern by MCLK); * Transmit path power down; * After software reset; pin reset and power on.
SCAL[5:0] = 000100 (default), One step change of this value of SCAL[5:0] results in 25% scaling up/down against the pulse amplitude.
3.3.4
TRANSMIT PATH LINE INTERFACE
The transmit line interface consists of TTIPn and TRINGn pins. The impedance matching can be realized by the internal impedance matching circuit or the external impedance matching circuit. If T_TERM[2] is set to `0', the internal impedance matching circuit will be selected. In this case, the T_TERM[1:0] bits (TERM, 02H...) can be set to choose 75 , 100 , 110 or 120 internal impedance of TTIPn/TRINGn. If T_TERM[2] is set
Table-14 Impedance Matching for Transmitter
Cable Configuration E1/75 E1/120 T1/0~133 ft T1/133~266 ft T1/266~399 ft T1/399~533 ft T1/533~655 ft J1/0~655 ft 0 dB LBO -7.5 dB LBO -15.0 dB LBO -22.5 dB LBO
Note: The precision of the resistors should be better than 1%
Internal Termination T_TERM[2:0] 000 001 010 PULS[3:0] 0000 0001 0010 0011 0100 0101 0110 011 010 0111 1000 1001 1010 1011 RT 0 T_TERM[2:0] 1XX
External Termination PULS[3:0] 0001 0001 RT 9.4
22
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
3.3.5
TRANSMIT PATH POWER DOWN
3.4
RECEIVE PATH
The transmit path can be powered down individually by setting the T_OFF bit (TCF0, 04H...) to `1'. In this case, the TTIPn/TRINGn pins are turned into high impedance. In hardware control mode, the transmit path can be powered down by setting PATTn[1:0] pins to `11' on a per channel basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
The receive path consists of Receive Internal Termination, Monitor Gain, Amplitude/Wave Shape Detector, Digital Tuning Controller, Adaptive Equalizer, Data Slicer, CDR (Clock & Data Recovery), Optional Jitter Attenuator, Decoder and LOS/AIS Detector. Refer to Figure-7. 3.4.1 RECEIVE INTERNAL TERMINATION The impedance matching can be realized by the internal impedance matching circuit or the external impedance matching circuit. If R_TERM[2] is set to `0', the internal impedance matching circuit will be selected. In this case, the R_TERM[1:0] bits (TERM, 02H...) can be set to choose 75 , 100 , 110 or 120 internal impedance of RTIPn/RRINGn. If R_TERM[2] is set to `1', the internal impedance matching circuit will be disabled. In this case, the external impedance matching circuit will be used to realize the impedance matching. Figure-8 shows the appropriate external components to connect with the cable for one channel. Table-15 is the list of the recommended impedance matching for receiver.
LOS/AIS Detector
LOS
RTIP RRING
Receive Internal termination
Monitor Gain
Adaptive Equalizer
Data Slicer
Clock and Data Recovery
Jitter Attenuator
RCLK Decoder RDP RDN
Figure-7 Receive Path Function Block Diagram
Table-15 Impedance Matching for Receiver
Cable Configuration E1/75 E1/120 T1 J1 Internal Termination R_TERM[2:0] 000 001 010 011 RR 120 1XX External Termination R_TERM[2:0] RR 75 120 100 110
23
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
A
RX Line
*
1:1 * RR
*
VDDRn One of the Two Identical Channels D8 * * RTIPn VDDRn D7 0.1F RRINGn TTIPn
*
3.3 V 68F 1
B
2:1 ** TX Line Cp
2
VDDRn D6 * * * D5 VDDTn D4 RT * * D3 VDDTn D2 RT D1
3
IDT82V2082
GNDRn
VDDTn 0.1F GNDTn *
3.3 V 68F 1
* *
TRINGn
Note: 1. Common decoupling capacitor 2. Cp 0-560 (pF) 3. D1 - D8, Motorola - MBR0540T1;
International Rectifier - 11DQ04 or 10BQ060
Figure-8 Transmit/Receive Line Circuit In hardware control mode, TERMn, PULSn[3:0] pins can be used to select impedance matching for both receiver and transmitter on a per channel basis. If TERMn pin is low, internal impedance network will be used. If TERMn pin is high, external impedance network will be used in E1 mode, or external impedance network for receiver and internal impedance network for transmitter will be used in T1/J1 mode. (This applies to ZB die revision only). When internal impedance network is used, PULSn[3:0] pins should be set to select specific internal impedance for the corresponding channel. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details. 3.4.2 LINE MONITOR
RRING
DSX cross connect point
RTIP
monitor gain=0dB
RRING
R
normal receive mode
RTIP
monitor gain =22/26/32dB
In both T1/J1 and E1 short haul applications, the non-intrusive monitoring on channels located in other chips can be performed by tapping the monitored channel through a high impedance bridging circuit. Refer to Figure9 and Figure-10. After a high resistance bridging circuit, the signal arriving at the RTIPn/ RRINGn is dramatically attenuated. To compensate this attenuation, the Monitor Gain can be used to boost the signal by 22 dB, 26 dB and 32 dB, selected by MG[1:0] bits (RCF2, 0BH...). For normal operation, the Monitor Gain should be set to 0 dB. In hardware control mode, MONTn pin can be used to set the Monitor Gain on a per channel basis. When MONTn pin is low, the Monitor Gain for the specific channel is 0 dB. When MONTn pin is high, the Monitor Gain for the specific channel is 26 dB. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
monitor mode
Figure-9 Monitoring Receive Line in Another Chip
DSX cross connect point
TTIP
TRING
R
normal transmit mode
RTIP
monitor gain monitor gain =22/26/32dB
RRING
monitor mode
Figure-10 Monitor Transmit Line in Another Chip
24
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
3.4.3
ADAPTIVE EQUALIZER
3.4.7
DECODER
The adaptive equalizer can remove most of the signal distortion due to intersymbol interference caused by cable attenuation. It can be enabled or disabled by setting EQ_ON bit to `1' or `0' (RCF1, 0AH...). When the adaptive equalizer is out of range, EQ_S bit (STAT0, 16H...) will be set to `1' to indicate the status of equalizer. If EQ_IES bit (INTES, 15H...) is set to `1', any changes of EQ_S bit will generate an interrupt and EQ_IS bit (INTS0, 18H...) will be set to `1' if it is not masked. If EQ_IES bit is set to `0', only the `0' to `1' transition of the EQ_S bit will generate an interrupt and EQ_IS bit will be set to `1' if it is not masked. The EQ_IS bit will be reset after being read. The Amplitude/wave shape detector keeps on measuring the amplitude/wave shape of the incoming signals during an observation period. This observation period can be 32, 64, 128 or 256 symbol periods, as selected by UPDW[1:0] bits (RCF2, 0BH...). A shorter observation period allows quicker responses to pulse amplitude variation while a longer observation period can minimize the possible overshoots. The default observation period is 128 symbol periods. Based on the observed peak value for a period, the equalizer will be adjusted to achieve a normalized signal. LATT[4:0] bits (STAT1, 17H...) indicate the signal attenuation introduced by the cable in approximately 2 dB per step. 3.4.4 RECEIVE SENSITIVITY For short haul application, the Receive Sensitivity for both E1 and T1/ J1 is -10 dB. For long haul application, the receive sensitivity is -43 dB for E1 and -36 dB for T1/J1. When the chip is configured by hardware, the short haul or long haul operating mode can be selected by setting EQn on a per channel basis. For short haul mode, the Receive Sensitivity for both E1 and T1/J1 is -10 dB. For long haul mode, the receive sensitivity is -43 dB for E1 and -36 dB for T1/J1. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details. 3.4.5 DATA SLICER The Data Slicer is used to generate a standard amplitude mark or a space according to the amplitude of the input signals. The threshold can be 40%, 50%, 60% or 70%, as selected by the SLICE[1:0] bits (RCF2, 0BH...). The output of the Data Slicer is forwarded to the CDR (Clock & Data Recovery) unit or to the RDPn/RDNn pins directly if the CDR is disabled. 3.4.6 CDR (Clock & Data Recovery) The CDR is used to recover the clock and data from the received signal. The recovered clock tracks the jitter in the data output from the Data Slicer and keeps the phase relationship between data and clock during the absence of the incoming pulse. The CDR can also be by-passed in the Dual Rail mode. When CDR is by-passed, the data from the Data Slicer is output to the RDPn/RDNn pins directly.
In T1/J1 applications, the R_MD[1:0] bits (RCF0, 09H...) is used to select the AMI decoder or B8ZS decoder. In E1 applications, the R_MD[1:0] bits (RCF0, 09H...) are used to select the AMI decoder or HDB3 decoder. When the chip is configured by hardware, the operation mode of receive and transmit path can be selected by setting RXTXM[1:0] pins on a global basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details. 3.4.8 RECEIVE PATH SYSTEM INTERFACE The receive path system interface consists of RCLKn pin, RDn/RDPn pin and RDNn pin. In E1 mode, the RCLKn outputs a recovered 2.048 MHz clock. In T1/J1 mode, the RCLKn outputs a recovered 1.544 MHz clock. The received data is updated on the RDn/RDPn and RDNn pins on the active edge of RCLKn. The active edge of RCLKn can be selected by the RCLK_SEL bit (RCF0, 09H...). And the active level of the data on RDn/ RDPn and RDNn can be selected by the RD_INV bit (RCF0, 09H...). In hardware control mode, only the active edge of RCLKn can be selected. If RCLKE is set to high, the falling edge will be chosen as the active edge of RCLKn. If RCLKE is set to low, the rising edge will be chosen as the active edge of RCLKn. The active level of the data on RDn/RDPn and RDNn is the same as that in software control mode. The received data can be output to the system side in two different ways: Single Rail or Dual Rail, as selected by R_MD bit [1] (RCF0, 09H...). In Single Rail mode, only RDn pin is used to output data and the RDNn/CVn pin is used to report the received errors. In Dual Rail Mode, both RDPn pin and RDNn pin are used for outputting data. In the receive Dual Rail mode, the CDR unit can be by-passed by setting R_MD[1:0] to `11' (binary). In this situation, the output data from the Data Slicer will be output to the RDPn/RDNn pins directly, and the RCLKn outputs the exclusive OR (XOR) of the RDPn and RDNn. This is called receiver slicer mode. In this case, the transmit path is still operating in Dual Rail mode. 3.4.9 RECEIVE PATH POWER DOWN The receive path can be powered down individually by setting R_OFF bit (RCF0, 09H...) to `1'. In this case, the RCLKn, RDn/RDPn, RDNn and LOSn will be logic low. In hardware control mode, receiver power down can be selected by pulling RPDn pin to high on a per channel basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for more details.
25
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
3.4.10 G.772 NON-INTRUSIVE MONITORING In applications using only one channel, channel 1 can be configured to monitor the data received or transmitted in channel 2. The MONT[1:0] bits (GCF, 20H) determine which direction (transmit/receive) will be monitored. The monitoring is non-intrusive per ITU-T G.772. Figure-11 illustrates the concept.
The monitored line signal (transmit or receive) goes through Channel 1's Clock and Data Recovery. The signal can be observed digitally at the RCLK1, RD1/RDP1 and RDN1. If Channel 1 is configured to Remote Loopback while in the Monitoring mode, the monitored data will be output on TTIP1/TRING1.
Channel 2
LOS2 LOS/AIS Detection B8ZS/ HDB3/AMI Decoder Clock and Data Recovery Receiver Internal Termination RTIP2 RRING2
RCLK2 RD2/RDP2 CV2/RDN2
Jitter Attenuator
Data Slicer
Adaptive Equalizer
TCLK2 TD2/TDP2 TDN2
B8ZS/ HDB3/AMI Encoder
Jitter Attenuator
Waveform Shaper/LBO
Line Driver
Transmitter Internal Termination
TTIP2 TRING2
Channel 1
LOS1 DLOS/AIS Detection B8ZS/ HDB3/AMI Decoder Clock and Data Recovery ALOS Detection Receiver Internal Termination
G.772 Monitor
RCLK1 RD1/RDP1 CV1/RDN1
Jitter Attenuator
Data Slicer
Adaptive Equalizer
RTIP1 RRING1
Remote Loopback
TCLK1 TD1/TDP1 TDN1 B8ZS/ HDB3/AMI Encoder Jitter Attenuator Waveform Shaper/LBO Line Driver Transmitter Internal Termination TTIP1 TRING1
Figure-11 G.772 Monitoring Diagram
26
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
3.5
JITTER ATTENUATOR
There is one Jitter Attenuator in each channel of the LIU. The Jitter Attenuator can be deployed in the transmit path or the receive path, and can also be disabled. This is selected by the JACF[1:0] bits (JACF, 03H...). In hardware control mode, Jitter Attenuator position, bandwidth and the depth of FIFO can be selected by JA[1:0] pins on a global basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details. 3.5.1 JITTER ATTENUATION FUNCTION DESCRIPTION The Jitter Attenuator is composed of a FIFO and a DPLL, as shown in Figure-12. The FIFO is used as a pool to buffer the jittered input data, then the data is clocked out of the FIFO by a de-jittered clock. The depth of the FIFO can be 32 bits, 64 bits or 128 bits, as selected by the JADP[1:0] bits (JACF, 03H...). In hardware control mode, the depth of FIFO can be selected by JA[1:0] pins on a global basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details. Consequently, the constant delay of the Jitter Attenuator will be 16 bits, 32 bits or 64 bits. Deeper FIFO can tolerate larger jitter, but at the cost of increasing data latency time.
In E1 applications, the Corner Frequency of the DPLL can be 0.9 Hz or 6.8 Hz, as selected by the JABW bit (JACF, 03H...). In T1/J1 applications, the Corner Frequency of the DPLL can be 1.25 Hz or 5.00 Hz, as selected by the JABW bit (JACF, 03H...). The lower the Corner Frequency is, the longer time is needed to achieve synchronization. When the incoming data moves faster than the outgoing data, the FIFO will overflow. This overflow is captured by the JAOV_IS bit (INTS1, 19H...). If the incoming data moves slower than the outgoing data, the FIFO will underflow. This underflow is captured by the JAUD_IS bit (INTS1, 19H...). For some applications that are sensitive to data corruption, the JA limit mode can be enabled by setting JA_LIMIT bit (JACF, 03H...) to `1'. In the JA limit mode, the speed of the outgoing data will be adjusted automatically when the FIFO is close to its full or emptiness. The criteria of starting speed adjustment are shown in Table-16. The JA limit mode can reduce the possibility of FIFO overflow and underflow, but the quality of jitter attenuation is deteriorated.
Table-16 Criteria of Starting Speed Adjustment
FIFO Depth Criteria for Adjusting Data Outgoing Speed
32 Bits
2 bits close to its full or emptiness 3 bits close to its full or emptiness 4 bits close to its full or emptiness
Jittered Data
FIFO 32/64/128
W R
RDn/RDPn De-jittered Data RDNn
64 Bits 128 Bits
3.5.2
JITTER ATTENUATOR PERFORMANCE
Jittered Clock
DPLL
De-jittered Clock RCLKn
The performance of the Jitter Attenuator in the IDT82V2082 meets the ITU-T I.431, G.703, G.736-739, G.823, G.824, ETSI 300011, ETSI TBR12/ 13, AT&T TR62411 specifications. Details of the Jitter Attenuator performance is shown in Table-68 Jitter Tolerance and Table-69 Jitter Attenuator Characteristics.
MCLK
Figure-12 Jitter Attenuator
27
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
3.6
3.6.1
LOS AND AIS DETECTION
LOS DETECTION
The Loss of Signal Detector monitors the amplitude of the incoming signal level and pulse density of the received signal on RTIPn and RRINGn. * LOS declare (LOS=1) A LOS is detected when the incoming signal has "no transitions", i.e., when the signal level is less than Q dB below nominal for N consecutive pulse intervals. Here N is defined by LAC bit (MAINT0, 0CH...). LOS will be declared by pulling LOSn pin to high (LOS=1) and LOS interrupt will be generated if it is not masked. * LOS clear (LOS=0) The LOS is cleared when the incoming signal has "transitions", i.e., when the signal level is greater than P dB below nominal and has an average pulse density of at least 12.5% for M consecutive pulse intervals, starting with the receipt of a pulse. Here M is defined by LAC bit (MAINT0, 0CH...). LOS status is cleared by pulling LOSn pin to low.
* LOS detect level threshold In short haul mode, the amplitude threshold Q is fixed on 800 mVpp, while P=Q+200 mVpp (200 mVpp is the LOS level detect hysteresis). In long haul mode, the value of Q can be selected by LOS[4:0] bit (RCF1, 0AH...), while P=Q+4 dB (4 dB is the LOS level detect hysteresis). The LOS[4:0] default value is 10101 (-46 dB). When the chip is configured by hardware, the LOS detect level is fixed if the IDT82V2082 operates in long haul mode. It is -46dB (E1) and -38dB (T1/J1). * Criteria for declare and clear of a LOS detect The detection supports the ANSI T1.231 and I.431 for T1/J1 mode and G.775 and ETSI 300233/I.431 for E1 mode. The criteria can be selected by LAC bit (MAINT0, 0CH...) and T1E1 bit (GCF, 20H). Table-17 and Table-18 summarize LOS declare and clear criteria for both short haul and long haul application. * All Ones output during LOS On the system side, the RDPn/RDNn will reflect the input pulse "transition" at the RTIPn/RRINGn side and output recovered clock (but the quality of the output clock can not be guaranteed when the input level is lower than the maximum receive sensitivity) when AISE bit (MAINT0, 0CH...) is 0; or output All Ones as AIS when AISE bit (MAINT0, 0CH...) is 1. In this case RCLKn output is replaced by MCLK. On the line side, the TTIPn/TRINGn will output All Ones as AIS when ATAO bit (MAINT0, 0CH...) is 1. The All Ones pattern uses MCLK as the reference clock. LOS indicator is always active for all kinds of loopback modes.
LOS=1
signal level>P density=OK (observing windows= M)
signal levelLOS=0
Figure-13 LOS Declare and Clear
Table-17 LOS Declare and Clear Criteria for Short Haul Mode
Control bit LOS declare threshold LOS clear threshold
T1E1
LAC 0=T1.231 Level < 800 mVpp N=175 bits Level > 1 Vpp M=128 bits 12.5% mark density <100 consecutive zeroes Level > 1 Vpp M=128 bits 12.5% mark density <100 consecutive zeroes Level > 1 Vpp M=32 bits 12.5% mark density <16 consecutive zeroes Level > 1 Vpp M=32 bits 12.5% mark density <16 consecutive zeroes
1=T1/J1 1=I.431 Level < 800 mVpp N=1544 bits
Level < 800 mVpp N=32 bits 0=G.775 0=E1 Level < 800 mVpp N=2048 bits 1=I.431/ETSI
28
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-18 LOS Declare and Clear Criteria for Long Haul Mode
Control bit LOS declare threshold LOS clear threshold Note
T1E1
LAC
LOS[4:0]
Q (dB) -4 -6 ... -38 ... -46 -48 -4 -16 -18 ... -30 -32 ... -38 ... -46 -48 -4 ... -8 -10 ... -36 -38 ... -46 -48 -4 -6 ... -20 -22 ... -46 -48 Level < Q N=2048 bits Level > Q+ 4dB M=32 bits 12.5% mark density <16 consecutive zeroes I.431 Level detect range is -6 to -20 dB Level < Q N=32 bits Level > Q+ 4dB M=32 bits 12.5% mark density <16 consecutive zeroes G.775 Level detect range is -9 to -35 dB Level < Q N=175 bits Level > Q+ 4dB M=128 bits 12.5% mark density <100 consecutive zeroes
0
00000 00001 ... T1.231 10001 ... 10101 10110-11111 00000 ... 00110
Level < Q N=1544 bits
1=T1/J1
1
I.431 00111 ... 01101 01110 ... 10001 ... 10101 10110-11111 00000 ... 00010
Level > Q+ 4dB M=128 bits 12.5% mark density <100 consecutive zeroes
I.431 Level detect range is -18 to -30 dB
-
-
0
00011 G.775 ... 10000 10001 ... 10101(default) 10110-11111 00000 00001 I.431/ ... ETSI 01000 01001 ... 10101(default) 10110-11111
0=E1
1
3.6.2
AIS DETECTION
The Alarm Indication Signal can be detected by the IDT82V2082 when the Clock & Data Recovery unit is enabled. The status of AIS detection is reflected in the AIS_S bit (STAT0, 16H...). In T1/J1 applications, the criteria for declaring/clearing AIS detection are in compliance with the ANSI
T1.231. In E1 applications, the criteria for declaring/clearing AIS detection comply with the ITU G.775 or the ETSI 300233, as selected by the LAC bit (MAINT0, 0CH...). Table-19 summarizes different criteria for AIS detection Declaring/Clearing.
Table-19 AIS Condition
ITU G.775 for E1 (LAC bit is set to `0' by default) AIS detected AIS cleared ETSI 300233 for E1 (LAC bit is set to `1') ANSI T1.231 for T1/J1
Less than 3 zeros contained in each of two consecutive Less than 3 zeros contained in a 512-bit Less than 9 zeros contained in an 8192-bit stream 512-bit streams are received stream are received (a ones density of 99.9% over a period of 5.3ms) 3 or more zeros contained in each of two consecutive 3 or more zeros contained in a 512-bit 9 or more zeros contained in an 8192-bit stream 512-bit streams are received stream are received are received
29
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
3.7
TRANSMIT AND DETECT INTERNAL PATTERNS
The internal patterns (All Ones, All Zeros, PRBS/QRSS pattern and Activate/Deactivate Loopback Code) will be generated and detected by IDT82V2082. TCLKn is used as the reference clock by default. MCLK can also be used as the reference clock by setting the PATT_CLK bit (MAINT0, 0CH...) to `1'. If the PATT_CLK bit (MAINT0, 0CH...) is set to `0' and the PATT[1:0] bits (MAINT0, 0CH...) are set to `00', the transmit path will operate in normal mode. When the chip is configured by hardware, the transmit path will operate in normal mode by setting PATTn[1:0] pins to `00' on a per channel basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details. 3.7.1 TRANSMIT ALL ONES In transmit direction, the All Ones data can be inserted into the data stream when the PATT[1:0] bits (MAINT0, 0CH...) are set to `01'. The transmit data stream is output from TTIPn/TRINGn. In this case, either TCLKn or MCLK can be used as the transmit clock, as selected by the PATT_CLK bit (MAINT0, 0CH...). In hardware control mode, the All Ones data can be inserted into the data stream in transmit direction by setting PATTn[1:0] pins to `01' on a per channel basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details. 3.7.2 TRANSMIT ALL ZEROS If the PATT_CLK bit (MAINT0, 0CH...) is set to `1', the All Zeros will be inserted into the transmit data stream when the PATT[1:0] bits (MAINT0, 0CH...) are set to `00'. 3.7.3 PRBS/QRSS GENERATION AND DETECTION A PRBS/QRSS will be generated in the transmit direction and detected in the receive direction by IDT82V2082. The QRSS is 220-1 for T1/J1 applications and the PRBS is 215-1 for E1 applications, with maximum zero restrictions according to the AT&T TR62411 and ITU-T O.151. When the PATT[1:0] bits (MAINT0, 0CH...) are set to `10', the PRBS/ QRSS pattern will be inserted into the transmit data stream with the MSB first. The PRBS/QRSS pattern will be transmitted directly or invertedly. In hardware control mode, the PRBS data will be generated in the transmit direction and inserted into the transmit data stream by setting PATTn[1:0] pins to `10' on a per channel basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details. The PRBS/QRSS in the received data stream will be monitored. If the PRBS/QRSS has reached synchronization status, the PRBS_S bit (STAT0, 16H...) will be set to `1', even in the presence of a logic error rate less than or equal to 10-1. The criteria for setting/clearing the PRBS_S bit are shown in Table-20.
PRBS data can be inverted through setting the PRBS_INV bit (MAINT0, 0CH...). Any change of PRBS_S bit will be captured by PRBS_IS bit (INTS0, 18H...). The PRBS_IES bit (INTES, 15H...) can be used to determine whether the `0' to `1' change of PRBS_S bit will be captured by the PRBS_IS bit or any changes of PRBS_S bit will be captured by the PRBS_IS bit. When the PRBS_IS bit is `1', an interrupt will be generated if the PRBS_IM bit (INTM0, 13H...) is set to `1'. The received PRBS/QRSS logic errors can be counted in a 16-bit counter if the ERR_SEL [1:0] bits (MAINT6, 12H...) are set to `00'. Refer to 3.9 ERROR DETECTION/COUNTING AND INSERTION for the operation of the error counter.
3.8
LOOPBACK
To facilitate testing and diagnosis, the IDT82V2082 provides four different loopback configurations: Analog Loopback, Digital Loopback, Remote Loopback and Inband Loopback. 3.8.1 ANALOG LOOPBACK When the ALP bit (MAINT1, 0DH...) is set to `1', the corresponding channel is configured in Analog Loopback mode. In this mode, the transmit signals are looped back to the Receiver Internal Termination in the receive path then output from RCLKn, RDn, RDPn/RDNn. At the same time, the transmit signals are still output to TTIPn/TRINGn in transmit direction. Figure-14 shows the process. In hardware control mode, Analog Loopback can be selected by setting LPn[1:0] pins to `01' on a per channel basis. 3.8.2 DIGITAL LOOPBACK When the DLP bit (MAINT1, 0DH...) is set to `1', the corresponding channel is configured in Digital Loopback mode. In this mode, the transmit signals are looped back to the jitter attenuator (if enabled) and decoder in receive path, then output from RCLKn, RDn, RDPn/RDNn. At the same time, the transmit signals are still output to TTIPn/TRINGn in transmit direction. Figure-15 shows the process. Both Analog Loopback mode and Digital Loopback mode allow the sending of the internal patterns (All Ones, All Zeros, PRBS, etc.) which will overwrite the transmit signals. In this case, either TCLKn or MCLK can be used as the reference clock for internal patterns transmission. In hardware control mode, Digital Loopback can be selected by setting LPn[1:0] pins to `10' on a per channel basis. 3.8.3 REMOTE LOOPBACK When the RLP bit (MAINT1, 0DH...) is set to `1', the corresponding channel is configured in Remote Loopback mode. In this mode, the recovered clock and data output from Clock and Data Recovery on the receive path is looped back to the jitter attenuator (if enabled) and Waveform Shaper in transmit path. Figure-16 shows the process. In hardware control mode, Remote Loopback can be selected by setting LPn[1:0] pins to `11' on a per channel basis.
Table-20 Criteria for Setting/Clearing the PRBS_S Bit
PRBS/QRSS 6 or less than 6 bit errors detected in a 64 bits hopping window.
Detection
PRBS/QRSS More than 6 bit errors detected in a 64 bits hopping window.
Missing
30
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
One of the Two Identical Channels
LOSn
LOS/AIS Detection B8ZS/ HDB3/AMI Decoder Clock and Data Recovery Receiver Internal Termination RTIPn RRINGn
RCLKn RDn/RDPn CVn/RDNn
Jitter Attenuator
Data Slicer
Adaptive Equalizer
Analog Loopback
TCLKn TDn/TDPn TDNn B8ZS/ HDB3/AMI Encoder Jitter Attenuator Waveform Shaper/LBO Line Driver Transmitter Internal Termination TTIPn TRINGn
Figure-14 Analog Loopback
One of the Two Identical Channels
LOSn
LOS/AIS Detection B8ZS/ HDB3/AMI Decoder Clock and Data Recovery Receiver Internal Termination RTIPn RRINGn
RCLKn RDn/RDPn CVn/RDNn
Jitter Attenuator
Data Slicer
Adaptive Equalizer
Digital Loopback
TCLKn TDn/TDPn TDNn B8ZS/ HDB3/AMI Encoder Jitter Attenuator Waveform Shaper/LBO Line Driver Transmitter Internal Termination TTIPn TRINGn
Figure-15 Digital Loopback
One of the Two Identical Channels
LOSn
LOS/AIS Detection B8ZS/ HDB3/AMI Decoder Clock and Data Recovery Receiver Internal Termination RTIPn RRINGn
RCLKn RDn/RDPn CVn/RDNn
Jitter Attenuator
Data Slicer
Adaptive Equalizer
Remote Loopback
TCLKn TDn/TDPn TDNn B8ZS/ HDB3/AMI Encoder Jitter Attenuator Waveform Shaper/LBO Line Driver Transmitter Internal Termination TTIPn TRINGn
Figure-16 Remote Loopback
31
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
3.8.4
INBAND LOOPBACK
When PATT[1:0] bits (MAINT0, 0CH...) are set to `11', the corresponding channel is configured in Inband Loopback mode. In this mode, an unframed activate/Deactivate Loopback Code is generated repeatedly in transmit direction per ANSI T1. 403 which overwrite the transmit signals. In receive direction, the framed or unframed code is detected per ANSI T1. 403, even in the presence of 10-2 bit error rate. If the Automatic Remote Loopback is enabled by setting ARLP bit (MAINT1, 0DH...) to `1', the chip will establish/demolish the Remote Loopback based on the reception of the Activate Loopback Code/ Deactivate Loopback Code for 5.1 s. If the ARLP bit (MAINT1, 0DH...) is set to `0', the Remote Loopback can also be demolished forcedly. 3.8.4.1 Transmit Activate/Deactivate Loopback Code The pattern of the transmit Activate/Deactivate Loopback Code is defined by the TIBLB[7:0] bits (MAINT3, 0FH...). Whether the code represents an Activate Loopback Code or a Deactivate Loopback Code is judged by the far end receiver. The length of the pattern ranges from 5 bits to 8 bits, as selected by the TIBLB_L[1:0] bits (MAINT2, 0EH...). The pattern can be programmed to 6-bit-long or 8-bit-long respectively by repeating itself if it is 3-bit-long or 4-bit-long. When the PATT[1:0] bits (MAINT0, 0CH...) are set to `11', the transmission of the Activate/Deactivate Loopback Code is initiated. If the PATT_CLK bit (MAINT0, 0CH...) is set to `0' and the PATT[1:0] bits (MAINT0, 0CH...) are set to `00', the transmission of the Activate/Deactivate Loopback Code will stop. The local transmit activate/deactivate code setting should be the same as the receive code setting in the remote end. It is the same thing for the other way round. 3.8.4.2 Receive Activate/Deactivate Loopback Code The pattern of the receive Activate Loopback Code is defined by the RIBLBA[7:0] bits (MAINT4, 10H...). The length of this pattern ranges from 5 bits to 8 bits, as selected by the RIBLBA_L [1:0] bits (MAINT2, 0EH...). The pattern can be programmed to 6-bit-long or 8-bit-long respectively by repeating itself if it is 3-bit-long or 4-bit-long. The pattern of the receive Deactivate Loopback Code is defined by the RIBLBD[7:0] bits (MAINT5, 11H...). The length of the receive Deactivate Loopback Code ranges from 5 bits to 8 bits, as selected by the RIBLBD_L[1:0] bits (MAINT2, 0EH...). The pattern can be programmed to
6-bit-long or 8-bit-long respectively by repeating itself if it is 3-bit-long or 4bit-long. After the Activate Loopback Code has been detected in the receive data for more than 30 ms (in E1 mode) / 40 ms (in T1/J1 mode), the IBLBA_S bit (STAT0, 16H...) will be set to `1' to declare the reception of the Activate Loopback Code. After the Deactivate Loopback Code has been detected in the receive data for more than 30 ms (In E1 mode) / 40 ms (In T1/J1 mode), the IBLBD_S bit (STAT0, 16H...) will be set to `1' to declare the reception of the Deactivate Loopback Code. When the IBLBA_IES bit (INTES, 15H...) is set to `0', only the `0' to `1' transition of the IBLBA_S bit will generate an interrupt and set the IBLBA_IS bit (INTS0, 18H...) to `1'. When the IBLBA_IES bit is set to `1', any changes of the IBLBA_S bit will generate an interrupt and set the IBLBA_IS bit (INTS0, 18H...) to `1'. The IBLBA_IS bit will be reset to `0' after being read. When the IBLBD_IES bit (INTES, 15H...) is set to `0', only the `0' to `1' transition of the IBLBD_S bit will generate an interrupt and set the IBLBD_IS bit (INTS0, 18H...) to `1'. When the IBLBD_IES bit is set to `1', any changes of the IBLBD_S bit will generate an interrupt and set the IBLBD_IS bit (INTS0, 18H...) to `1'. The IBLBD_IS bit will be reset to `0' after being read. 3.8.4.3 Automatic Remote Loopback When ARLP bit (MAINT1, 0DH...) is set to `1', the corresponding channel is configured into the Automatic Remote Loopback mode. In this mode, if the Activate Loopback Code has been detected in the receive data for more than 5.1 s, the Remote Loopback (shown as Figure-16) will be established automatically, and the RLP_S bit (STAT1, 17H...) will be set to `1' to indicate the establishment of the Remote Loopback. The IBLBA_S bit (STAT0, 16H...) is set to `1' to generate an interrupt. In this case, the Remote Loopback mode will still be kept even if the receiver stop receiving the Activate Loopback Code. If the Deactivate Loopback Code has been detected in the receive data for more than 5.1 s, the Remote Loopback will be demolished automatically, and the RLP_S bit (STAT1, 17H...) will set to `0' to indicate the demolishment of the Remote Loopback. The IBLBD_S bit (STAT0, 16H...) is set to `1' to generate an interrupt. The Remote Loopback can also be demolished forcedly by setting ARLP bit (MAINT1, 0DH...) to `0'.
32
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
3.9
3.9.1
ERROR DETECTION/COUNTING AND INSERTION
DEFINITION OF LINE CODING ERROR *
The following line encoding errors can be detected and counted by the IDT82V2082: * Received Bipolar Violation (BPV) Error: In AMI coding, when two consecutive pulses of the same polarity are received, a BPV error is declared. * HDB3/B8ZS Code Violation (CV) Error: In HDB3/B8ZS coding, a CV error is declared when two consecutive BPV errors are
detected, and the pulses that have the same polarity as the previous pulse are not the HDB3/B8ZS zero substitution pulses. Excess Zero (EXZ) Error: There are two standards defining the EXZ errors: ANSI and FCC. The EXZ_DEF bit (MAINT6, 12H...) chooses which standard will be adopted by the corresponding channel to judge the EXZ error. Table-21 shows definition of EXZ. In hardware control mode, only ANSI standard is adopted.
Table-21 EXZ Definition
EXZ Definition ANSI AMI HDB3 B8ZS FCC
More than 15 consecutive zeros are detected More than 3 consecutive zeros are detected More than 7 consecutive zeros are detected
More than 80 consecutive zeros are detected More than 3 consecutive zeros are detected More than 7 consecutive zeros are detected
3.9.2
ERROR DETECTION AND COUNTING
Auto Report Mode (CNT_MD=1)
Which type of the receiving errors (Received CV/BPV errors, excess zero errors and PRBS logic errors) will be counted is determined by ERR_SEL[1:0] bits (MAINT6, 12H...). Only one type of receiving error can be counted at a time except that when the ERR_SEL[1:0] bits are set to `11', both CV/BPV and EXZ errors will be detected and counted. The selected type of receiving errors is counted in an internal 16-bit Error Counter. Once an error is detected, an error interrupt which is indicated by corresponding bit in (INTS1, 19H...) will be generated if it is not masked. This Error Counter can be operated in two modes: Auto Report Mode and Manual Report Mode, as selected by the CNT_MD bit (MAINT6, 12H...). In Single Rail mode, once BPV or CV errors are detected, the CVn pin will be driven to high for one RCLK period. * Auto Report Mode In Auto Report Mode, the internal counter starts to count the received errors when the CNT_MD bit (MAINT6, 12H...) is set to `1'. A one-second timer is used to set the counting period. The received errors are counted within one second. If the one-second timer expires, the value in the internal counter will be transferred to (CNT0, 1AH...) and (CNT1, 1BH...), then the internal counter will be reset and start to count received errors for the next second. The errors occurred during the transfer will be accumulated to the next round. The expiration of the one-second timer will set TMOV_IS bit (INTS1, 19H...) to `1', and will generate an interrupt if the TIMER_IM bit (INTM1, 14H...) is set to `0'. The TMOV_IS bit (INTS1, 19H...) will be cleared after the interrupt register is read. The content in the (CNT0, 1AH...) and (CNT1, 1BH...) should be read within the next second. If the counter overflows, a counter overflow interrupt which is indicated by CNT_OV_IS bit (INTS1, 19H...) will be generated if it is not masked by CNT_IM bit (INTM1, 14H...).
N
counting next second repeats the same process
One-Second Timer expired? Y data in counter
CNT0, CNT1 counter 0
Bit TMOV_IS is set to '1'
read the data in CNT0, CNT1 within the next second Bit TMOV_IS is cleared after the interrupt register is read
Figure-17 Auto Report Mode
33
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
* Manual Report Mode In Manual Report Mode, the internal Error Counter starts to count the received errors when the CNT_MD bit (MAINT6, 12H...) is set to `0'. When there is a `0' to `1' transition on the CNT_TRF bit (MAINT6, 12H...), the data in the counter will be transferred to (CNT0, 1AH...) and (CNT1, 1BH...), then the counter will be reset. The errors occurred during the transfer will be accumulated to the next round. If the counter overflows, a counter overflow interrupt indicated by CNT_OV_IS bit (INTS1, 19H...) will be generated if it is not masked by CNT_IM bit (INTM1, 14H...).
Manual Report mode (CNT_MD=0)
3.9.3
BIPOLAR VIOLATION AND PRBS ERROR INSERTION
Only when three consecutive `1's are detected in the transmit data stream, will a `0' to `1' transition on the BPV_INS bit (MAINT6, 12H...) generate a bipolar violation pulse, and the polarity of the second `1' in the series will be inverted. A `0' to `1' transition on the EER_INS bit (MAINT6, 12H...) will generate a logic error during the PRBS/QRSS transmission.
3.10 LINE DRIVER FAILURE MONITORING
The transmit driver failure monitor can be enabled or disabled by setting DFM_OFF bit (TCF1, 05H...). If the transmit driver failure monitor is enabled, the transmit driver failure will be captured by DF_S bit (STAT0, 16H...). The transition of the DF_S bit is reflected by DF_IS bit (INTS0, 18H...), and, if enabled by DF_IM bit (INTM0, 13H...), will generate an interrupt. When there is a short circuit on the TTIPn/TRINGn port, the output current will be limited to 100 mA (typical), and an interrupt will be generated. In hardware control mode, the transmit driver failure monitor is always enabled.
counting N A '0' to '1' transition on CNT_TRF? Y CNT0, CNT1 counter counter 0 data in next round repeat the same process
Read the data in CNT0, CNT1 within next round1 Reset CNT_TRF for the next '0' to '1' transition
Figure-18 Manual Report Mode
Note: It is recommended that users should do the followings within next round of error counting: Read the data in CNT0 and CNT1; Reset CNT_TRF bit for the next `0' to `1' transition on this bit.
34
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
3.11 MCLK AND TCLK
3.11.1 MASTER CLOCK (MCLK) MCLK is an independent, free-running reference clock. MCLK is 1.544 MHz for T1/J1 applications and 2.048 MHz in E1 mode. This reference clock is used to generate several internal reference signals: * Timing reference for the integrated clock recovery unit. * Timing reference for the integrated digital jitter attenuator. * Timing reference for microcontroller interface. * Generation of RCLK signal during a loss of signal condition if AIS is enabled. * Reference clock during Transmit All Ones (TAOS), all zeros, PRBS/ QRSS and Inband Loopback code if it is selected as the reference clock. For ATAO and AIS, MCLK is always used as the reference clock. * Reference clock during Transmit All Ones (TAO) condition or sending PRBS/QRSS in hardware control mode. Figure-19 shows the chip operation status in different conditions of MCLK and TCLKn. The missing of MCLK will set all the TTIPn/TRINGn to high impedance state.
3.11.2 TRANSMIT CLOCK (TCLK) TCLKn is used to sample the transmit data on TDn/TDPn, TDNn. The active edge of TCLKn can be selected by the TCLK_SEL bit (TCF0, 04H...). During Transmit All Ones, PRBS/QRSS patterns or Inband Loopback Code, either TCLKn or MCLK can be used as the reference clock. This is selected by the PATT_CLK bit (MAINT0, 0CH...). But for Automatic Transmit All Ones and AIS, only MCLK is used as the reference clock and the PATT_CLK bit is ignored. In Automatic Transmit All Ones condition, the ATAO bit (MAINT0, 0CH) is set to `1'. In AIS condition, the AISE bit (MAINT0, 0CH) is set to `1'. If TCLKn has been missing for more than 70 MCLK cycles, TCLK_LOS bit (STAT0, 16H...) will be set, and the corresponding TTIPn/TRINGn will become high impedance if this channel is not used for remote loopback or is not using MCLK to transmit internal patterns (TAOS, All Zeros, PRBS and in-band loopback code). When TCLK is detected again, TCLK_LOS bit (STAT0, 16H...) will be cleared. The reference frequency to detect a TCLK loss is derived from MCLK.
MCLK=H/L?
Clocked
yes
L/H
TCLKn status?
clocked
both the transmitters high impedance
generate transmit clock loss interrupt if not masked in software control mode; transmitter n high impedance
normal operation
Figure-19 TCLK Operation Flowchart
35
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
3.12 MICROCONTROLLER INTERFACES
The microcontroller interface provides access to read and write the registers in the device. The chip supports serial microcontroller interface and two kinds of parallel microcontroller interface: Motorola non-Multiplexed mode and Intel non-Multiplexed mode. Different microcontroller interfaces can be selected by setting MODE[1:0] pins to different values. Refer to MODE1 and MODE0 in pin description and 8 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS for details 3.12.1 PARALLEL MICROCONTROLLER INTERFACE The interface is compatible with Motorola or Intel microcontroller. When MODE[1:0] pins are set to `10', Parallel-non-Multiplexed-Motorola interface
is selected. When MODE[1:0] pins are set to `11', Parallel-non-MultiplexedIntel Interface is selected. Refer to 8 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS for details. 3.12.2 SERIAL MICROCONTROLLER INTERFACE When MODE[1:0] pins are set to `01', Serial Interface is selected. In this mode, the registers are programmed through a 16-bit word which contains an 8-bit address/command byte (6 address bits A0~A5 and bit R/W) and an 8-bit data byte (D0~D7). When bit R/W is `1', data is read out from pin SDO. When bit R/W is `0', data is written into SDI pin. Refer to Figure-20.
CS
SCLK SDI A0 A1 A2 A3 A4 A5 R/W D7
D0
D1
D2
D3
D4
D5
D6
address/command byte
SDO D0
input data byte (R/W=0)
D1 D2 D3 D4 D5 D6 D7
remains high impedance
output data byte (R/W=1)
Figure-20 Serial Microcontroller Interface Function Timing
36
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
3.13 INTERRUPT HANDLING
All kinds of interrupt of the IDT82V2082 are indicated by the INT pin. When the INT_PIN[0] bit (GCF, 20H) is `0', the INT pin is open drain active low, with a 10 K external pull-up resistor. When the INT_PIN[1:0] bits (GCF, 20H) are `01', the INT pin is push-pull active low; when the INT_PIN[1:0] bits are `10', the INT pin is push-pull active high. All the interrupt can be disabled by the INTM_GLB bit (GCF, 20H). When the INTM_GLB bit (GCF, 20H) is set to `0', an active level on the INT pin represents an interrupt of the IDT82V2082. The INT_CH[1:0] (GCF, 20H) should be read to identify which channel(s) generate the interrupt. The interrupt event is captured by the corresponding bit in the Interrupt Status Register (INTS0, 18H...) or (INTS1, 19H...). Every kind of interrupt can be enabled/disabled individually by the corresponding bit in the register (INTM0, 13H...) or (INTM1, 14H...). Some event is reflected by the corresponding bit in the Status Register (STAT0, 16H...) or (STAT1, 17H...), and the Interrupt Trigger Edge Selection Register can be used to determine how the Status Register sets the Interrupt Status Register. After the Interrupt Status Register (INTS0, 18H...) or (INTS1, 19H...) is read, the corresponding bit indicating which channel generates the interrupt in the INTCH register (21H) will be reset. Only when all the pending interrupt is acknowledged through reading the Interrupt Status Registers
of all the channels (INTS0, 18H...) or (INTS1, 19H...) will all the bits in the INTCH register (21H) be reset and the INT pin become inactive. There are totally fourteen kinds of events that could be the interrupt source for one channel: (1).LOS Detected (2).AIS Detected (3).Driver Failure Detected (4).TCLK Loss (5).Synchronization Status of PRBS (6).PRBS Error Detected (7).Code Violation Received (8).Excessive Zeros Received (9).JA FIFO Overflow/Underflow (10).Inband Loopback Code Status
(11).Equalizer Out of Range
(12).One-Second Timer Expired (13). Error Counter Overflow (14).Arbitrary Waveform Generator Overflow Table-22 is a summary of all kinds of interrupt and the associated Status bit, Interrupt Status bit, Interrupt Trigger Edge Selection bit and Interrupt Mask bit.
Table-22 Interrupt Event
Interrupt Event Status bit (STAT0, STAT1) Interrupt Status bit (INTS0, INTS1) Interrupt Edge Selection bit (INTES) Interrupt Mask bit (INTM0, INTM1)
LOS Detected AIS Detected Driver Failure Detected TCLK Loss Synchronization Status of PRBS/QRSS PRBS/QRSS Error Code Violation Received Excessive Zeros Received JA FIFO Overflow JA FIFO Underflow Equalizer Out of Range Inband Loopback Activate Code Status Inband Loopback Deactivate Code Status One-Second Timer Expired Error Counter Overflow
LOS_S AIS_S DF_S TCLK_LOS PRBS_S
LOS_IS AIS_IS DF_IS TCLK_LOS_IS PRBS_IS ERR_IS CV_IS EXZ_IS JAOV_IS JAUD_IS
LOS_IES AIS_IES DF_IES TCLK_IES PRBS_IES
LOS_IM AIS_IM DF_IM TCLK_IM PRBS_IM ERR_IM CV_IM EXZ_IM JAOV_IM JAUD_IM
EQ_S IBLBA_S IBLBD_S
EQ_IS IBLBA_IS IBLBD_IS TMOV_IS CNT_OV_IS DAC_OV_IS
EQ_IES IBLBA_IES IBLBD_IES
EQ_IM IBLBA_IM IBLBD_IM TIMER_IM CNT_IM DAC_OV_IM
Arbitrary Waveform Generator Overflow
3.14 5V TOLERANT I/O PINS
All digital input pins will tolerate 5.0 10% volts and are compatible with TTL logic.
*
Hardware Reset: Asserting the RST pin low for a minimum of 100 ns will reset the chip.
3.15 RESET OPERATION
The chip can be reset in two ways: * Software Reset: Writing to the RST register (01H) will reset the chip in 1 s.
37
After reset, all drivers output are in high impedance state, all the internal flip-flops are reset, and all the registers are initialized to default values.
3.16 POWER SUPPLY
This chip uses a single 3.3 V power supply.
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
4
4.1
PROGRAMMING INFORMATION
REGISTER LIST AND MAP
Local Registers. If the configuration of both of the two channels is the same, the COPY bit (GCF, 20H) can be set to `1' to establish the Broadcasting mode. In the Broadcasting mode, the Writing operation on any of the two channels' registers will be copied to the corresponding registers of the other channel.
The IDT82V2082 registers can be divided into Global Registers and Local Registers. The operation on the Global Registers affects both of the two channels while the operation on Local Registers only affects the specific channel. For different channel, the address of Local Register is different. Table-23 is the map of Global Registers and Table-24 is the map of
Table-23 Global Register List and Map
Address (hex) CH1 CH2 Register R/W b7 b6 b5 b4 MAP b3 b2 b1 b0
00 01 20 21
ID RST GCF INTCH
R W R/W R
ID7 MONT1 -
ID6 MONT0 -
ID5 -
ID4 T1E1 -
ID3 COPY -
ID2 INTM_GLB -
ID1 INT_PIN1 INT_CH2
ID0 INT_PIN0 INT_CH1
38
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INDUSTRIAL TEMPERATURE RANGES
Table-24 Per Channel Register List and Map
Address (hex) CH1 CH2 Register R/W b7 b6 b5 b4 MAP b3 b2 b1 b0
Transmit and receive termination register
02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B
22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B
TERM JACF TCF0 TCF1 TCF2 TCF3 TCF4 RCF0 RCF1 RCF2 MAINT0 MAINT1 MAINT2 MAINT3 MAINT4 MAINT5 MAINT6 INTM0 INTM1 INTES STAT0 STAT1 INTS0 INTS1 CNT0 CNT1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R
DONE TIBLB7 RIBLBA7 RIBLBD7 EQ_IM DAC_OV_IM EQ_IES EQ_S EQ_IS DAC_OV_IS Bit7 Bit15
RW WDAT6 EQ_ON PATT1 TIBLB6 RIBLBA6 RIBLBD6 BPV_INS IBLBA_IM JAOV_IM IBLBA_IES IBLBA_S IBLBA_IS JAOV_IS Bit6 Bit14
T_TERM2 JA_LIMIT DFM_OFF SCAL5 UI1 WDAT5 SLICE1 PATT0 TIBLB_L1 TIBLB5 RIBLBA5 RIBLBD5 ERR_INS IBLBD_IM JAUD_IM IBLBD_IES IBLBD_S RLP_S IBLBD_IS JAUD_IS Bit5 Bit13
T_TERM1 JACF1 T_OFF THZ SCAL4 UI0 WDAT4 R_OFF LOS4 SLICE0 PATT_CLK TIBLB_L0 TIBLB4 RIBLBA4 RIBLBD4 EXZ_DEF PRBS_IM ERR_IM PRBS_IES PRBS_S LATT4 PRBS_IS ERR_IS Bit4 Bit12
T_TERM0 JACF0 TD_INV PULS3 SCAL3 SAMP3 WDAT3 RD_INV LOS3 UPDW1 PRBS_INV ARLP RIBLBA_L1 TIBLB3 RIBLBA3 RIBLBD3 ERR_SEL1 TCLK_IM EXZ_IM TCLK_IES TCLK_LOS LATT3 TCLK_LOS_IS EXZ_IS Bit3 Bit11
R_TERM2 JADP1 TCLK_SEL PULS2 SCAL2 SAMP2 WDAT2 RCLK_SEL LOS2 UPDW0 LAC RLP RIBLBA_L0 TIBLB2 RIBLBA2 RIBLBD2 ERR_SEL0 DF_IM CV_IM DF_IES DF_S LATT2 DF_IS CV_IS Bit2 Bit10
R_TERM1 JADP0 T_MD1 PULS1 SCAL1 SAMP1 WDAT1 R_MD1 LOS1 MG1 AISE ALP RIBLBD_L1 TIBLB1 RIBLBA1 RIBLBD1 CNT_MD AIS_IM TIMER_IM AIS_IES AIS_S LATT1 AIS_IS TMOV_IS Bit1 Bit9
R_TERM0 JABW T_MD0 PULS0 SCAL0 SAMP0 WDAT0 R_MD0 LOS0 MG0 ATAO DLP RIBLBD_L0 TIBLB0 RIBLBA0 RIBLBD0 CNT_TRF LOS_IM CNT_IM LOS_IES LOS_S LATT0 LOS_IS CNT_OV_IS Bit0 Bit8
Jitter attenuation control register Transmit path control registers
Receive path control registers
Network Diagnostics control registers
Interrupt control registers
Line status registers
Interrupt status registers
Counter registers
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
4.2
4.2.1
REGISTER DESCRIPTION
GLOBAL REGISTERS
Table-25 ID: Device Revision Register
(R, Address = 00H)
Symbol Bit Default Description
ID[7:0]
7-0
00H
00H is for the first version.
Table-26 RST: Reset Register
(W, Address = 01H)
Symbol Bit Default Description
RST[7:0]
7-0
00H
Software reset. A write operation on this register will reset all internal registers to their default values, and the status of all ports are set to the default status. The content in this register can not be changed.
Table-27 GCF: Global Configuration Register
(R/W, Address = 20H)
Symbol Bit Default Description
MONT[1:0]
7-6
00
G.772 monitor = 00/10: Normal = 01: Receiver 1 monitors the receive path of channel 2 = 11: Receiver 1 monitors the transmit path of channel 2 Reserved. This bit selects the E1 or T1/J1 operation mode globally. = 0: E1 mode is selected. = 1: T1/J1 mode is selected. Enable broadcasting mode. = 0: Broadcasting mode disabled = 1: Broadcasting mode enabled. Writing operation on one channel's register will be copied exactly to the corresponding registers in other channel. Global interrupt enable = 0: Interrupt is globally enabled. But for each individual interrupt, it still can be disabled by its corresponding Interrupt mask Bit. = 1: All the interrupts are disabled for both channels. Interrupt pin control = x0: Open drain, active low (with an external pull-up resistor) = 01: Push-pull, active low = 11: Push-pull, active high
T1E1
5 4
0 0
COPY
3
0
INTM_GLB
2
1
INT_PIN[1:0]
1-0
00
Table-28 INTCH: Interrupt Channel Indication Register
(R, Address =21H)
Symbol Bit Default Description
INT_CH[1:0]
7-2 1-0
000000 00
Reserved. INT_CH[n]=0 indicates that an interrupt was generated by channel [n+1].
40
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
4.2.2
TRANSMIT AND RECEIVE TERMINATION REGISTER
Table-29 TERM: Transmit and Receive Termination Configuration Register
(R/W, Address = 02H, 22H)
Symbol Bit Default Description
T_TERM[2:0]
7-6 5-3
00 000
Reserved. These bits select the internal termination for transmit line impedance matching. = 000: Internal 75 impedance matching = 001: Internal 120 impedance matching = 010: Internal 100 impedance matching = 011: Internal 110 impedance matching = 1xx: Selects external impedance matching resistors for E1 mode only. T1/J1 does not require external impedance resistors (see Table-14). These bits select the internal termination for receive line impedance matching. = 000: Internal 75 impedance matching = 001: Internal 120 impedance matching = 010: Internal 100 impedance matching = 011: Internal 110 impedance matching = 1xx: Selects external impedance matching resistors (see Table-15).
R_TERM[2:0]
2-0
000
4.2.3
JITTER ATTENUATION CONTROL REGISTER
Table-30 JACF: Jitter Attenuation Configuration Register
(R/W, Address = 03H, 23H)
Symbol Bit Default Description
JA_LIMIT JACF[1:0]
7-6 5 4-3
00 1 00
Reserved. = 0: Normal mode = 1: JA limit mode Jitter Attenuation configuration = 00/10: JA not used = 01: JA in transmit path = 11: JA in receive path Jitter Attenuation depth select = 00: 128 bits = 01: 64 bits = 1x: 32 bits Jitter transfer function bandwidth select = 0: 6.8 Hz (E1) 5 Hz (T1/J1) =1: 0.9 Hz (E1) 1.25 Hz (T1/J1)
JADP[1:0]
2-1
00
JABW
0
0
41
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
4.2.4
TRANSMIT PATH CONTROL REGISTERS
Table-31 TCF0: Transmitter Configuration Register 0
(R/W, Address = 04H, 24H)
Symbol Bit Default Description
T_OFF
7-5 4
000 0
Reserved Transmitter power down enable = 0: Transmitter power up = 1: Transmitter power down (line driver high impedance) Transmit data invert = 0: Data on TDn or TDPn/TDNn is active high = 1: Data on TDn or TDPn/TDNn is active low Transmit clock edge select = 0: Data on TDPn/TDNn is sampled on the falling edge of TCLKn = 1: Data on TDPn/TDNn is sampled on the rising edge of TCLKn Transmitter operation mode control T_MD[1:0] select different stages of the transmit data path = 00: Enable HDB3/B8ZS encoder and waveform shaper blocks. Input on pin TDn is single rail NRZ data = 01: Enable AMI encoder and waveform shaper blocks. Input on pin TDn is single rail NRZ data = 1x: Encoder is bypassed, dual rail NRZ transmit data input on pin TDPn/TDNn
TD_INV
3
0
TCLK_SEL
2
0
T_MD[1:0]
0-1
00
Table-32 TCF1: Transmitter Configuration Register 1
(R/W, Address = 05H, 25H)
Symbol Bit Default Description
DFM_OFF
7-6 5
00 0
Reserved. This bit should be `0' for normal operation. Transmit driver failure monitor disable = 0: DFM is enabled = 1: DFM is disabled Transmit line driver high impedance enable = 0: Normal state = 1: Transmit line driver high impedance enable (other transmit path still work normally). These bits select the transmit template/LBO for short-haul/long-haul applications. T1/E1/J1 00001 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 11xx E1 E1 DSX1 DSX1 DSX1 DSX1 DSX1 J1 DS1 DS1 DS1 DS1 TCLK 2.048 MHz 2.048 MHz 1.544 MHz 1.544 MHz 1.544 MHz 1.544 MHz 1.544 MHz 1.544 MHz 1.544 MHz 1.544 MHz 1.544 MHz 1.544 MHz Cable impedance 75 120 100 100 100 100 100 110 100 100 100 100 Cable range or LBO 0-133 ft 133-266 ft 266-399 ft 399-533 ft 533-655 ft 0-655 ft 0 dB LBO -7.5 dB LBO -15.0 dB LBO -22.5 dB LBO Allowable Cable loss 0-43 dB 0-43 dB 0-0.6 dB 0.6-1.2 dB 1.2-1.8 dB 1.8-2.4 dB 2.4-3.0 dB 0-3.0 dB 0-36 dB 0-28.5 dB 0-21 dB 0-13.5 dB
THZ
4
1
PULS[3:0]
3-0
0000
User programmable waveform setting
1. In internal impedance matching mode, for E1/75 cable impedance, the PULS[3:0] bits (TCF1, 05H...) should be set to `0000'. In external impedance matching mode, for E1/75 cable impedance, the PULS[3:0] bits should be set to `0001'.
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-33 TCF2: Transmitter Configuration Register 2
(R/W, Address = 06H, 26H)
Symbol Bit Default Description
SCAL[5:0]
7-6 5-0
00 100001
Reserved. SCAL specifies a scaling factor to be applied to the amplitude of the user-programmable arbitrary pulses which is to be transmitted if needed. The default value of SCAL[5:0] is `100001'. Refer to 3.3.3.3 User-Programmable Arbitrary Waveform. = 110110: Default value for T1 0~133 ft, T1 133~266 ft, T1 266~399 ft, T1 399~533 ft, T1 533~655 ft, J1 0~655 ft, DS1 0 dB LBO. One step change of this value results in 2% scaling up/down against the pulse amplitude. = 010001: Default value for DS1 -7.5 dB LBO. One step change of this value results in 6.25% scaling up/down against the pulse amplitude. = 001000: Default value for DS1 -15.0 dB LBO. One step change of this value results in 12.5% scaling up/down against the pulse amplitude. = 000100: Default value for DS1 -22.5 dB LBO. One step change of this value results in 25% scaling up/down against the pulse amplitude. = 100001: Default value for E1 75 and 120 . One step change of this value results in 3% scaling up/down against the pulse amplitude.
Table-34 TCF3: Transmitter Configuration Register 3
(R/W, Address = 07H, 27H)
Symbol Bit Default Description
DONE RW
7 6
0 0
After `1' is written to this bit, a read or write operation is implemented. This bit selects read or write operation = 0: Write to RAM = 1: Read from RAM These bits specify the unit interval address. There are totally 4 unit intervals. = 00: UI address is 0 (The most left UI) = 01: UI address is 1 = 10: UI address is 2 = 11: UI address is 3 These bits specify the sample address. Each UI has totally 16 samples. = 0000: Sample address is 0 (The most left sample) = 0001: Sample address is 1 = 0010: Sample address is 2 ...... = 1110: Sample address is 14 = 1111: Sample address is 15
UI[1:0]
5-4
00
SAMP[3:0]
3-0
0000
Table-35 TCF4: Transmitter Configuration Register 4
(R/W, Address = 08H, 28H)
Symbol Bit Default Description
WDAT[6:0]
7 6-0
0 0000000
Reserved In Indirect Write operation, the WDAT[6:0] will be loaded to the pulse template RAM, specifying the amplitude of the Sample. After an Indirect Read operation, the amplitude data of the Sample in the pulse template RAM will be output to the WDAT[6:0].
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
4.2.5
RECEIVE PATH CONTROL REGISTERS
Table-36 RCF0: Receiver Configuration Register 0
(R/W, Address = 09H, 29H)
Symbol Bit Default Description
R_OFF
7-5 4
000 0
Reserved Receiver power down enable = 0: Receiver power up = 1: Receiver power down Receive data invert = 0: Data on RDn or RDPn/RDNn is active high = 1: Data on RDn or RDPn/RDNn is active low Receive clock edge select (this bit is ignored in slicer mode) = 0: Data on RDn or RDPn/RDNn is updated on the rising edge of RCLKn = 1: Data on RDn or RDPn/RDNn is updated on the falling edge of RCLKn Receive path decoding selection = 00: Receive data is HDB3 (E1)/B8ZS (T1/J1) decoded and output on RDn pin with single rail NRZ format = 01: Receive data is AMI decoded and output on RDn pin with single rail NRZ format = 10: Decoder is bypassed, re-timed dual rail data with NRZ format output on RDPn/RDNn (dual rail mode with clock recovery) = 11: CDR and decoder are bypassed, slicer data with RZ format output on RDPn/RDNn (slicer mode)
RD_INV
3
0
RCLK_SEL
2
0
R_MD[1:0]
1-0
00
44
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-37 RCF1: Receiver Configuration Register 1
(R/W, Address= 0AH, 2AH)
Symbol Bit Default Description
EQ_ON LOS[4:0]
7 6 5 4:0
0 0 0 10101
Reserved = 0: Receive equalizer off (short haul receiver) = 1: Receive equalizer on (long haul receiver) Reserved. LOS Clear Level (dB) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 -11111 0 >-2 >-4 >-6 >-8 >-10 >-12 >-14 >-16 >-18 >-20 >-22 >-24 >-26 >-28 >-30 >-32 >-34 >-36 >-38 >-40 >-42 >-44 LOS Declare Level (dB) <-4 <-6 <-8 <-10 <-12 <-14 <-16 <-18 <-20 <-22 <-24 <-26 <-28 <-30 <-32 <-34 <-36 <-38 <-40 <-42 <-44 <-46 <-48
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-38 RCF2: Receiver Configuration Register 2
(R/W, Address = 0BH, 2BH)
Symbol Bit Default Description
SLICE[1:0]
7-6 5-4
00 01
Reserved. Receive slicer threshold = 00: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 40% of the peak amplitude. = 01: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 50% of the peak amplitude. = 10: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 60% of the peak amplitude. = 11: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 70% of the peak amplitude. Equalizer observation window = 00: 32 bits = 01: 64 bits = 10: 128 bits = 11: 256 bits Monitor gain setting: these bits select the internal linear gain boost = 00: 0 dB = 01: 22 dB = 10: 26 dB = 11: 32 dB
UPDW[1:0]
3-2
10
MG[1:0]
1-0
00
4.2.6
NETWORK DIAGNOSTICS CONTROL REGISTERS
Table-39 MAINT0: Maintenance Function Control Register 0
(R/W, Address = 0CH, 2CH)
Symbol Bit Default Description
PATT[1:0]
7 6-5
0 00
Reserved. These bits select the internal pattern and insert it into transmit data stream. = 00: Normal operation (PATT_CLK = 0) / insert all zeros (PATT_CLK = 1) = 01: Insert All Ones = 10: Insert PRBS (E1: 215-1) or QRSS (T1/J1: 220-1) = 11: Insert programmable Inband loopback activate or deactivate code (default value 00001) Selects reference clock for transmitting internal pattern = 0: Uses TCLKn as the reference clock = 1: Uses MCLK as the reference clock Inverts PRBS = 0: The PRBS data is not inverted = 1: The PRBS data is inverted before transmission and detection LOS/AIS criterion is selected as below: = 0: G.775 (E1) / T1.231 (T1/J1) = 1: ETSI 300233& I.431 (E1) / I.431 (T1/J1) AIS enable during LOS = 0: AIS insertion on RDPn/RDNn/RCLKn is disabled during LOS = 1: AIS insertion on RDPn/RDNn/RCLKn is enabled during LOS Automatically Transmit All Ones (enabled only when PATT[1:0] = 01) = 0: Disabled = 1: Automatically Transmit All Ones pattern at TTIPn/TRINGn during LOS
PATT_CLK
4
0
PRBS_INV
3
0
LAC
2
0
AISE
1
0
ATAO
0
0
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-40 MAINT1: Maintenance Function Control Register 1
(R/W, Address= 0DH, 2DH)
Symbol Bit Default Description
ARLP
7-4 3
0000 0
Reserved Automatic remote loopback enable = 0: Disables automatic remote loopback (normal transmit and receive operation) = 1: Enables automatic remote loopback Remote loopback enable = 0: Disables remote loopback (normal transmit and receive operation) = 1: Enables remote loopback Analog loopback enable = 0: Disables analog loopback (normal transmit and receive operation) = 1: Enables analog loopback Digital loopback enable = 0: Disables digital loopback (normal transmit and receive operation) = 1: Enables digital loopback
RLP
2
0
ALP
1
0
DLP
0
0
Table-41 MAINT2: Maintenance Function Control Register 2
(R/W, Address = 0EH, 2EH)
Symbol Bit Default Description
TIBLB_L[1:0]
7-6 5-4
00 00
Reserved Defines the length of the user-programmable transmit loopback activate/deactivate code contained in TIBLB register. The default selection is 5 bits length. = 00: 5-bit long activate code in TIBLB [4:0] = 01: 6-bit long activate code in TIBLB [5:0] = 10: 7-bit long activate code in TIBLB [6:0] = 11: 8-bit long activate code in TIBLB [7:0] Defines the length of the user-programmable receive activate loopback code contained in RIBLBA register. The default selection is 5 bits length. = 00: 5-bit long activate code in RIBLBA [4:0] = 01: 6-bit long activate code in RIBLBA [5:0] = 10: 7-bit long activate code in RIBLBA [6:0] = 11: 8-bit long activate code in RIBLBA [7:0] Defines the length of the user-programmable receive deactivate loopback code contained in RIBLBD register. The default selection is 6 bits length. = 00: 5-bit long deactivate code in RIBLBD [4:0] = 01: 6-bit long deactivate code in RIBLBD [5:0] = 10: 7-bit long deactivate code in RIBLBD [6:0] = 11: 8-bit long deactivate code in RIBLBD [7:0]
RIBLBA_L[1:0]
3-2
00
RIBLBD_L[1:0]
1-0
01
Table-42 MAINT3: Maintenance Function Control Register 3
(R/W, Address = 0FH, 2FH)
Symbol Bit Default Description
TIBLB[7:0]
7-0
(000)00001 Defines the user-programmable transmit Inband loopback activate or deactivate code. The default selection is 00001. TIBLB [7:0] form the 8-bit repeating code TIBLB [6:0] form the 7-bit repeating code TIBLB [5:0] form the 6-bit repeating code TIBLB [4:0] form the 5-bit repeating code
47
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-43 MAINT4: Maintenance Function Control Register 4
(R/W, Address = 10H, 30H)
Symbol Bit Default Description
RIBLBA[7:0]
7-0
(000)00001 Defines the user-programmable receive Inband loopback activate code. The default selection is 00001. RIBLBA [7:0] form the 8-bit repeating code RIBLBA [6:0] form the 7-bit repeating code RIBLBA [5:0] form the 6-bit repeating code RIBLBA [4:0] form the 5-bit repeating code
Table-44 MAINT5: Maintenance Function Control Register 5
(R/W, Address = 11H, 31H)
Symbol Bit Default Description
RIBLBD[7:0]
7-0
(00)001001 Defines the user-programmable receive Inband loopback deactivate code. The default selection is 001001. RIBLBD [7:0] form the 8-bit repeating code RIBLBD [6:0] form the 7-bit repeating code RIBLBD [5:0] form the 6-bit repeating code RIBLBD [4:0] form the 5-bit repeating code
Table-45 MAINT6: Maintenance Function Control Register 6
(R/W, Address = 12H, 32H)
Symbol Bit Default Description
BPV_INS
7 6
0 0
Reserved. BPV error insertion A `0' to `1' transition on this bit will cause a single bipolar violation error to be inserted into the transmit data stream. This bit must be cleared and set again for a subsequent error to be inserted. PRBS logic error insertion A `0' to `1' transition on this bit will cause a single PRBS logic error to be inserted into the transmit PRBS data stream. This bit must be cleared and set again for a subsequent error to be inserted. EXZ definition select = 0: ANSI = 1: FCC These bits choose which type of error will be counted = 00: The PRBS logic error is counted by a 16-bit error counter = 01: The EXZ error is counted by a 16-bit error counter = 10: The Received CV (BPV) error is counted by a 16-bit error counter = 11: Both CV (BPV) and EXZ errors are counted by a 16-bit error counter. Counter operation mode select = 0: Manual Report mode = 1: Auto Report mode = 0: Clear this bit for the next `0' to `1' transition on this bit. = 1: Error counting result is transferred to CNT0 and CNT1 and the error counter is reset.
ERR_INS
5
0
EXZ_DEF
4
0
ERR_SEL
3-2
00
CNT_MD
1
0
CNT_TRF
0
0
48
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
4.2.7
INTERRUPT CONTROL REGISTERS
Table-46 INTM0: Interrupt Mask Register 0
(R/W, Address = 13H, 33H)
Symbol Bit Default Description
EQ_IM
7
1
Equalizer out of range interrupt mask = 0: Equalizer out of range interrupt enabled = 1: Equalizer out of range interrupt masked In-band Loopback activate code detect interrupt mask = 0: In-band Loopback activate code detect interrupt enabled = 1: In-band Loopback activate code detect interrupt masked In-band Loopback deactivate code detect interrupt mask = 0: In-band Loopback deactivate code detect interrupt enabled = 1: In-band Loopback deactivate code detect interrupt masked PRBS synchronic signal detect interrupt mask = 0: PRBS synchronic signal detect interrupt enabled = 1: PRBS synchronic signal detect interrupt masked TCLK loss detect interrupt mask = 0: TCLK loss detect interrupt enabled = 1: TCLK loss detect interrupt masked Driver Failure interrupt mask = 0: Driver Failure interrupt enabled = 1: Driver Failure interrupt masked Alarm Indication Signal interrupt mask = 0: Alarm Indication Signal interrupt enabled = 1: Alarm Indication Signal interrupt masked Loss Of Signal interrupt mask = 0: Loss Of Signal interrupt enabled = 1: Loss Of Signal interrupt masked
IBLBA_IM
6
1
IBLBD_IM
5
1
PRBS_IM
4
1
TCLK_IM
3
1
DF_IM
2
1
AIS_IM
1
1
LOS_IM
0
1
49
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-47 INTM1: Interrupt Masked Register 1
(R/W, Address = 14H, 34H)
Symbol Bit Default Description
DAC_OV_IM
7
1
DAC arithmetic overflow interrupt mask = 0: DAC arithmetic overflow interrupt enabled = 1: DAC arithmetic overflow interrupt masked JA overflow interrupt mask = 0: JA overflow interrupt enabled = 1: JA overflow interrupt masked JA underflow interrupt mask = 0: JA underflow interrupt enabled = 1: JA underflow interrupt masked PRBS/QRSS logic error detect interrupt mask = 0: PRBS/QRSS logic error detect interrupt enabled = 1: PRBS/QRSS logic error detect interrupt masked Receive excess zeros interrupt mask = 0: Receive excess zeros interrupt enabled = 1: Receive excess zeros interrupt masked Receive error interrupt mask = 0: Receive error interrupt enabled = 1: Receive error interrupt masked One-Second Timer expiration interrupt mask = 0: One-Second Timer expiration interrupt enabled = 1: One-Second Timer expiration interrupt masked Counter overflow interrupt mask = 0: Counter overflow interrupt enabled = 1: Counter overflow interrupt masked
JAOV_IM
6
1
JAUD_IM
5
1
ERR_IM
4
1
EXZ_IM
3
1
CV_IM
2
1
TIMER_IM
1
1
CNT_IM
0
1
50
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-48 INTES: Interrupt Trigger Edge Select Register
(R/W, Address = 15H, 35H)
Symbol Bit Default Description
EQ_IES
7
0
This bit determines the Equalizer out of range interrupt event. = 0: Interrupt event is generated as a `0' to `1' transition of the EQ_S bit in the STAT0 status register = 1: Interrupt event is generated as either a `0' to `1' transition or a `1' to `0' transition of the EQ_S bit in the STAT0 status register. This bit determines the Inband Loopback Activate Code interrupt event. = 0: Interrupt event is generated as a `0' to `1' transition of the IBLBA_S bit in STAT0 status register = 1: Interrupt event is generated as either a `0' to `1' transition or a `1' to `0' transition of the IBLBA_S bit in STAT0 status register This bit determines the Inband Loopback Deactivate Code interrupt event. = 0: Interrupt event is generated as a `0' to `1' transition of the IBLBD_S bit in STAT0 status register = 1: Interrupt event is generated as either a `0' to `1' transition or a `1' to `0' transition of the IBLBD_S bit in STAT0 status register This bit determines the PRBS/QRSS synchronization status interrupt event. = 0: Interrupt event is generated as a `0' to `1' transition of the PRBS_S bit in STAT0 status register = 1: Interrupt event is generated as either a `0' to `1' transition or a `1' to `0' transition of the PRBS_S bit in STAT0 status register This bit determines the TCLK Loss interrupt event. = 0: Interrupt event is generated as a `0' to `1' transition of the TCLK_LOS bit in STAT0 status register = 1: Interrupt event is generated as either a `0' to `1' transition or a `1' to `0' transition of the TCLK_LOS bit in STAT0 status register This bit determines the Driver Failure interrupt event. = 0: Interrupt event is generated as a `0' to `1' transition of the DF_S bit in STAT0 status register = 1: Interrupt event is generated as either a `0' to `1' transition or a `1' to `0' transition of the DF_S bit in STAT0 status register This bit determines the AIS interrupt event. = 0: Interrupt event is generated as a `0' to `1' transition of the AIS_S bit in STAT0 status register = 1: Interrupt event is generated as either a `0' to `1' transition or a `1' to `0' transition of the AIS_S bit in STAT0 status register This bit determines the LOS interrupt event. = 0: Interrupt is generated as a `0' to `1' transition of the LOS_S bit in STAT0 status register = 1: Interrupt is generated as either a `0' to `1' transition or a `1' to `0' transition of the LOS_S bit in STAT0 status register
IBLBA_IES
6
0
IBLBD_IES
5
0
PRBS_IES
4
0
TCLK_IES
3
0
DF_IES
2
0
AIS_IES
1
0
LOS_IES
0
0
51
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
4.2.8
LINE STATUS REGISTERS
Table-49 STAT0: Line Status Register 0 (real time status monitor)
(R, Address = 16H, 36H)
Symbol Bit Default Description
EQ_S
7
0
Equalizer status indication = 0: In range = 1: Out of range In-band Loopback activate code receive status indication = 0: No Inband Loopback activate code is detected = 1: Activate signal is detected and then received over a period of more than t ms, with a bit error rate less than 102 . The bit remains set as long as the bit error rate does not exceed 10-2. Note1: If automatic remote loopback switching is disabled (ARLP = 0), t = 40 ms. If automatic remote loopback switching is enabled (ARLP = 1), t= 5.1 s. The rising edge of this bit activates the remote loopback operation in local end. Note2: If IBLBA_IM=0: A `0' to `1' transition on this bit causes an activate code detected interrupt if IBLBA _IES bit is `0'; Any changes of this bit causes an activate code detected interrupt if IBLBA _IES bit is set to `1'.
IBLBA_S
6
0
IBLBD_S
5
0
In-band Loopback deactivate code receive status indication = 0: No Inband Loopback deactivate signal is detected = 1: The Inband Loopback deactivate signal is detected and then received over a period of more than t, with a bit error rate less than 10-2. The bit remains set as long as the bit error rate does not exceed 10-2. Note1: If automatic remote loopback switching is disabled (ARLP = 0), t = 40 ms. If automatic remote loopback switching is enabled (ARLP = 1), t = 5.1 s. The rising edge of this bit disables the remote loopback operation. Note2: If IBLBD_IM=0: A `0' to `1' transition on this bit causes a deactivate code detected interrupt if IBLBD _IES bit is `0'; Any changes of this bit causes a deactivate code detected interrupt if IBLBD _IES bit is set to `1'.
PRBS_S
4
0
Synchronous status indication of PRBS/QRSS (real time) = 0: 215-1 (E1) PRBS or 220-1 (T1/J1) QRSS not detected = 1: 215-1 (E1) PRBS or 220-1 (T1/J1) QRSS detected Note: If PRBS_IM=0: A `0' to `1' transition on this bit causes a synchronous status detected interrupt if PRBS _IES bit is `0'. Any changes of this bit causes an interrupt if PRBS_IES bit is set to `1'.
TCLK_LOS
3
0
TCLKn loss indication = 0: Normal = 1: TCLK pin has not toggled for more than 70 MCLK cycles Note: If TCLK_IM=0: A `0' to `1' transition on this bit causes an interrupt if TCLK _IES bit is `0'. Any changes of this bit causes an interrupt if TCLK_IES bit is set to `1'.
DF_S
2
0
Line driver status indication = 0: Normal operation = 1: Line driver short circuit is detected. Note: If DF_IM=0 A `0' to `1' transition on this bit causes an interrupt if DF _IES bit is `0'. Any changes of this bit causes an interrupt if DF_IES bit is set to `1'.
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Table-49 STAT0: Line Status Register 0 (real time status monitor) (Continued)
(R, Address = 16H, 36H)
Symbol Bit Default Description
AIS_S
1
0
Alarm Indication Signal status detection = 0: No AIS signal is detected in the receive path = 1: AIS signal is detected in the receive path Note: If AIS_IM=0 A `0' to `1' transition on this bit causes an interrupt if AIS _IES bit is `0'. Any changes of this bit causes an interrupt if AIS_IES bit is set to `1'.
LOS_S
0
0
Loss Of Signal status detection = 0: Loss of signal on RTIPn/RRINGn is not detected = 1: Loss of signal on RTIPn/RRINGn is detected. Note: If LOS_IM=0 A `0' to `1' transition on this bit causes an interrupt if LOS _IES bit is `0'. Any changes of this bit causes an interrupt if LOS_IES bit is set to `1'.
Table-50 STAT1: Line Status Register 1 (real time status monitor)
(R, Address = 17H, 37H)
Symbol Bit Default Description
RLP_S
7-6 5
00 0
Reserved. Indicating the status of Remote Loopback = 0: The remote loopback is inactive. = 1: The remote loopback is active (closed). Line Attenuation Indication 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 -11111 0 to 2 dB 2 to 4 dB 4 to 6 dB 6 to 8 dB 8 to 10 dB 10 to 12 dB 12 to 14 dB 14 to 16 dB 16 to 18 dB 18 to 20 dB 20 to 22 dB 22 to 24 dB 24 to 26 dB 26 to 28 dB 28 to 30 dB 30 to 32 dB 32 to 34 dB 34 to 36 dB 36 to 38 dB 38 to 40 dB 40 to 42 dB 42 to 44 dB >44 dB
LATT[4:0]
4-0
00000
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4.2.9
INTERRUPT STATUS REGISTERS
Table-51 INTS0: Interrupt Status Register 0
(R, Address = 18H, 38H) (this register is reset and relevant interrupt request is cleared after a read)
Symbol Bit Default Description
EQ_IS
7
0
This bit indicates the occurrence of Equalizer out of range interrupt event. = 0: No interrupt event from the Equalizer out of range occurred = 1: Interrupt event from the Equalizer out of range occurred This bit indicates the occurrence of the Inband Loopback Activate Code interrupt event. = 0: No Inband Loopback Activate Code interrupt event occurred = 1: Inband Loopback Activate Code interrupt event occurred This bit indicates the occurrence of the Inband Loopback Deactivate Code interrupt event. = 0: No Inband Loopback Deactivate Code interrupt event occurred = 1: Interrupt event of the received Inband Loopback Deactivate Code occurred. This bit indicates the occurrence of the interrupt event generated by the PRBS/QRSS synchronization status. = 0: No PRBS/QRSS synchronization status interrupt event occurred = 1: PRBS/QRSS synchronization status interrupt event occurred This bit indicates the occurrence of the interrupt event generated by the TCLK loss detection. = 0: No TCLK loss interrupt event. = 1:TCLK loss interrupt event occurred. This bit indicates the occurrence of the interrupt event generated by the Driver Failure. = 0: No Driver Failure interrupt event occurred = 1: Driver Failure interrupt event occurred This bit indicates the occurrence of the AIS (Alarm Indication Signal) interrupt event. = 0: No AIS interrupt event occurred = 1: AIS interrupt event occurred This bit indicates the occurrence of the LOS (Loss of signal) interrupt event. = 0: No LOS interrupt event occurred = 1: LOS interrupt event occurred
IBLBA_IS
6
0
IBLBD_IS
5
0
PRBS_IS
4
0
TCLK_LOS_IS
3
0
DF_IS
2
0
AIS_IS
1
0
LOS_IS
0
0
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Table-52 INTS1: Interrupt Status Register 1
(R, Address = 19H, 39H) (this register is reset and the relevant interrupt request is cleared after a read)
Symbol Bit Default Description
DAC_OV_IS
7
0
This bit indicates the occurrence of the pulse amplitude overflow of Arbitrary Waveform Generator interrupt event. = 0: No pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred = 1: The pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred This bit indicates the occurrence of the Jitter Attenuator Overflow interrupt event. = 0: No JA Overflow interrupt event occurred = 1: JA Overflow interrupt event occurred This bit indicates the occurrence of the Jitter Attenuator Underflow interrupt event. = 0: No JA Underflow interrupt event occurred = 1: JA Underflow interrupt event occurred This bit indicates the occurrence of the interrupt event generated by the detected PRBS/QRSS logic error. = 0: No PRBS/QRSS logic error interrupt event occurred = 1: PRBS/QRSS logic error interrupt event occurred This bit indicates the occurrence of the Excessive Zeros interrupt event. = 0: No Excessive Zeros interrupt event occurred = 1: EXZ interrupt event occurred This bit indicates the occurrence of the Code Violation interrupt event. = 0: No Code Violation interrupt event occurred = 1: Code Violation interrupt event occurred This bit indicates the occurrence of the One-Second Timer Expiration interrupt event. = 0: No One-Second Timer Expiration interrupt event occurred = 1: One-Second Timer Expiration interrupt event occurred This bit indicates the occurrence of the Counter Overflow interrupt event. = 0: No Counter Overflow interrupt event occurred = 1: Counter Overflow interrupt event occurred
JAOV_IS
6
0
JAUD_IS
5
0
ERR_IS
4
0
EXZ_IS
3
0
CV_IS
2
0
TMOV_IS
1
0
CNT_OV_IS
0
0
4.2.10 COUNTER REGISTERS
Table-53 CNT0: Error Counter L-byte Register 0
(R, Address = 1AH, 3AH)
Symbol Bit Default Description
CNT_L[7:0]
7-0
00H
This register contains the lower eight bits of the 16-bit error counter. CNT_L[0] is the LSB.
Table-54 CNT1: Error Counter H-byte Register 1
(R, Address = 1BH, 3BH)
Symbol Bit Default Description
CNT_H[7:0]
7-0
00H
This register contains the upper eight bits of the 16-bit error counter. CNT_H[7] is the MSB.
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5
HARDWARE CONTROL PIN SUMMARY
Table-55 Hardware Control Pin Summary
Pin No. TQFP 9 10 Symbol MODE1 MODE0 Description MODE[1:0]: Operation mode of Control interface select (global control) 00= Hardware interface 01= Serial interface 10= Parallel - non-Multiplexed - Motorola Interface 11= Parallel - non-Multiplexed - Intel Interface TERMn: Termination interface select (per channel control) These pins select internal or external impedance matching for channel n (n=1 or 2) 0 = ternary interface with internal impedance matching network. 1 = ternary interface with external impedance matching network in E1 mode; ternary interface with external impedance matching network for receiver and ternary interface with internal impedance matching network for transmitter in T1/J1 mode. (External impedance matching is not supported by T1/J1 mode transmitter.) (This applies to ZB die revision only). RXTXM[1:0]: Receive and transmit path operation mode select (global control) 00= single rail with HDB3/B8ZS coding 01= single rail with AMI coding 10= dual rail interface with CDR enable 11= slicer mode PULSn[3:0]: These pins are used to select the following functions (per channel control): * T1/E1/J1 mode (T1/E1/J1 selection of common clock is decided by PULS1n/PULS2n, n=0~3) * Transmit pulse template * Internal termination impedance (75/100/110/120) PULSn[3:0] T1/E1/J1 TCLK Cable impedance (internal matching impedance) Cable range or LBO Cable loss
13 12
TERM1 TERM2
14 15
RXTXM1 RXTXM0
54 53 52 51 50 49 48 47
PULS13 PULS12 PULS11 PULS10 PULS23 PULS22 PULS21 PULS20
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 -1111
E1 E1 DSX1 DSX1 DSX1 DSX1 DSX1 J1 DS1 DS1 DS1 DS1 DS1
2.048 MHz 2.048 MHz 1.544 MHz 1.544 MHz 1.544 MHz 1.544 MHz 1.544 MHz 1.544 MHz 1.544 MHz 1.544 MHz 1.544 MHz 1.544 MHz 1.544 MHz
75 120 100 100 100 100 100 110 100 100 100 100 100
0-133 ft 133-266 ft 266-399 ft 399-533 ft 533-655 ft 0-655 ft 0 dB LBO -7.5 dB LBO -15.0 dB LBO -22.5 dB LBO -
0-43 dB 0-43 dB 0-0.6 dB 0.6-1.2 dB 1.2-1.8 dB 1.8-2.4 dB 2.4-3.0 dB 0-3.0 dB 0-36 dB 0-28.5 dB 0-21 dB 0-13.5 dB 0-13.5 dB
58 60
EQ1 EQ2
EQn: Receive Equalizer on/off control (per channel control) When the chip is configured by hardware with ternary interface, these pins select Short Haul or Long Haul operation mode for channel n (n=1 or 2) 0= short haul (10dB) 1= long haul (36dB for T1/J1, 43 dB for E1) RPDn: Receiver power down control (per channel control) 0= Normal operation 1= receiver power down
57 59
RPD1 RPD2
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Table-55 Hardware Control Pin Summary (Continued)
Pin No. TQFP 46 45 56 55 16 17 Symbol PATT11 PATT10 PATT21 PATT20 JA1 JA0 Description PATTn[1:0]: Transmit test pattern select (per channel control) In hardware control mode, these pins select the transmit pattern for channel n (n=1 or 2) 00 = normal 01= All Ones 10= PRBS 11= transmitter power down JA[1:0]: Jitter attenuation position, bandwidth and the depth of FIFO select (global control) 00= JA is disabled 01= JA in receiver, broad bandwidth, FIFO=64 bits 10= JA in receiver, narrow bandwidth, FIFO=128 bits 11= JA in transmitter, narrow bandwidth, FIFO=128 bits MONTn: Receive Monitor n gain select (per channel control) In hardware control mode with ternary interface, this pin selects the receive monitor gain for receiver n (n=1 or 2) 0= 0 dB 1= 26 dB LPn[1:0]: Loopback mode select (per channel control) When the chip is configured by hardware, these pins are used to select loopback operation modes for channel n (Inband loopback is not provided in hardware control mode). 00= no loopback 01= analog loopback 10= digital loopback 11= remote loopback THZ: Transmitter Driver High Impedance Enable (global control) This signal enables or disables both of the transmitter drivers. A low level on this pin enables both of the two drivers while a high level on this pin places both of the two drivers in high impedance state. RCLKE: the active edge of RCLKn select when hardware control mode is used (global control) 0= select the rising edge as active edge of RCLKn 1= select the falling edge as active edge of RCLKn
19 18
MONT1 MONT2
42 41 44 43
LP11 LP10 LP21 LP20
20
THZ
11
RCLKE
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6
IEEE STD 1149.1 JTAG TEST ACCESS PORT
Clock (TCK) pins. Data is shifted into the registers via the Test Data Input (TDI) pin, and shifted out of the registers via the Test Data Output (TDO) pin. Both TDI and TDO are clocked at a rate determined by TCK. The JTAG boundary scan registers include BSR (Boundary Scan Register), IDR (Device Identification Register), BR (Bypass Register) and IR (Instruction Register). These will be described in the following pages. Refer to Figure-21 for architecture.
The IDT82V2082 supports the digital Boundary Scan Specification as described in the IEEE 1149.1 standards. The boundary scan architecture consists of data and instruction registers plus a Test Access Port (TAP) controller. Control of the TAP is performed through signals applied to the Test Mode Select (TMS) and Test
Digital output pins
Digital input pins
parallel latched output
BSR (Boundary Scan Register)
IDR (Device Identification Register) TDI BR (Bypass Register)
MUX
MUX
IR (Instruction Register)
TDO
Control<6:0> TMS TRST TCK TAP (Test Access Port) Controller Select high impedance enable
Figure-21 JTAG Architecture
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6.1
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER
The IR (Instruction Register) with instruction decode block is used to select the test to be executed or the data register to be accessed or both. The instructions are shifted in LSB first to this 3-bit register. See Table56 for details of the codes and the instructions related.
Table-56 Instruction Register Description
IR CODE INSTRUCTION COMMENTS
000
Extest
The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is placed between TDI and TDO. The signal on the input pins can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. The signal on the output pins can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state.
100
Sample / Preload The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. The normal path between IDT82V2082 logic and the I/O pins is maintained. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. Idcode Bypass The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state. The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay. The instruction is used to bypass the device.
110 111
6.2
6.2.1
JTAG DATA REGISTER
DEVICE IDENTIFICATION REGISTER (IDR)
6.2.2
BYPASS REGISTER (BR)
The IDR can be set to define the producer number, part number and the device revision, which can be used to verify the proper version or revision number that has been used in the system under test. The IDR is 32 bits long and is partitioned as in Table-57. Data from the IDR is shifted out to TDO LSB first.
The BR consists of a single bit. It can provide a serial path between the TDI input and TDO output, bypassing the BSR to reduce test access times. 6.2.3 BOUNDARY SCAN REGISTER (BSR) The BSR can apply and read test patterns in parallel to or from all the digital I/O pins. The BSR is a 98 bits long shift register and is initialized and read using the instruction EXTEST or SAMPLE/PRELOAD. Each pin is related to one or more bits in the BSR. For details, please refer to the BSDL file. 6.2.4 TEST ACCESS PORT CONTROLLER The TAP controller is a 16-state synchronous state machine. Figure-22 shows its state diagram following the description of each state. Note that the figure contains two main branches to access either the data or instruction registers. The value shown next to each state transition in this figure states the value present at TMS at each rising edge of TCK. Please refer to Table-58 for details of the state description.
Table-57 Device Identification Register Description
Bit No.
Comments
Set to `1' Producer Number Part Number Device Revision
0 1-11 12-27 28-31
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Table-58 TAP Controller State Description
STATE DESCRIPTION
Test Logic Reset
In this state, the test logic is disabled. The device is set to normal operation. During initialization, the device initializes the instruction register with the IDCODE instruction. Regardless of the original state of the controller, the controller enters the Test-Logic-Reset state when the TMS input is held high for at least 5 rising edges of TCK. The controller remains in this state while TMS is high. The device processor automatically enters this state at power-up. This is a controller state between scan operations. Once in this state, the controller remains in the state as long as TMS is held low. The instruction register and all test data registers retain their previous state. When TMS is high and a rising edge is applied to TCK, the controller moves to the Select-DR state. This is a temporary controller state and the instruction does not change in this state. The test data register selected by the current instruction retains its previous state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-DR state and a scan sequence for the selected test data register is initiated. If TMS is held high and a rising edge applied to TCK, the controller moves to the Select-IR-Scan state. In this state, the Boundary Scan Register captures input pin data if the current instruction is EXTEST or SAMPLE/PRELOAD. The instruction does not change in this state. The other test data registers, which do not have parallel input, are not changed. When the TAP controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or the Shift-DR state if TMS is low. In this controller state, the test data register connected between TDI and TDO as a result of the current instruction shifts data on stage toward its serial output on each rising edge of TCK. The instruction does not change in this state. When the TAP controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or remains in the Shift-DR state if TMS is low. This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-DR state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between TDI and TDO. For example, this state could be used to allow the tester to reload its pin memory from disk during application of a long test sequence. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The controller remains in this state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-DR state. This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-DR state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The Boundary Scan Register is provided with a latched parallel output to prevent changes while data is shifted in response to the EXTEST and SAMPLE/PRELOAD instructions. When the TAP controller is in this state and the Boundary Scan Register is selected, data is latched into the parallel output of this register from the shift-register path on the falling edge of TCK. The data held at the latched parallel output changes only in this state. All shift-register stages in the test data register selected by the current instruction retain their previous value and the instruction does not change during this state. This is a temporary controller state. The test data register selected by the current instruction retains its previous state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-IR state, and a scan sequence for the instruction register is initiated. If TMS is held high and a rising edge is applied to TCK, the controller moves to the Test-Logic-Reset state. The instruction does not change during this state. In this controller state, the shift register contained in the instruction register loads a fixed value of '100' on the rising edge of TCK. This supports fault-isolation of the board-level serial test data path. Data registers selected by the current instruction retain their value and the instruction does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR state if TMS is held high, or the Shift-IR state if TMS is held low. In this state, the shift register contained in the instruction register is connected between TDI and TDO and shifts data one stage towards its serial output on each rising edge of TCK. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR state if TMS is held high, or remains in the Shift-IR state if TMS is held low. This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-IR state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The pause state allows the test controller to temporarily halt the shifting of data through the instruction register. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The controller remains in this state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-IR state. This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-IR state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
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Table-58 TAP Controller State Description (Continued)
STATE DESCRIPTION
Update-IR
The instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of TCK. When the new instruction has been latched, it becomes the current instruction. The test data registers selected by the current instruction retain their previous value.
1
Test-logic Reset 0
0 Run Test/Idle
1
Select-DR 0 1 Capture-DR 0
1
Select-IR 0 1 Capture-IR 0
1
0 Shift-DR 1 Exit1-DR 0 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 1 Shift-IR 1 Exit1-IR 0
0
1
0
Figure-22 JTAG State Diagram
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7
TEST SPECIFICATIONS
Table-59 Absolute Maximum Rating
Symbol Parameter Min Max Unit
VDDA, VDDD VDDIO VDDT1-2 VDDR1-2
Core Power Supply I/O Power Supply Transmit Power Supply Receive Power Supply Input Voltage, Any Digital Pin Input Voltage, Any RTIPn and RRINGn pin1 ESD Voltage, any pin Transient latch-up current, any pin
-0.5 -0.5 -0.5 -0.5 GND-0.5 GND-0.5 2000 2 500 3
4.6 4.6 4.6 4.6 5.5 VDDR+0.5
V V V V V V V V
Vin
100 -10 10 100 1.23 120 -65 +150
mA mA mA W C C
Iin
Input current, any digital pin
4 4
DC Input current, any analog pin Pd Tc Ts Case Temperature Storage Temperature
Maximum power dissipation in package
CAUTION: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1.Reference to ground 2.Human body model 3.Charge device model 4.Constant input current
Table-60 Recommended Operation Conditions
Symbol Parameter Min Typ Max Unit
VDDA,VDDD VDDIO VDDT VDDR TA
Core Power Supply I/O Power Supply Transmitter Power Supply Receive Power Supply Ambient operating temperature E1, 75 load 50% ones density data 100% ones density data E1, 120 Load 50% ones density data 100% ones density data T1, 100 Load 50% ones density data 100% ones density data J1, 110 Load 50% ones density data 100% ones density data
3.13 3.13 3.13 3.13 -40 -
3.3 3.3 3.3 3.3 25 100 130 110 130 120 170 100 130
3.47 3.47 3.47 3.47 85 110 140 120 140 130 180 110 140
V V V V C mA
Total current dissipation1,2,3
mA
mA
mA
1.Power consumption includes power consumption on device and load. Digital levels are 10% of the supply rails and digital outputs driving a 50 pF capacitive load. 2.Maximum power consumption over the full operating temperature and power supply voltage range. 3.In short haul mode, if internal impedance matching is chosen, E1 75 power dissipation values are measured with template PULS[3:0] = 0000; E1 120 power dissipation values are measured with template PULS[3:0] = 0001; T1 power dissipation values are measured with template PULS[3:0] = 0110; J1 power dissipation values are measured with template PULS[3:0] = 0111.
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Table-61 Power Consumption
Symbol Parameter Min Typ Max1,2 Unit
E1, 3.3 V, 75 Load 50% ones density data: 100% ones density data: E1, 3.3 V, 120 Load 50% ones density data: 100% ones density data: T1, 3.3 V, 100 Load3 50% ones density data: 100% ones density data: J1, 3.3 V, 110 Load 50% ones density data: 100% ones density data: 330 430 490 mW 370 430 400 560 490 630 mW 330 430 490 mW
mW
1.Maximum power and current consumption over the full operating temperature and power supply voltage range. Includes all channels. 2.Power consumption includes power absorbed by line load and external transmitter components. 3.T1 is measured with maximum cable length.
Table-62 DC Characteristics
Symbol Parameter Min Typ Max Unit
VIL VIH VOL VOH VMA II
Input Low Level Voltage Input High Voltage Output Low level Voltage (Iout=1.6mA) Output High level Voltage (Iout=400A) Analog Input Quiescent Voltage (RTIPn, RRINGn pin while floating) Input Leakage Current TMS, TDI, TRST All other digital input pins High Impedance Leakage Current Input capacitance Output load capacitance Output load capacitance (bus pins)
2.0 2.4
1.5
0.8 0.4 VDDIO
V V V V V
-10 -10
50 10 10 15 50 100
A A A pF pF pF
IZL Ci Co Co
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Table-63 E1 Receiver Electrical Characteristics
Symbol Parameter Min Typ Max Unit Test conditions
Receiver sensitivity Short haul with cable loss@1024kHz: Long haul with cable loss@1024kHz: Analog LOS level Short haul Long haul Allowable consecutive zeros before LOS G.775: I.431/ETSI300233: LOS reset Receive Intrinsic Jitter 20Hz - 100kHz Input Jitter Tolerance 1 Hz - 20 Hz 20 Hz - 2.4 KHz 18 KHz - 100 KHz ZDM Receiver Differential Input Impedance Input termination resistor tolerance RRX Receive Return Loss 51 KHz - 102 KHz 102 KHz - 2.048 MHz 2.048 MHz - 3.072 MHz Receive path delay Single rail Dual rail 20 20 20 7 2 37 5 2 20 12.5 800 -4 32 2048
-10 -43
dB
-48
mVp-p dB
A LOS level is programmable for Long Haul
% ones 0.05 U.I. U.I. U.I. U.I. K 1% dB dB dB U.I. U.I.
G.775, ETSI 300 233 JA enabled
G.823, with 6 dB cable attenuation
Internal mode
G.703 Internal termination
RPD
JA disabled
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-64 T1/J1 Receiver Electrical Characteristics
Symbol Parameter Min Typ Max Unit Test conditions
receiver sensitivity Short haul with cable loss@772kHz: Long haul with cable loss@772kHz: Analog LOS level Short haul Long haul Allowable consecutive zeros before LOS T1.231-1993 I.431 LOS reset Receive Intrinsic Jitter 10 Hz - 8 kHz 10 Hz - 40 kHz 8 kHz - 40 kHz Wide band Input Jitter Tolerance 0.1 Hz - 1 Hz 4.9 Hz - 300 Hz 10 KHz - 100 KHz ZDM RRX Receiver Differential Input Impedance Input termination resistor tolerance Receive Return Loss 39 KHz - 77 KHz 77 KHz - 1.544 MHz 1.544 MHz - 2.316 MHz Receive path delay Single rail Dual rail 20 20 20 7 2 138.0 28.0 0.4 20 12.5 800 -4 175 1544
-10 -36
dB
-48
mVp-p dB
A LOS level is programmable for Long Haul
% ones 0.02 0.025 0.025 0.050 U.I. U.I. U.I. U.I. U.I. U.I. U.I. K 1% dB dB dB U.I. U.I.
G.775, ETSI 300 233 JA enabled ( in receive path)
AT&T62411
Internal mode
G.703 Internal termination JA disabled
RPD
65
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-65 E1 Transmitter Electrical Characteristics
Symbol Parameter Min Typ Max Unit
Vo-p
Output pulse amplitudes E1, 75 load E1, 120 load Zero (space) level E1, 75 load E1, 120 load Transmit amplitude variation with supply Difference between pulse sequences for 17 consecutive pulses (T1.102)
2.14 2.7 -0.237 -0.3 -1 232 0.95 0.95
2.37 3.0
2.60 3.3 0.237 0.3 +1 200
V V V V % mV ns
Vo-s
Tpw
Output Pulse Width at 50% of nominal amplitude Ratio of the amplitudes of Positive and Negative Pulses at the center of the pulse interval (G.703) Ratio of the width of Positive and Negative Pulses at the center of the pulse interval (G.703)
244
256 1.05 1.05
RTX
Transmit Return Loss (G.703) 51 KHz - 102 KHz 102 KHz - 2.048 MHz 2.048 MHz - 3.072 MHz 20 15 12 0.050 8.5 4.5 100 dB dB dB U.I. U.I. U.I. mA
JTXp-p Td
Intrinsic Transmit Jitter (TCLK is jitter free) 20 Hz - 100 KHz Transmit path delay (JA is disabled) Single rail Dual rail
Isc
Line short circuit current
66
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-66 T1/J1 Transmitter Electrical Characteristics
Symbol Parameter Min Typ Max Unit
Vo-p Vo-s
Output pulse amplitudes Zero (space) level Transmit amplitude variation with supply Difference between pulse sequences for 17 consecutive pulses (T1.102)
2.4 -0.15 -1
3.0
3.6 0.15 +1 200
V V % mV ns ns
TPW
Output Pulse Width at 50% of nominal amplitude Pulse width variation at the half amplitude (T1.102) Imbalance between Positive and Negative Pulses amplitude (T1.102) Output power level (T1.102) @772kHz @1544kHz (referenced to power at 772kHz)
338 0.95
350
362 20 1.05
12.6 -29 20 15 12
17.9
dBm dBm dB dB dB
RTX
Transmit Return Loss 39 KHz - 77 KHz 77 KHz - 1.544 MHz 1.544 MHz - 2.316 MHz
JTXP-P
Intrinsic Transmit Jitter (TCLK is jitter free) 10 Hz - 8 KHz 8 KHz - 40 KHz 10 Hz - 40 KHz wide band 0.020 0.025 0.025 0.050 8.5 4.5 100 U.I.p-p U.I.p-p U.I.p-p U.I.p-p U.I. U.I. mA
Td
Transmit path delay (JA is disabled) Single rail Dual rail
ISC
Line short circuit current
67
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-67 Transmitter and Receiver Timing Characteristics
Symbol Parameter Min Typ Max Unit
MCLK frequency E1: T1/J1: MCLK tolerance MCLK duty cycle Transmit path TCLK frequency E1: T1/J1: TCLK tolerance TCLK Duty Cycle t1 t2 Transmit Data Setup Time Transmit Data Hold Time Delay time of THZ low to driver high impedance Delay time of TCLK low to driver high impedance Receive path Clock recovery capture E1 range 1 T1/J1 RCLK duty cycle 2 t4 RCLK pulse width 2 E1: T1/J1: t5 RCLK pulse width low time E1: T1/J1: t6 RCLK pulse width high time E1: T1/J1: Rise/fall time 3 t7 Receive Data Setup Time E1: T1/J1: t8 Receive Data Hold Time E1: T1/J1: 200 200 244 324 ns 200 200 244 324 ns 203 259 244 324 285 389 20 ns ns 203 259 244 324 285 389 ns 457 607 488 648 519 689 ns 40 80 180 50 60 % ppm 75 -50 10 40 40 10 2.048 1.544 +50 90 MHz ppm % ns ns us U.I. -100 30 2.048 1.544 100 70 MHz ppm %
1.Relative to nominal frequency, MCLK= 100 ppm 2.RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2UI displacement for E1 per ITU G.823). 3.For all digital outputs. C load = 15pF
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
TCLKn
t1
t2
TDn/TDPn
TDNn
Figure-23 Transmit System Interface Timing
t4 RCLKn t6 t5
t7 RDPn/RDn (RCLK_SEL = 0 software mode) (RCLKE = 0 hardware mode) RDNn/CVn
t8
t7 RDPn/RDn (RCLK_SEL = 1 software mode) (RCLKE = 1 hardware mode) RDNn/CVn
t8
Figure-24 Receive System Interface Timing
Table-68 Jitter Tolerance
Jitter Tolerance Min Typ Max Unit Standard
E1: 1 Hz 20 Hz - 2.4 KHz 18 KHz - 100 KHz T1/J1: 1 Hz 4.9 Hz - 300 Hz 10 KHz - 100 KHz
37 1.5 0.2 138.0 28.0 0.4
U.I. U.I. U.I. U.I. U.I. U.I.
G.823 Cable attenuation is 6dB AT&T 62411
69
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Figure-25 E1 Jitter Tolerance Performance
Figure-26 T1/J1 Jitter Tolerance Performance
70
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-69 Jitter Attenuator Characteristics
Parameter Jitter Transfer Function Corner (-3dB) Frequency Min Typ Max Unit
E1, 32/64/128 bits FIFO JABW = 0: JABW = 1: T1/J1, 32/64/128 bits FIFO JABW = 0: JABW = 1:
Jitter Attenuator
6.8 0.9 5 1.25
Hz Hz Hz Hz
E1: (G.736) @ 3 Hz @ 40 Hz @ 400 Hz @ 100 kHz T1/J1: (Per AT&T pub.62411) @ 1 Hz @ 20 Hz @ 1 kHz @ 1.4 kHz @ 70 kHz Jitter Attenuator Latency Delay 32 bits FIFO: 64 bits FIFO: 128 bits FIFO: Input jitter tolerance before FIFO overflow or underflow 32 bits FIFO: 64 bits FIFO: 128 bits FIFO:
-0.5 -0.5 +19.5 +19.5 0 0 +33.3 40 40 16 32 64 28 58 120
dB
U.I. U.I. U.I. U.I. U.I. U.I.
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Figure-27 E1 Jitter Transfer Performance
Figure-28 T1/J1 Jitter Transfer Performance
72
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-70 JTAG Timing Characteristics
Symbol Parameter Min Typ Max Unit
t1 t2 t3 t4
TCK Period TMS to TCK setup Time TDI to TCK Setup Time TCK to TMS Hold Time TCK to TDI Hold Time TCK to TDO Delay Time
100 25 25 50
ns ns ns ns
t1 TCK
t2 TMS TDI
t3
t4
TDO
Figure-29 JTAG Interface Timing
73
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
8
8.1
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS
SERIAL INTERFACE TIMING
Table-71 Serial Interface Timing Characteristics
Symbol t1 t2 t3 t4 t5 t6 t7 t10 t11 Parameter Min Typ Max Unit Comments
SCLK High Time SCLK Low Time Active CS to SCLK Setup Time Last SCLK Hold Time to Inactive CS Time
CS Idle Time
100 100 5 41 41 0 82 95 90
ns ns ns ns ns ns ns ns ns
SDI to SCLK Setup Time SCLK to SDI Hold Time SCLK to SDO Valid Delay Time Inactive CS to SDO High Impedance Hold Time
CS t3 SCLK t6 SDI LSB t7 LSB t7 MSB t1 t2 t4 t5
Figure-30 Serial Interface Write Timing
1 SCLK CS SDO
2
3
4
5
6
7
8 t10
9
10
11
12
13
14
15 t4
16
0
1
2
3
4
5
6
t11 7
Figure-31 Serial Interface Read Timing with SCLKE=1
1 SCLK CS SDO
2
3
4
5
6
7
8
9 t10 0
10
11
12
13
14
15
16 t4 t11 7
1
2
3
4
5
6
Figure-32 Serial Interface Read Timing with SCLKE=0
74
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
8.2
PARALLEL INTERFACE TIMING
Table-72 Non-Multiplexed Motorola Read Timing Characteristics
Symbol tRC tDW tRWV tRWH tAV tADH tPRD tDAZ tRecovery Parameter Min Max Unit
Read Cycle Time Valid DS Width Delay from DS to Valid Read Signal
190 180 15 65 15 65 175 5 5 20
ns ns ns ns ns ns ns ns ns
R/W to DS Hold Time
Delay from DS to Valid Address Address to DS Hold Time
DS to Valid Read Data Propagation Delay
Delay from DS inactive to data bus High Impedance Recovery Time from Read Cycle
tRC tDW DS+CS tRWH tRWV R/W tADH tAV A[x:0] tPRD READ D[7:0] Valid Data Valid Address tDAZ tRecovery
Figure-33 Non-Multiplexed Motorola Read Timing
75
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-73 Non-Multiplexed Motorola Write Timing Characteristics
Symbol tWC tDW tRWV tRWH tAV tAH tDV tDHW tRecovery Parameter Min Max Unit
Write Cycle Time Valid DS Width Delay from DS to Valid Write Signal
120 100 15 65 15 65 15 65 5
ns ns ns ns ns ns ns ns ns
R/W to DS Hold Time
Delay from DS to Valid Address Address to DS Hold Time Delay from DS to Valid Write Data Write Data to DS Hold Time Recovery Time from Write Cycle
tWC tDW DS+CS tRWH tRWV R/W tAH Valid Address tDHW
tRecovery
tAV A[x:0]
tDV Write D[7:0]
Valid Data
Figure-34 Non-Multiplexed Motorola Write Timing
76
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-74 Non-Multiplexed Intel Read Timing Characteristics
Symbol tRC tRDW tAV tAH tPRD tDAZ tRecovery Parameter Min Max Unit
Read Cycle Time Valid RD Width Delay from RD to Valid Address Address to RD Hold Time
RD to Valid Read Data Propagation Delay
190 180 15 65 175 5 5 20
ns ns ns ns ns ns ns
Delay from RD inactive to data bus High Impedance Recovery Time from Read Cycle
tRC tRDW CS+RD tAH tAV A[x:0] tPRD READ D[7:0] Valid Data Valid Address
tRecovery
tDAZ
Note: WR should be tied to high
Figure-35 Non-Multiplexed Intel Read Timing
77
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-75 Non-Multiplexed Intel Write Timing Characteristics
Symbol tWC tWRW tAV tAH tDV tDHW tRecovery Parameter Min Max Unit
Write Cycle Time Valid WR Width Delay from WR to Valid Address Address to WR Hold Time Delay from WR to Valid Write Data Write Data to WR Hold Time Recovery Time from Write Cycle
120 100 15 65 15 65 5
ns ns ns ns ns ns ns
tWC tWRW WR+ CS tAH tAV A[x:0] Valid Address tDHW tDV Write D[7:0] Valid Data
tRecovery
Note: RD should be tied to high
Figure-36 Non-Multiplexed Intel Write Timing
78
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXXXX Device Type XX X Process/ Temperature Range
Blank
Industrial (-40 C to +85 C)
PF
Thin Quad Flatpack (TQFP, PN80)
82V2082
Long Haul/Short Haul LIU
DATASHEET DOCUMENT HISTORY
08/26/2003 pgs. 19, 20, 21,22, 33, 37, 45, 63, 64 04/09/2004 pgs. 14, 22, 24, 56 07/19/2004 pgs. 34, 66, 67
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