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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
FEATURES
* One 312.5MHz nominal LVDS output * Selectable crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal or LVCMOS single-ended input * Output frequency can be varied in 2% steps from nominal * VCO range: 560MHz - 690MHz * RMS phase jitter @ 312.5MHz, using a 25MHz crystal (1.875MHz-20MHz): 0.52ps (typical) * Output supply modes Core/Output 3.3V/3.3V 3.3V/2.5V * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS-complaint packages
GENERAL DESCRIPTION
The ICS844101I-312 is a low phase-noise frequency margining synthesizer and is a memHiPerClockSTM ber of the HiPerClockSTM family of high performance clock solutions from ICS. In the default mode, the device nominally generates a 312.5MHz LVDS output clock signal from a 25MHz crystal input. There is also a frequency margining mode available where the device can be programmed, using the serial interface, to vary the output frequency up or down from nominal in 2% steps. The ICS844101I-312 is provided in a 16pin TSSOP.
IC S
BLOCK DIAGRAM
OE CLK
Pullup Pulldown
PIN ASSIGNMENT
GND S_LOAD S_DATA Q S_CLOCK SEL nQ OE VDDA VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 MODE VDDO Q nQ GND CLK XTAL_OUT XTAL_IN
1
25MHz
/P OSC
0
XTAL_IN XTAL_OUT SEL
Phase Detector
VCO
560 - 690MHz
/N
Pulldown
/M
ICS844101I-312
16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View
S_CLOCK S_DATA S_LOAD MODE
Pulldown Pulldown Pulldown Pulldown
Serial Control
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844101AGI-312
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by an output divider prior to being sent to the LVPECL output buffer. The divider provides a 50% output duty cycle. The relationship between the crystal input frequency, the M divider, the VCO frequency and the output frequency is provided in Table 1. When changing back from frequency margining mode to nominal mode, the device will return to the default nominal configuration that will provide 312.5MHz output frequency. Serial operation occurs when S_LOAD is HIGH. Serial data can be loaded in either the default mode or the frequency margining mode. The 6-bit shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. After shifting in the 6-bit M divider value, S_LOAD is transitioned from HIGH to LOW which latches the contents of the shift-register into the M divider control register. When S_LOAD is LOW, any transitions of S_CLOCK or S_DATA are ignored.
VCO (MHz) 562.5 575 587.5 600 612.5 625 637.5 650 662.5 675 687.5 Output Divider (N) 2 2 2 2 2 2 2 2 2 2 2 Output Frequency (MHz) 281.25 287.5 293.75 300 306.25 312.5 318.75 325 331.25 337.5 343.75 % Change -10.0 -8.0 -6.0 -4.0 -2.0 0 2.0 4.0 6.0 8.0 10.0
FUNCTIONAL DESCRIPTION
The ICS844101I-312 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A 25MHz fundamental crystal is used as the input to the on chip oscillator. The output of the oscillator is fed into the pre-divider. In frequency margining mode, the 25MHz crystal frequency is divided by 2 and a 12.5MHz reference frequency is applied to the phase detector. The VCO of the PLL operates over a range of 560MHz to 690MHz. The output of the M divider is also applied to the phase detector. The default mode for the ICS844101I-312 is 312.5MHz output frequency using a 25MHz crystal. The output frequency can be changed by placing the device into the margining mode using the mode pin and using the serial interface to program the M feedback divider. Frequency margining mode operation occurs when the MODE input is HIGH. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for
TABLE 1. FREQUENCY MARGIN FUNCTION TABLE
XTAL (MHz) 25 25 25 25 25 25 25 25 25 25 25 Pre-Divider (P) 2 2 2 2 2 2 2 2 2 2 2 Reference Frequency (MHz) 12.5 12.5 12.5 12.5 12.5 12.5 12.5 12.5 12.5 12.5 12.5 Feedback Divider (M) 45 46 47 48 49 50 51 52 53 54 55 M-Data (Binary) 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111
SERIAL LOADING
S_CLOCK S_DATA
t
M5 M4
S
M3
M2
M1
M0
t
S
t
H
S_LOAD
Time
FIGURE 1. SERIAL LOAD OPERATIONS
844101AGI-312
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
Power supply ground. Pulldown Controls the operation of the Serial input. LVCMOS/LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. Pulldown LVCMOS/LVTTL interface levels. Clock in serial data present at S_DATA input into the shift register on the Pulldown rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Select pin. When HIGH, selects CLK input. Pulldown When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. Output enable pin. Controls enabling and disabling of Q/nQ outputs. Pullup LVCMOS/LVTTL interface levels Analog supply pin. Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Pulldown LVCMOS/LVTTL clock input. Differential output pair. LVPECL interface levels.
TABLE 2. PIN DESCRIPTIONS
1, 12 2 3 4 5 6 7 8 9, 10 11 13, 14 15 GND S_LOAD S_DATA S_CLOCK SEL OE VDDA VDD XTAL_IN, XTAL_OUT CL K nQ, Q VDDO Input Input Input Input Input Power Power Input Input Ouput Power Power
Output supply pin. MODE pin. LOW = default mode. HIGH = frequency margining mode. 16 MODE Input Pulldown LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP Parameter Input Capacitance Input Pulldown Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
844101AGI-312
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 4A. OE CONTROL INPUT FUNCTION TABLE
Input OE 0 1 Outputs Q , nQ HiZ Enabled
TABLE 4B. SEL CONTROL INPUT FUNCTION TABLE
Input SEL 0 1 Selected Source XTAL_IN, XTAL_OUT CLK
TABLE 4C. MODE CONTROL INPUT FUNCTION TABLE
Input Mode 0 1 Condition Q, nQ Default Mode Frequency Margining Mode
TABLE 4D. SERIAL MODE FUNCTION TABLE
Inputs S_LOAD L H S_CLOCK X S_DATA X Data Serial inputs are ignored. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are latched. Conditions
L X NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition
844101AGI-312
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
4.6V -0.5V to VDD + 0.5V 10mA 15mA -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG
Package Thermal Impedance, JA 89C/W (0 lfpm)
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 85 7 19 Maximum 3.465 3.465 3.465 Units V V V mA mA mA
TABLE 5B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%,VDDO = 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 2.375 Typical 3.3 3.3 2.5 85 7 18 Maximum 3.465 3.465 2.625 Units V V V mA mA mA
844101AGI-312
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
Test Conditions VDD = 3.3V VDD = 3.3V Minimum Typical 2 -0.3 Maximum VCC + 0.3 0.8 150 5 -5 -150 20 Units V V A A A A ns/v
TABLE 5C. LVCMOS / LVTTL DC CHARACTERISTICS, TA = -40C TO 85C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current CLK, SEL, S_LOAD, S_CLOCK, S_DATA, MODE OE CLK, SEL, S_LOAD, S_CLOCK, S_DATA, MODE OE t/v Input Transistion Rise/Fall Rate OE, SEL, S_CLOCK, S_DATA, S_LOAD, MODE
VDD = VIN = 3.465 VDD = VIN = 3.465 VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V
IIL
Input Low Current
TABLE 5D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 375 40 1.42 50 Maximum Units mV mV V mV
TABLE 5E. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 365 40 1.37 50 Maximum Units mV mV V mV
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal. Test Conditions Minimum Typical Maximum 25 50 7 100 Units MHz pF W Fundamental
844101AGI-312
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
Test Conditions Minimum Typical 25 25 50 Maximum Units MHz MHz MHz
TABLE 7. INPUT FREQUENCY CHARACTERISTICS, TA = -40C TO 85C
Symbol Parameter CLK fIN Input Frequency XTAL_IN/XTAL_OUT S_CLOCK
TABLE 8A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol fOUT t jit(O) tR / tF odc Parameter Output Frequency RMS Phase Jitter ; NOTE 1 Output Rise/Fall Time Mode = LOW 312.5MHz, (1.875MHz - 20MHz) 20% to 80% Test Conditions Minimum Typical 312.5 0.52 360 50 10 10 10 Maximum Units MHz ps ps % ns ns ns
Output Duty Cycle S_DATA to S_CLOCK tS Setup Time S_CLOCK to S_LOAD S_DATA to Hold Time tH S_CLOCK NOTE 1: Characterized using a 25MHz cr ystal.
TABLE 8B. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%,VDDO = 2.5V5%, TA = -40C TO 85C
Symbol fOUT t jit(O) tR / tF odc Parameter Output Frequency RMS Phase Jitter ; NOTE 1 Output Rise/Fall Time Mode = LOW 312.5MHz, (1.875MHz - 20MHz) 20% to 80% Test Conditions Minimum Typical 312.5 0.50 375 50 10 10 10 Maximum Units MHz ps ps % ns ns ns
Output Duty Cycle S_DATA to S_CLOCK tS Setup Time S_CLOCK to S_LOAD S_DATA to Hold Time tH S_CLOCK NOTE 1: Characterized using a 25MHz cr ystal.
844101AGI-312
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
3.3V 2.5V
3.3V
Qx
SCOPE
++ -
SCOPE
Qx
Power Supply +
Float GND
LVDS
-
LVDS
nQx
nQx
POWER SUPPLY Float GND
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQ
Noise Power
Q
Phase Noise Mask
t PW
t
PERIOD
odc =
f1 Offset Frequency f2
t PW t PERIOD
x 100%
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
80% Clock Outputs
80% VSW I N G tF
out
tR
out
VOS/ VOS
OUTPUT RISE/FALL TIME
VDD out
OFFSET VOLTAGE SETUP
DC Input
LVDS
100
VOD/ VOD out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
844101AGI-312
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REV. A NOVEMBER 28, 2005
20%
20%
DC Input
LVDS
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844101I-312 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA. The 10 resistor can also be replaced by a ferrite bead.
3.3V VDD .01F VDDA .01F 10F 10
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844101I-312 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 3 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 27p X1 18pF Parallel Crystal XTAL_IN C2 27p
Figure 3. CRYSTAL INPUt INTERFACE
844101AGI-312
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS:
CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
2.5V or 3.3V VDD LVDS_Driv er + R1 100
-
100 Ohm Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
844101AGI-312
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER RELIABILITY INFORMATION
TABLE 9.
JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0 200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
137.1C/W 89.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS844101I-312 is: 4093
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 10. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
844101AGI-312
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 11. ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature ICS844101AGI-312 TBD 16 Lead TSSOP tube -40C to 85C ICS844101AGI-312T TBD 16 Lead TSSOP 2500 tape & reel -40C to 85C ICS844101AGI-312LF TBD 16 Lead "Lead-Free" TSSOP tube -40C to 85C ICS844101AGI-312LFT TBD 16 Lead "Lead-Free" TSSOP 2500 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS complaint.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 844101AGI-312
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REV. A NOVEMBER 28, 2005

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