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| HUF75831SK8 Data Sheet December 2001 3A, 150V, 0.095 Ohm, N-Channel, UltraFET(R) Power MOSFET Packaging JEDEC MS-012AA BRANDING DASH Features * Ultra Low On-Resistance - rDS(ON) = 0.095, VGS = 10V 5 1 2 3 4 * Simulation Models - Temperature Compensated PSPICE(R) and SABERTM Electrical Models - Spice and SABER Thermal Impedance Models - www.fairchildsemi.com * Peak Current vs Pulse Width Curve Symbol SOURCE (1) SOURCE (2) SOURCE (3) GATE (4) DRAIN (8) DRAIN (7) DRAIN (6) DRAIN (5) * UIS Rating Curve Ordering Information PART NUMBER HUF75831SK8 PACKAGE MS-012AA BRAND 75831SK8 NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUF75831SK8T. Absolute Maximum Ratings TA = 25oC, Unless Otherwise Specified HUF75831SK8 UNITS V V V A A 150 150 20 3 2 Figure 4 Figures 6, 14, 15 2.5 20 -55 to 150 300 260 W mW/oC oC oC oC Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TA= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA= 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Tech Brief TB370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg NOTES: 1. TJ = 25oC to 125oC. 2. 50oC/W measured using FR-4 board with 0.76 in 2 (490.3 mm2) copper pad at 10 second. 3. 152oC/W measured using FR-4 board with 0.054 in 2 (34.8 mm2) copper pad at 1000 seconds 4. 189oC/W measured using FR-4 board with 0.0115 in 2 (7.42 mm2) copper pad at 1000 seconds CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html For severe environments, see our Automotive HUFA series. All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification. (c)2001 Fairchild Semiconductor Corporation HUF75831SK8 Rev. B HUF75831SK8 Electrical Specifications PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current BVDSS IDSS ID = 250A, VGS = 0V (Figure 11) VDS = 140V, VGS = 0V VDS = 135V, VGS = 0V, TA = 150oC Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance THERMAL SPECIFICATIONS Thermal Resistance Junction to Ambient RJA Pad Area = 0.76 in2 (490.3 mm2) (Note 2) Pad Area = 0.054 in2 (34.8 mm2) (Note 3) Pad Area = 0.0115 in2 (7.42 mm2)(Note 4) SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) 1175 275 72 pF pF pF Qg(TOT) Qg(10) Qg(TH) Qgs Qgd VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 75V, ID = 3A, Ig(REF) = 1.0mA (Figures 13, 16, 17) 66 35 2.4 4.3 11 80 42 2.9 nC nC nC nC nC tON td(ON) tr td(OFF) tf tOFF VDD = 75V, ID = 3A VGS = 10V, RGS = 4.7 (Figures 18, 19) 11 6 40 9 25 75 ns ns ns ns ns ns 50 152 189 oC/W oC/W oC/W TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 150 - - 1 250 100 V A A nA IGSS VGS = 20V VGS(TH) rDS(ON) VGS = VDS, ID = 250A (Figure 10) ID = 3A, VGS = 10V (Figure 9) 2 - 0.079 4 0.095 V Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage SYMBOL VSD ISD = 3A ISD = 1.5A Reverse Recovery Time Reverse Recovered Charge trr QRR ISD = 3A, dISD/dt = 100A/s ISD = 3A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 1.00 132 380 UNITS V V ns nC (c)2001 Fairchild Semiconductor Corporation HUF75831SK8 Rev. B HUF75831SK8 Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 3 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (oC) 150 4 VGS = 10V, RJA = 50oC/W 2 1 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 3 1 THERMAL IMPEDANCE ZJA, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-2 10-1 100 101 102 103 RJA = 50oC/W 0.1 0.01 SINGLE PULSE 0.001 10-5 10-4 10-3 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 500 RJA = 50oC/W IDM, PEAK CURRENT (A) 100 TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 VGS = 10V 10 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 1 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 102 103 150 - TA 125 FIGURE 4. PEAK CURRENT CAPABILITY (c)2001 Fairchild Semiconductor Corporation HUF75831SK8 Rev. B HUF75831SK8 Typical Performance Curves 100 RJA = 50oC/W ID, DRAIN CURRENT (A) (Continued) 100 IAS , AVALANCHE CURRENT (A) If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 10 100s 10 STARTING TJ = 25oC STARTING TJ = 150oC 1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) SINGLE PULSE TJ = MAX RATED TA = 25oC 1 10 100 1ms 10ms 0.1 1 0.01 500 0.1 1 10 100 tAV, TIME IN AVALANCHE (ms) VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 5. FORWARD BIAS SAFE OPERATING AREA 20 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 15 20 VGS = 20V VGS = 10V ID, DRAIN CURRENT (A) 15 VGS = 7V VGS = 6V VGS =5V ID, DRAIN CURRENT (A) 10 TJ = 150oC 5 10 TJ = -55oC 5 TJ = 25oC 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0 0.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC 1.0 1.5 2.0 VGS , GATE TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS 2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0 NORMALIZED GATE THRESHOLD VOLTAGE 1.2 VGS = VDS, ID = 250A 1.1 1.0 1.5 0.9 1.0 VGS = 10V, ID = 3A 0.5 -80 0.8 -40 0 40 80 120 160 0.7 -80 -40 0 40 80 120 160 T J, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE (c)2001 Fairchild Semiconductor Corporation HUF75831SK8 Rev. B HUF75831SK8 Typical Performance Curves 1.15 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A C, CAPACITANCE (pF) 1.10 1000 (Continued) 3000 VGS = 0V, f = 1MHz CISS = CGS + CGD 1.05 COSS CDS + CGD 100 1.00 0.95 CRSS = CGD 10 0.1 0.90 -80 -40 0 40 80 120 160 1.0 10 150 TJ , JUNCTION TEMPERATURE (oC) VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 75V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 3A ID = 0.5A 0 10 20 30 Qg , GATE CHARGE (nC) 40 2 0 NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + - 0V IAS 0.01 0 tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS (c)2001 Fairchild Semiconductor Corporation HUF75831SK8 Rev. B HUF75831SK8 Test Circuits and Waveforms (Continued) VDS RL VDD VDS VGS = 20V VGS + Qg(TOT) Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 10V DUT Ig(REF) FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS VDS tON td(ON) RL VDS + tOFF td(OFF) tr tf 90% 90% VGS DUT RGS VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM Thermal Resistance vs Mounting Pad Area The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the par t. ( T JM - TA ) P = -----------------------------DM Z JA dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 20 defines the RJA for the device as a function of the top HUF75831SK8 Rev. B (EQ. 1) In using surface mount devices such as the SOP-8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power (c)2001 Fairchild Semiconductor Corporation HUF75831SK8 copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Displayed on the curve are RJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM . Thermal resistances corresponding to other copper areas can be obtained from Figure 20 or by calculation using Equation 2. RJA is defined as the natural log of the area times a coefficient added to a constant. The area, in square inches is the top copper area including the gate and source pads. R JA = 83.2 - 23.6 x graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1. 240 RJA = 83.2 - 23.6*ln(AREA) 200 RJA (oC/W) 189oC/W - 0.0115in2 160 152oC/W - 0.054in2 ln ( Area ) 120 (EQ. 2) 80 0.01 The transient thermal impedance (ZJA) is also effected by varied top copper board area. Figure 21 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the 0.1 AREA, TOP COPPER AREA (in2) 1.0 FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA 150 COPPER BOARD AREA - DESCENDING ORDER 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.00 in2 120 ZJA, THERMAL IMPEDANCE (oC/W) 90 60 30 0 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103 FIGURE 21. THERMAL IMPEDANCE vs MOUNTING PAD AREA (c)2001 Fairchild Semiconductor Corporation HUF75831SK8 Rev. B HUF75831SK8 PSPICE Electrical Model .SUBCKT HUF75831SK8 2 1 3 ; CA 12 8 2.00e-9 CB 15 14 2.00e-9 CIN 6 8 1.10e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD 10 rev 4 Feb 2000 LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + EBREAK MWEAK MMED MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 14 IT 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 17 18 DBODY DRAIN 2 RSLC1 51 ESLC 50 RSLC2 5 51 ESG 6 8 + LGATE GATE 1 RLGATE EVTEMP RGATE + 18 22 9 20 EVTHRES + 19 8 6 IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 1.12e-9 LSOURCE 3 7 1.29e-10 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 5.80e-2 RGATE 9 20 1.95 RLDRAIN 2 5 10 RLGATE 1 9 11.2 RLSOURCE 3 7 1.29 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 2.20e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD - - VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*40),2))} .MODEL DBODYMOD D (IS = 9.95e-13 RS = 6.61e-3 TRS1 = 1.02e-4 TRS2 = 0 CJO = 1.53e-9 TT = 2.12e-7 M = 0.62) .MODEL DBREAKMOD D (RS = 9.00e- 1TRS1 = 9.94e- 4TRS2 = 1.06e-7) .MODEL DPLCAPMOD D (CJO = 1.35e- 9IS = 1e-3 0M = 0.90) .MODEL MMEDMOD NMOS (VTO = 3.18 KP = 1.70 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.95) .MODEL MSTROMOD NMOS (VTO = 3.56 KP = 30 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.85 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 19.5 Rs = 0.10) .MODEL RBREAKMOD RES (TC1 = 9.97e- 4TC2 = 5.07e-7) .MODEL RDRAINMOD RES (TC1 = 8.52e-3 TC2 = 2.44e-5) .MODEL RSLCMOD RES (TC1 = 3.28e-3 TC2 = 0) .MODEL RSOURCEMOD RES (TC1 = 1.00e-3 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -2.08e-3 TC2 = -8.86e-6) .MODEL RVTEMPMOD RES (TC1 = -3.08e- 3TC2 = 0) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -6.0 VOFF= -4.0) VON = -4.0 VOFF= -6.0) VON = -3.0 VOFF= 0.0) VON = 0.0 VOFF= -3.0) NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2001 Fairchild Semiconductor Corporation + - EBREAK 11 7 17 18 155.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 RDRAIN 21 16 - VBAT + 8 22 RVTHRES HUF75831SK8 Rev. B HUF75831SK8 SABER Electrical Model REV 4 feb 2000 template huf75831sk8 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (is = 9.95e-13, rs=6.61e-3, trs1=1.02e-4, trs2=0, cjo = 1.53e-9, tt = 2.12e-7, m = 0.62) dp..model dbreakmod = (rs=9.00e-1, trs1=9.94e-4, trs2=1.06e-7) dp..model dplcapmod = (cjo = 1.35e-9, is = 1e-30, m = 0.90) m..model mmedmod = (type=_n, vto = 3.18, kp = 1.70, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.56, kp = 30, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.85, kp = 0.08, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.0, voff = -4.0) DPLCAP 5 sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -.4.0, voff = -6.0) 10 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -3.0, voff = 0.0) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.0, voff = -3.0) RSLC1 c.ca n12 n8 = 2.00e-9 c.cb n15 n14 = 2.00e-9 c.cin n6 n8 = 1.10e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1.00e-9 l.lgate n1 n9 = 1.12e-9 l.lsource n3 n7 = 1.29e-10 GATE 1 RLGATE CIN LGATE 51 RSLC2 ISCL LDRAIN DRAIN 2 RLDRAIN ESG + EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8 50 RDRAIN 21 16 DBREAK 11 MWEAK MMED EBREAK + 17 18 DBODY MSTRO 8 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 9.97e-4, tc2 = 5.07e-7 res.rdrain n50 n16 = 5.80e-2, tc1 = 8.52e-3, tc2 = 2.44e-5 res.rgate n9 n20 = 1.95 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 11.2 res.rlsource n3 n7 = 1.29 res.rslc1 n5 n51 = 1e-6, tc1 = 3.28e-3, tc2 = 0 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2.20e-3, tc1 = 1.00e-3, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -3.08e-3, tc2 = 0 res.rvthres n22 n8 = 1, tc1 = -2.08e-3, tc2 = -8.86e-6 spe.ebreak n11 n7 n17 n18 = 155.4 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/40))** 2)) } } S1A 12 13 8 S1B CA 13 + EGS 6 8 S2A 14 13 S2B - LSOURCE 7 RLSOURCE SOURCE 3 RSOURCE RBREAK 17 18 RVTEMP CB + EDS 5 8 19 14 IT 15 VBAT + - - 8 RVTHRES 22 (c)2001 Fairchild Semiconductor Corporation HUF75831SK8 Rev. B HUF75831SK8 SPICE Thermal Model REV 02 Feb 2000 HUF75831SK8 Copper Area = 0.04 in2 CTHERM1 th 8 2.0e-3 CTHERM2 8 7 5.0e-3 CTHERM3 7 6 1.0e-2 CTHERM4 6 5 4.0e-2 CTHERM5 5 4 9.0e-2 CTHERM6 4 3 1.2e-1 CTHERM7 3 2 0.5 CTHERM8 2 tl 1.3 RTHERM1 th 8 0.1 RTHERM2 8 7 0.5 RTHERM3 7 6 1.0 RTHERM4 6 5 5.0 RTHERM5 5 4 8.0 RTHERM6 4 3 26 RTHERM7 3 2 39 RTHERM8 2 tl 55 C th JUNCTION RTHERM1 8 CTHERM1 RTHERM2 7 CTHERM2 RTHERM3 6 CTHERM3 RTHERM4 5 CTHERM4 SABER Thermal Model Copper Area = 0.04 in2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 = 2.0e-3 ctherm.ctherm2 8 7 = 5.0e-3 ctherm.ctherm3 7 6 = 1.0e-2 ctherm.ctherm4 6 5 = 4.0e-2 ctherm.ctherm5 5 4 = 9.0e-2 ctherm.ctherm6 4 3 = 1.2e-1 ctherm.ctherm7 3 2 = 0.5 ctherm.ctherm8 2 tl = 1.3 rtherm.rtherm1 th 8 = 0.1 rtherm.rtherm2 8 7 = 0.5 rtherm.rtherm3 7 6 = 1.0 rtherm.rtherm4 6 5 = 5.0 rtherm.rtherm5 5 4 = 8.0 rtherm.rtherm6 4 3 = 26 rtherm.rtherm7 3 2 = 39 rtherm.rtherm8 2 tl = 55 RTHERM5 CTHERM5 4 RTHERM6 3 CTHERM6 RTHERM7 2 CTHERM7 RTHERM8 CTHERM8 tl CASE TABLE 1. THERMAL MODELS COMPONENT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8 1.2e-1 0.5 1.3 26 39 55 0.04 in2 1.5e-1 1.0 2.8 20 24 38.7 0.28 in2 2.0e-1 1.0 3.0 15 21 31.3 0.52 in2 2.0e-1 1.0 3.0 13 19 29.7 0.76 in2 2.0e-1 1.0 3.0 12 18 25 1.0 in2 (c)2001 Fairchild Semiconductor Corporation HUF75831SK8 Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM DISCLAIMER FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R) SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R) VCXTM STAR*POWER is used under license FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4 |
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