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GDC21D401B
(Video Decoder)
Version 1.0
Mar, 99
HDS-GDC21D401B-9908 / 10
GDC21D401B
The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by Hyundai for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Hyundai or others. These Hyundai products are intended for usage in general electronic equipment (office equipment, communication equipment, measuring equipment, domestic electrification, etc.). Please make sure that you consult with us before you use these Hyundai products in equipment which require high quality and / or reliability, and in equipment which could have major impact to the welfare of human life (atomic energy control, airplane, spaceship, traffic signal, combustion control, all types of safety devices, etc.). Hyundai cannot accept liability to any damage which may occur in case these Hyundai products were used in the mentioned equipment without prior consultation with Hyundai. Copyright 1999 Hyundai Micro Electronics Co.,Ltd. All Rights Reserved
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GDC21D401B
TABLE OF CONTENTS
1. General Description ............................................................................................................5 2. Features...............................................................................................................................5 3. Pin Description....................................................................................................................6 4. Block Diagram ...................................................................................................................10 5. Functional Description .....................................................................................................11 5.1 Initialization and Decoding Start ...................................................................................11 5.2 Picture Decoding ..........................................................................................................11 5.3 STC (System Time Clock) Generation..........................................................................12 5.4 DTS (Decoding Time Stamp) Synchronization..............................................................12 5.5 Error Concealment .......................................................................................................12 5.6 User Data Read............................................................................................................12 5.7 Bitstream Buffer Over/Underflow..................................................................................13 5.8 VLD (Variable Length Decoder) ....................................................................................13 5.9 Inverse Quantization ....................................................................................................13 5.10 IDCT (Inverse Discrete Cosine Transform) .................................................................13 5.11 MC(Motion Compensation) .........................................................................................13 5.12 Transport Interface .....................................................................................................14 5.13 Host Interface.............................................................................................................15 5.14 Video Data Output Format..........................................................................................20 5.15 Video Data Output Timing ..........................................................................................21 5.16 SDRAM Interface .......................................................................................................22 6. Electrical Specification .....................................................................................................24 6.1 Absolute Maximum Rating............................................................................................24 6.2 Recommended Operating Range .................................................................................24 6.3 DC Characteristics (VDD = 3.3 V10%, TA = 0 ~ 70 E................................................24 ) 6.4 AC Characteristics (VDD = 3.3 V10%, TA = 0 ~ 70 E ................................................25 ) 7. Package Mechanical Data .................................................................................................26 7.1 Package Pin Out ..........................................................................................................26 7.2 Physical Dimension ......................................................................................................29
4
GDC21D401B
Video Decoder
GDC21D401B
1. General Description
The Video Decoder(VD) decodes video elementary stream of MPEG-2(ISO/ICE 13818-2)MP@HL. It supports the ATSC digital TV video standard, and can be used for the video part of the ATSC digital TV with the Transport Decoder and the VDP(Video Display Processor). Picture decoding timing can be controlled internally for A/V lip synchronization, and externally for Video Trick Mode by host microprocessor via I2C bus. The Video Decoder can extract video user data including caption from video elementary stream, and host microprocessor can read the video user data from the Video Decoder(VD) via I2C. It uses four 16x1M SDRAMs and can support up to 81 MHz memory clock speed.
2. Features
* Supports MPEG-2 (ISO/ICE 13818-2) MP@HL * Supports all video input formats of ATSC digital TV standard * Supports picture decoding capability up to 1920x1088 30 Frame/Sec * Supports all kinds of motion compensation methods of MPEG-2 * Supports MPEG-2 error code, syntax error detection, and slice-based error concealment * Supports DTS synchronization * Supports VBV delay mode and low delay mode decoding * Supports film mode decoding (3:2 Pull down) * Supports high level commands for trick mode * Supports 8(w)x64(d) internal user data FIFO * Outputs: macroblock format 4-pel parallel output 54 MHz synchronous I/F Data window (pdwin, sclk, and mbclk) Picture information (Picture structure, Field parity, and DCT type) * External memory for VBV buffer , DTS FIFO and 2-frame memory: 64-bit Data Bus 81 MHz Synchronous Interface 64-Mbyte Four 16x1M SDRAMs * Host processor interface: I2C bus interface Two interrupt signals Supports 23 programmable internal registers
5
GDC21D401B
3. Pin Description
P_SHARE_IN[10] P_SHARE_IN[9] P_SHARE_IN[8] MCLK_OUT TEST_ OUT[2] FP_FD MCLK_IN DEC_ERROR VSS P_WAIT PIC_DIS_SYNC VDD VDD PDATA[31] PDATA[30] PDATA[29] PDATA[28] VSS VSS PDATA[27] PDATA[26] PDATA[25] PDATA[24] VDD PDATA[23] PDATA[22] PDATA[21] PDATA[20] VSS PDATA[19] PDATA[18] VDD PDATA[17] PDATA[16] PDATA[15] VDD PDATA[14] PDATA[13] PDATA[12] VSS PDATA[11] VSS PDATA[10] VDD PDATA[9] PDATA[8] VDD PDATA[7] PDATA[6] PDATA[5] PDATA[4] VSS VSS PDATA[3] VDD VDD PDATA[2] PDATA[1] PDATA[0] VSS
235
230
225
220
215
210
205
200
195
190
VSS SCANTESTON VDD IDCTTESTON MEMTESTON CLK_27M VSS \RESET TSW \VIDEN VSTCW VSS VID_STRB VID_DATA[0] VID_DATA[1] VID_DATA[2] VDD VID_DATA[3] VSS VID_DATA[4] VID_DATA[5] VDD VID_DATA[6] VSS VID_DATA[7] SCL VSS SDA \VID_REQ \UBUFF_FULL \INT_V VDD SDRAM_DATA[0] SDRAM_DATA[1] VSS SDRAM_DATA[2] VDD SDRAM_DATA[3] SDRAM_DATA[4] SDRAM_DATA[5] VDD SDRAM_DATA[6] SDRAM_DATA[7] VDD SDRAM_DATA[8] VSS SDRAM_DATA[9] SDRAM_DATA[10] VDD SDRAM_DATA[11] SDRAM_DATA[12] VSS SDRAM_DATA[13] SDRAM_DATA[14] VDD SDRAM_DATA[15] SDRAM_DATA[16] VSS SDRAM_DATA[17] SDRAM_DATA[18]
185
1 240
5
180
175
10 170
15 165
20 160
25
HME
GDC21D401B YYW W A
155
30
150
35
145
40 140
45 135
50 130
55 125
60
VSS PSTR[1] PSTR[0] PDWIN VSS D_INFO_WIN DIS_INFO VDD VDD \FFPN VSS MBFI MBCLK VDD SCLK VDCLK VSS SDRAM_DATA[63] SDRAM_DATA[62] SDRAM_DATA[61] VDD VDD SDRAM_DATA[60] SDRAM_DATA[59] VSS VSS SDRAM_DATA[58] VDD SDRAM_DATA[57] VSS SDRAM_DATA[56] VDD SDRAM_DATA[55] SDRAM_DATA[54] VSS SDRAM_DATA[53] SDRAM_DATA[52] VDD SDRAM_DATA[51] SDRAM_DATA[50] VSS SDRAM_DATA[49] SDRAM_DATA[48] VDD SDRAM_DATA[47] VDD SDRAM_DATA[46] SDRAM_DATA[45] VSS VSS SDRAM_DATA[44] VDD SDRAM_DATA[43] VDD SDRAM_DATA[42] SDRAM_DATA[41] VSS SDRAM_DATA[40] VSS SDRAM_DATA[39]
120
100
105
110
115
65
70
75
80
Figure 1. Pin Description
85
90
95
SDRAM_DATA[38] VDD SDRAM_DATA[37] SDRAM_DATA[36] SDRAM_DATA[35] VSS SDRAM_DATA[34] SDRAM_DATA[33] SDRAM_DATA[32] VDD VDD CSN RASN CASN WEN VSS BA0 SDRAM_ADDR[10] SDRAM_ADDR[9] SDRAM_ADDR[8] VDD SDRAM_ADDR[7] SDRAM_ADDR[0] VSS VSS VSS MCLK VDD SDRAM_ADDR[6] SDRAM_ADDR[1] VDD SDRAM_ADDR[5] VDD SDRAM_ADDR[2] SDRAM_ADDR[4] VSS SDRAM_ADDR[3] VSS SDRAM_DATA[31] SDRAM_DATA[30] VDD SDRAM_DATA[29] SDRAM_DATA[28] VSS SDRAM_DATA[27] SDRAM_DATA[26] VDD SDRAM_DATA[25] SDRAM_DATA[24] VDD SDRAM_DATA[23] VSS SDRAM_DATA[22] VDD SDRAM_DATA[21] VSS SDRAM_DATA[20] VDD SDRAM_DATA[19] VSS
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GDC21D401B
(Package: 240 HQFP)
NAME VDCLK MCLK MCLK_IN MCLK_OUT CLK_27M \RESET PIN 165 94 234 237 6 8 TYPE DESCRIPTION CLOCK I Operating clock. - 54 MHz (max), 50 % duty cycle I SDRAM interface clock. - 81 MHz (max), 50 % duty cycle SDRAM interface clock. - 81 MHz (max), I 50 % duty cycle (the same clock as MCLK) SDRAM interface clock through clock buffer for delay effect. O This signal input is MCLK_IN. I External system time clock. - 27 MHz RESET I Power on reset(active low). At least 3 VDCLKs. Decoding starts after 128 VDCLKs from the last reset low state. I2C-BUS INTERFACE I I2C-bus serial clock. - 400 KHz(max) I/O I2C-bus serial data TRANSPORT INTERFACE I Transport Decoder data bus O I I Transport data request(active low) Transport data strobe. VID_DATA[7:0] is latched on the rising edge. PTS & DTS data enable(active high). In LG DTV chipset, this signal is connected to the PTS_DTS_STRB pin of GDC21D301A. Video bitstream data enable(active low) STC data enable(active high) HOST INTERRUPT Video decoder interrupt(active low) User data FIFO is full(active low). When it happens, host microprocessor must read the user data from user data FIFO. Otherwise video decoder suspends decoding. SDRAM INTERFACE SDRAM chip selection(active low) SDRAM write enable(active low) SDRAM row address selection(active low) SDRAM column address selection(active low) SDRAM bank address. This indicates bank address, and low value selects bank `0'. SDRAM address SDRAM data bus
SCL SDA VID_DATA[7:0] \VID_REQ VID_STRB TSW
26 28 25,23,21,20, 18,16,15,14 29 13 9
\VIDEN VSTCW \INT_V \UBUFF_FULL
10 11 31 30
I I O O
CSN WEN RASN CASN BA0 SDRAM_ADDR [10:0] SDRAM_DATA [63:0]
109 106 108 107 104
103,102,101, 99,92,89,86, 84,87,91,98 163,162,161, 158,157,154, 152,150,43, 42,40,39,38, 36, 34, 33
O O O O O O I/O
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GDC21D401B
Pin Description (continued)
NAME DIS_INFO D_INFO_WIN PIC_DIS_SYNC P_WAIT PIN TYPE DESCRIPTION VDP INTERFACE - SYNC & PICTURE FORMAT 174 O Serialized picture format data 175 O Serialized picture format data enable(active high) 230 I Picture display sync. - 30 Hz or 29.97 Hz, 50% duty VDP INTERFACE - PICTURE DATA 231 I PDATA wait(active high). This signal makes PDATA output to be suspended after 50 VDCLKs from the last high value. This signal is the output of the VDP. 177 O Picture data window(active high). During 1 picture data decoding, this signal is high. 179,178 O Picture structure. This indicates the structure of output picture. If this is equal to `1', the output picture is top field picture. If this is equal to `2', the output picture is bottom field picture. If this is equal to `3', the output picture is frame picture. 171 O First field parity(active low). This signal is the first_field_parity flag of output picture. When output picture is interlaced frame picture, the field of output frame is the first output by the VDP. 166 O Slice decoding window(active high). This signal has high value when a macroblock with the same vertical position is decoded. There are at least 2-clock low value periods between each slice decoding window. 168 O Macroblock decoding window(active high). This signal has high value when a macroblock data is decoded. The width of high value is always 96 VDCLKs. There are at least 2-clock low value periods between each macroblock decoding window. 233 O Decoding Error (active high) This is a multiplexed output signal. It is used to inform VDP R1.2 (GDC21D701B) of an error in Picture or Macro Block. 235 O Frame_Pred_Frame_Dct (active high) This signal is explained in ISO/IEC 13818-2 (Information technology - Generic coding of moving pictures and associated audio information : Video) If this flag is set to `1', only frame_DCT and frame prediction are used. In a field picture, it should be `0'. If progressive_frame is `1', Frame_pred_frame_dct should be set to `1'. This flag affects the syntax of the bitstream.
PDWIN PSTR[1:0]
\FFPN
SCLK
MBCLK
DEC_ERROR
FP_FD
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GDC21D401B
Pin Description (continued)
NAME MBFI PIN 169 TYPE O DESCRIPTION Macroblock Field IDCT. This signal has the meaning when a decoded picture is a frame picture. If this is set to `0', the output of a decoded macroblock has the form of frame IDCT. If this is set to `1', the output of a decoded macroblock has the form of field IDCT. Picture data. This is a bundle of four adjacent pixel data. A decoded macroblock consists of 96 consequent PDATA. The order of PDATA in a decoded macroblock depends on the MBFI signal.
PDATA[31:0]
227,226,225, 224,221,220, 191,190,187, 184,183,182
O
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GDC21D401B
4. Block Diagram
27 MHz System Clock STC Display Sync I 2C I/F DTS check Decoding Controller IDCT Coefficient Decoder IDCT coefficients
Quantization Matrix IQ IQ & & Buffer Buffer
Max.200 M sample/sec High-Speed IDCT 32 IDCT IDCT Display Processor Control
Decoded MB Data
32
Data Window
Predictor Macroblock Parameter Decoder MB parameters MB Decoding Controller
Video Bitstream
Video Bitstream Predecoder
FIFO
Sequence Parcer
FIFO
FIFO
Motion Vector Decoder
MB Motion Vector
MV Processor
Half- pel Predictor
FIFO
SDRAM Controller 64 Internal Data Bus Address
Figure 2. MPEG-2 MP@HL Video Decoder Block Diagram
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Data
GDC21D401B
5. Functional Description 5.1 Initialization and Decoding Start
Power on reset: \RESET = `0' during several ) clocks. In this state, bitstream buffers are flushed, all decoding controllers are reset, and all internal registers have default values. Decoding start: \RESET = `1'. In this state, ) the bitstream buffers begin to be filled with input video bitstreams. First, the bitstream is discarded until the 1st sequence header code appears, and then the sequence headers are decoded. Next, the picture data bitstream is decoded, and it continues to be decoded unless the buffers are underflow.
5.2 Picture Decoding
Picture decoding control state diagram is shown in Fig 3. Each picture decoding is synchronized with the external `pic_dis_sync` signal. If `pic_dis_sync` signal is changed, command is executed, then some decoding conditions are checked (sync parity: top or bottom, underflow, DTS check and skip check). If the condition is "repeat", decoding is suspended until this condition is ended. If the condition is "skip", one picture frame data is skipped. Or else decoding sync is generated, and controller is suspended for given `pic_dis_sync` duration which is determined by picture format information. If picture decoding is completed within the given `pic_dis_sync' duration, the state is changed to wait sync state, and next decoding cycle is executed. If picture decoding is not completed within the given duration, the state is changed to task overrun state. In the task overrun state, as soon as picture decoding is completed, next decoding cycle is executed without waiting `pic_dis_sync' transition.
WAIT SYNC
PIC_DIS_SYNC =
or
DEC. COMPLETE COMMAND DEC. COMPLETE TASK OVERRUN SKIP PIC_DIS_SYNC = or DEC. CHECK REPEAT DEC. SYNC GEN. SKIP
WAIT
WAIT
Figure 3. Picture Decoding Control State Diagram
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GDC21D401B
5.3 STC (System Time Clock) Generation
Internal STC counter is supported. STC value should be loaded after the reset by host microprocessor or transport decoder, and be counted at 90 KHz clock derived from external 27 MHz system clock. Also it should be loaded whenever the system time base is changed. 27 MHz system clock is supplied by transport decoder through external 27 MHz clock input. When system time base is changed, the time base of the current DTS can differ from that of the new STC temporarily because of video decoding delay. In this case, for about 0.5 sec, DTS synchronization mode must be disabled by using decoding mode register.
5.5 Error Concealment
When the VLD detects a bitstream syntax error or an MPEG-2 error code (0x000001B4), it performs appropriate error handling and error concealment to continue the decoding and to minimize the effect of the error on decoded video. If an error occurs at picture data layer, the slice-based error concealment is performed. If an error occurs at header layer, the associated sequence is skipped.
5.4 DTS (Decoding Time Stamp) Synchronization
The DTS values are determined when the associated pictures are decoded referring to the STC. The transport decoder must extract PTS & DTS values from MPEG-2 system layer, and transfer them to the VD through host interface or transport data interface. DTS values are extracted and stored in DTS-FIFO with 8-bit associated picture numbers(they are defined by the VD internally). Before each picture decoding, picture decoding controller checks if there is a DTS associated with each picture. And it compares the DTS value from DTS-FIFO with STC value. The DTS value is considered to match the current STC value if the DTS satisfies this equation:
STC + jitter_b(negative) < DTS < STC + jitter_f(positive)
5.6 User Data Read
User data in MPEG Video Sequence can be read 2 through host interface(I C) as follows. If user data interrupt is enabled, user data is stored in internal user data FIFO, and once `PIC_DEC_SYNC' is set to `high', a interrupt signal is generated which informs host that user data is stored in user data FIFO. If user data interrupt is disabled, user data is discarded. When user data interrupt signal is generated, host reads the `U_D_COUNT' register for bytes of user data FIFO. And then it reads the `USER_DATA' register(user data FIFO output) repeatedly as many as the number of `U_D_COUNT' register. In this case, the host 2 had better use I C burst read cycle for reading speed efficiency. If internal user data FIFO becomes full during user data interrupts, `\UBUFF_FULL' signal is generated. And also the host reads user data by using the same method as that of user data interrupt.
In the case that jitter is the tolerance for the comparison: If the DTS is less than STC + jitter_b (in other words, the time for current picture decoding has already passed), picture decoding controller discards B picture in VBV delay mode and any picture in low delay mode without decoding it. If the DTS is greater than STC + jitter_f (the time for current picture decoding has not come yet), picture decoding controller pauses decoding process until the DTS value falls within the allowed tolerance of STC.
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GDC21D401B
5.7 Bitstream Buffer Over/Underflow
The bitsream buffer should not be overflowed or underflowed in proper operation. When bitstream buffer is overflowed, video bitstream input is disabled during overflow. At the beginning of each picture, buffer underflow is checked. If the bitstream buffer doesn't include 1 picture bitstream, decoding is paused until this buffer is filled with 1 picture bitstream.
5.10 IDCT (Inverse Discrete Cosine Transform)
Coefficient data from IQ block is transmitted to IDCT block. IDCT block transforms these coefficients to pixel data or differential pixel data which have the values in the range of -256 to 255. For one 8x8 DCT block, the elapse time through IDCT block is a 30-VDCLK period. In the IDCT block, 8 adjacent coefficients are processed in parallel. The maximum transform speed of the IDCT block is 1 VDCLK x 4 Sample/sec. This speed is sufficient for decoding 1920x1088 30Hz frame data.
5.8 VLD (Variable Length Decoder)
The VLD executes the variable length decoding of MPEG-2 MP@HL. It is composed of sequence syntax parsing and code decoding. Headers, IDCT coefficients, and motion vectors are generated from input video bitstream by the VLD.
5.11 MC(Motion Compensation)
Motion Compensation Block restores macroblocks by using macroblock difference data from IDCT block and reference data which are read from external SDRAM. Address Generation Block in the MC generates SDRAM address by transforming macroblock address and motion vector to row/column address of SDRAM. The MC block supports all motion types of frames and field pictures. Motion vector range decoded in the MC has the range of f_code=9 for horizontal motion vector and f_code=8 for vertical motion vector. Reconstructed macroblock in the MC block is stored in the external frame memory for I or P picture, but in the case of B picture, decoded macroblock is transmitted directly to the VDP without being stored in the frame memory. Because reordering occurs in I or P picture decoding, macroblock data to be displayed is read from reference frame memory and is transmitted to the VDP in the form of macroblock.
5.9 Inverse Quantization
For decoding a macroblock, various parameters are transmitted to IQ block and MC block in sequence of decoding syntax from the VLD. Coefficient data transmitted to IQ block is multiplied by quantization matrix and quantization scale. Quantized coefficients are stored in two coefficient buffers, and if a request from MC block occurs, the buffer outputs 4 coefficients in parallel. Inverse scan processing is performed in the coefficient buffer by varying read/write address according to scan type.
13
GDC21D401B
5.12 Transport Interface
8-bit parallel data(vid_data[7:0]) interface is supported for transport data interface. Three kinds of data (Video bitstream, STC, and DTS) can be transferred through transport data interface. If \vid_en is low, video bitstream is transferred. If vstcw is high, STC is transferred. If tsw is high, PTS & DTS are transferred. Or else no data is transferred. Vid_data[7:0] is latched on the rising edge of vid_strb. When \VID_REQ is high, transport data interface is disabled, and when \VID_REQ is low, transport data interface is enabled. See the following Fig. 4.
VID_STRB TSW VSTCW \VID_EN VID_DATA
32 31:24 23:16 15:8 7:0 32
all `0' all `1'
31:24 23:16 15:8 7:0 32 31:24 23:16 15:8 7:0
PTS[32:0]
DTS[32:0]
PTS[32:0]
VID_STRB TSW VSTCW \VID_EN VID_DATA
32 31:24 23:16 15:8 7:0
all `0'
..... Video Bitstream
STC[32:0]
Figure 4. Transport Data Interface Timing Diagram
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GDC21D401B
5.13 Host Interface
I2C bus interface
I C bus interface is used for host data interface. It operates only as a Slave. The Chip-ID(dev address) of this IC is "0001111"b. Data on the 2 I C-bus can be transferred at the rate up to 100
2
kbit/s in the standard mode, or up to 400 kbit/s in 2 the fast mode. I C bus data read/write formats of this IC are shown in the Fig 5, 6, and 7. Burst Read Cycle can be used for the user data reading. 2 For more information, see the I C bus interface standard.
START CHIP ID
WRITE ACK ACK
START CHIP ID
WRITE ACK
PAUSE ACK
S
0001111
0
0
REG. ADDR.(7:0) 0
S
0001111
0
0
REG. DATA(7:0) 0
P
Figure 5. Write Cycle Diagram
START CHIP ID
WRITE ACK ACK
START CHIP ID
READ ACK
PAUSE ACK
S
0001111
0
0
REG. ADDR.(7:0) 0
S
0001111
1
0
REG. DATA(7:0) 1
P
Figure 6. Read Cycle Diagram
START CHIP ID
WRITE ACK ACK
START CHIP ID
READ ACK ACK
S
0001111
0
0
REG. ADDR.(7:0) 0
S
0001111
1
0
REG. DATA(7:0) 0
REG. DATA(7:0) 0
......
REG. DATA(7:0) 1
P
ACK
ACK PAUSE
Figure 7. Burst Read Cycle Diagram
15
GDC21D401B
Interrupt Mechanism
The host enables specific interrupt events to occur by setting the mask value of internal interrupt. When an event occurs and corresponding interrupt enable is set, an interrupt bit is set in an interrupt register. Everytime each picture decodes sync, host checks the contents of that register, and if any bit is set, it generates an interrupt. Exceptionally, in the case of OVF, UND and ERR interrupt signals are generated as soon as the error is detected. When the host serves the interrupt, interrupt register and interrupt signal are reset.
Table 2. Bit Definitions for Interrupt Register & Mask BIT # 0 1 2 3 4 5 6 MNEMONIC PIC_S GOP_H SEQ_H SEQ_E USR OVF UND/PTS EVENT Picture decoding GOP header decoding Seq. header decoding Seq. end decoding User data ready Buffer overflow Buffer underflow/ PTS received EVENT DEFINITION New picture is decoded. GOP headers are decoded. Sequence headers are decoded. Sequence end code is decoded. User data has been extracted and stored in the buffer. When the interrupt is disabled, user data is discarded. Bitstream buffer is full. Dec_mode(4) = `0': Bitstream buffer doesn't have 1 picture bitstream. Dec_mode(4) = `1' PTS value is received through transport interface. Error code or syntax error is detected in the bitstream (header layer).
7
ERR
Bitstream error
16
GDC21D401B
Register Description
Table 3. Internal Register Description NO 0 1 2 NAME Command Interrupt DTS0 SIZE 3 8 8 DESCRIPTION High level decoding command. Interrupt register. DTS[7:0]. When it is written by host microprocessor, DTS[19:0] values are stored in the DTS-FIFO. When DTS value is received through transport interface, it can be read via the DTS registers DTS[15:8]. DTS[19:16]. Forward tolerance of DTS synchronization, Jitter_f[7:0]. When it is written by host microprocessor, Jitter_f[19:16] values are applied. Jitter_f[15:8]. Jitter_f[19:16]. Backward tolerance of DTS synchronization, Jitter_b[7:0]. When it is written by host microprocessor, Jitter_b[19:16] values are applied. Jitter_b[15:8]. Jitter_b[19:16]. Slow motion command of repeated numbers. Header data register. It has header value indicated by H_addr. Header data address. User data register. It is an output of the User data FIFO. User data count in the User data FIFO. Interrupt mask. Decoding mode. System time clock, STC[7:0]. When it is written by host microprocessor, STC[19:0] values are loaded to internal STC counter. STC[15:8]. STC[19:16]. Write address pointer of the bitstream buffer. Unit value is 65,536 bits. Read address pointer of the bitstream buffer. Unit value is 65,536 bits. PTS[7:0]. When PTS value is received through tranport interface, it is stored in the PTS registers. PTS[15:8]. PTS[19:16]. DEFAULT play() all `0' all `0' R/W R/W R R/W
3 4 5
DTS1 DTS2 Jitter_f0
8 4 8
all `0' all `0' h"10"
R/W R/W R/W
6 7 8
Jitter_f1 Jitter_f2 Jitter_b0
8 4 8
h"0E" h"0" h"BA"
R/W R/W R/W
9 10 11 12 13 14 15 16 17 18
Jitter_b1 Jitter_b2 Slm_num Header H_addr User_data U_d_count Int_mask Dec_mode STC0
8 4 6 8 8 8 7 8 8 8
h"FA" h"F" h'8' all `0' all `0' all `0' all `0' all `0' all `0' all `0'
R/W R/W R/W R R/W R R R/W R/W R/W
19 20 21 22 23 24 25
STC1 STC2 W_ptr R_ptr PTS0 PTS1 PTS2
8 4 8 8 8 8 4
all `0' all `0' all `0' all `0' all `0' all `0' all `0'
R/W R/W R R R R R
17
GDC21D401B
Table 4. Definitions of Command Register. REG. VALUE 0 1 2 3 4 5 6 7 COMMAND Reset() Play() Slow_motion() Scan() Single_step() Pause() Fast_forward() NoCOM() DESCRIPTION Bitstream buffer is flushed and decoding controllers are reset. Start normal bitstream decoding. Decode pictures and pause during slm_num duration, and repeat this process. Skip to I picture and continue decoding. Decode 1 picture and pause. Decoding pause. Decode only I or P picture. No command is loaded in the register. In this state bitstream buffer continues to be filled with input bitstreams.
Table 5. Definition of Header Address H_ADDR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 HEADER H_size[7:0] V_size[7:0] `0'& h_size[10;8] & `0' & v_size[10:8] Aspect_ratio[3:0] & frame_rate[3:0] `0'&prog_seq&'0'&low_delay& pict_cod_type[1:0]& `0'&repeat_first_field Matrix_coefficients[7:0] VBV_delay[7:0] VBV_delay[15:8] Time_code[7:0] Time_code[15:8] Time_code[23:16] "0000000"&Time_code[24] Temporal_reference[7:0] "000000"&Temporal reference[8:9] Copyright_extension[7:0] Copyright_extension[15:8] Copyright_extension[23:16] Copyright_extension[31:24] Copyright_extension[39:32] Copyright_extension[47:40] Copyright_extension[55:48] Copyright_extension[63:56] Copyright_extension[71:64] Copyright_extension[79:72] "0000"&Copyright_extension[83:80]
18
GDC21D401B
Table 6. Definition of Decoding Mode Register BIT # 0 1 DESCRIPTION It must have "High". DTS input timing: `0' => DTS values are transferred to VD before the associated PSTC. `1' => DTS values are transferred to VD after the associated PSTC. PSTC represents the Picture Start Code. DTS synchronization: `0' => disabled `1' => enabled Picture reordering in VBV delay mode: `0' => enabled `1' => disabled Int_reg(6) & Int_mask(6) selection: `0' => UND `1' => PTS "000" : Not used
2 3 4 5~7
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GDC21D401B
5.14 Video Data Output Format
Video decoder transmits decoded macroblock data to the VDP via 32-bit bus. This bus consists of 4 adjacent pixel components. For a macroblock data, the number of 32-bit data is 96. The order of output data is the same of decoded block in the MPEG-2 Video bitstream syntax. For this reason, output sequence depends on the DCT_TYPE of decoded macroblock. Except for the macroblock
0 2 4 6 8 10 12 14 32 34 36 38 40 42 44 46 1 3 5 7 9 11 13 15 33 35 37 39 41 43 45 47 16 18 20 22 24 26 28 30 48 50 52 54 56 58 60 62 17 19 21 23 25 27 29 31 49 51 53 55 57 59 61 63
whose parameter is Frame picture and Field DCT, all macroblock outputs have the sequence of below figure(MBFI=0) in Fig 8. The top field data of the macroblock whose DCT_TYPE is field type(MBFI=1) is transmitted before the macroblock bottom field data for the luminance data. But the chrominance data has always the same sequence.
64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95
MBFI == 0
0 32 2 34 4 36 6 38 8 40 10 42 12 44 14 46 1 33 3 35 5 37 7 39 9 41 11 43 13 45 15 47 16 48 18 50 20 52 22 54 24 56 26 58 28 60 30 62 17 49 19 51 21 53 23 55 25 57 27 59 29 61 31 63 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95
MBFI == 1 Figure 8. The Sequence of Macroblock Output
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GDC21D401B
5.15 Video Data Output Timing
During decoding the picture which is field picture or frame picture, PDWIN signal is high. Between each picture decoding time, there is low level period of PDWIN signal, and it is longer than 128 VDCLKs. Picture parameter such as PSTR[1:0] or \FFPN is determined 2 clocks before PDWIN rising edge. Its value is not changed until PDWIN falling edge. SCLK shows that new slice decoding is started on its rising edge. Width of MBCLK high pulse is always 96 clocks, and low value period is longer than 2 clocks.
PDWIN PSTR[1:0] \FFPN SCLK
2 VDCLKs
Minimum 1 VDCLK
Minimum 128 VDCLKs
SCLK MBCLK
MBFI PDATA[31:0]
0 1 2 3 94 95
VDCLK
Figure 9. Timing Diagram
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GDC21D401B
5.16 SDRAM Interface
For storing reference frame data and bitstream, very large external memory is required. For this reason, 64-Mbit external memory (GM72V161621AT or same type of memory) is needed. The memory configuration is shown in the following Fig 10. Four 16-Mbit memories are directly attached to the VD. Data bus for SDRAMs is configured to 64-bit bus. Memory interface clock should be supplied to the VD and four SDRAMs with same clock phase. Higher frequency for MCLK and higher decoding speed can be achieved. The maximum frequency of MCLK is 81 MHz. This clock doesn't need to be locked with any other input clock.
Revision Note for SDRAM Clock Application Note(1): Recommended
4 ~ 10.5ns
SDRAM
16
CSN,WEN,RASN,CASN, BA0 SDRAM_ADDR[10:0]
5
CLK
11
SDRAM_DATA[63:0]
# 94
64
SDRAM
16
CLK
MCLK MCLK_IN
SDRAM
16
VSS MCLK_OUT N.C.
(No Connect)
CLK
SDRAM
16
CLK
CLK Driver
Figure 10. External Memory Interface 1
22
GDC21D401B
Revision Note for SDRAM Clock Application Note(2)
16
SDRAM
CLK
CSN,WEN,RASN,CASN, BA0 SDRAM_ADDR[10:0] SDRAM_DATA[63:0] MCLK MCLK_IN MCLK_OUT
# 94 # 234 # 237
5 11
64
16
SDRAM
CLK
SDRAM
16
CLK
16
SDRAM
CLK
CLK Driver
2 ~ 5 ns
# 234
# 237
Clock delay equivalent circuit
Figure 11. External Memory Interface 2
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GDC21D401B
6. Electrical Specification 6.1 Absolute Maximum Rating
SYMBOL PARAMETERS VALUES UNIT Power Supply Voltage -0.33 to 5.5 V VDD Digital Input Voltage -0.33 to VDD + 0.5 V VI Digital Output Voltage -0.33 to VDD + 0.5 V Vo Storage Temperature -55 to 125 Tstg C Power Dissipation 4.6 W Pd *Note :Absolute Maximum Ratings mean that the safety of the device cannot be guaranteed beyond these values, and this doesn't imply that the device should be operated within these limits.
6.2 Recommended Operating Range
SYMBOL VDD Topr PARAMETERS Power Supply Voltage Operating Temperature VALUES 3.3 10% 0 to 70 UNIT V C
6.3 DC Characteristics (VDD = 3.3 V 3/4 0%, TA = 0 ~ 70 E 1 )
SYMBOL VIH VIL VOH VOL IDD IDDQ FOPR PARAMETER Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Operating Current Standby Current Operating Frequency MIN 0.7X VDD -0.33 2.4 0 MAX VDD +0.33 0.2X VDD VDD 0.4 900 10 54 UNIT V V V V mA uA MHz
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GDC21D401B
6.4 AC Characteristics (VDD = 3.3 V 3/4 0%, TA = 0 ~ 70 E 1 )
tCP
MCLK VDCLK CLK27M VID_STRB
tCH
tCL
tS
All Intputs except for SDRAM I/F signals
tH
All Outputs except for SRAM I/F signals
tOD
Figure 12. Input/Output Timing SYMBOL PARAMETERS MIN Clock Period tCPmclk Clock Period tCPvdclk Clock Period tCPclk27m Clock Period tCPvid strb Clock High Time/Clock Low Time 5.5 tCHmclk/tCLmclk Clock High Time/Clock Low Time 8 tCHvdclk/tCLvdclk 16 tCHclk27m/tCLvdclk Clock High Time/Clock Low Time 16 tCHvid strb/tCLvdclk Clock High Time/Clock Low Time Input Hold Time 7 tH Input Setup Time 7 ts Output Delay Time tOD *Note : Low voltage input signal rising and falling edge switching time = 1.0 ns MAX 7.5 12 20 20 17 TYPE 13 20 36 36 UNIT ns ns ns ns ns ns ns ns ns ns ns
SDRAM I/F AC Characteristics (GDC21D401HQ)
SIGNAL SDRAM_DATA[63:0] SYMBOL Propagation Delay Setup Time Hold Time Propagation Delay Propagation Delay Propagation Delay MIN 4 0 2 4 4 4 MAX 10.5 0 3 10.5 10.5 10.5 TYPE UNIT ns ns ns ns ns ns
SDRAM_ADDR[10:0] BA0 CSN, WEN, RASN, CASN *Test Condition : Load Capacitance = 20pF 1.Min. Condition : Temperature = 0 C, VDD = 3.6 V 2. Max. Condition : Temperature = 100 C, VDD = 3.0 V
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GDC21D401B
7. Package Mechanical Data 7.1 Package Pin Out
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 TYPE GND I PWR I I I GND I I I I GND I I I I PWR I GND I I PWR I GND I I GND I/O O O O PWR I/O I/O GND I/O PWR I/O I/O I/O NAME VSS SCANTESTON VDD IDCTTESTON MEMTESTON CLK_27M VSS \RESET TSW \VIDEN VSTCW VSS VID_STRB VID_DATA[0] VID_DATA[1] VID_DATA[2] VDD VID_DATA[3] VSS VID_DATA[4] VID_DATA[5] VDD VID_DATA[6] VSS VID_DATA[7] SCL VSS SDA \VID_REQ \UBUFF_FULL \INT_V VDD SDRAM_DATA[0] SDRAM_DATA[1] VSS SDRAM_DATA[2] VDD SDRAM_DATA[3] SDRAM_DATA[4] SDRAM_DATA[5] PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 TYPE PWR I/O I/O PWR I/O GND I/O I/O PWR I/O I/O GND I/O I/O PWR I/O I/O GND I/O I/O GND I/O PWR I/O GND I/O PWR I/O GND I/O PWR I/O I/O PWR I/O I/O GND I/O I/O PWR NAME VDD SDRAM_DATA[6] SDRAM_DATA[7] VDD SDRAM_DATA[8] VSS SDRAM_DATA[9] SDRAM_DATA[10] VDD SDRAM_DATA[11] SDRAM_DATA[12] VSS SDRAM_DATA[13] SDRAM_DATA[14] VDD SDRAM_DATA[15] SDRAM_DATA[16] VSS SDRAM_DATA[17] SDRAM_DATA[18] VSS SDRAM_DATA[19] VDD SDRAM_DATA[20] VSS SDRAM_DATA[21] VDD SDRAM_DATA[22] VSS SDRAM_DATA[23] VDD SDRAM_DATA[24] SDRAM_DATA[25] VDD SDRAM_DATA[26] SDRAM_DATA[27] VSS SDRAM_DATA[28] SDRAM_DATA[29] VDD
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GDC21D401B
Package Pin Out(continued)
PIN 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 TYPE I/O I/O GND O GND O O PWR O PWR O O PWR I GND GND GND O O PWR O O O O GND O O O O PWR PWR I/O I/O I/O GND I/O I/O I/O PWR I/O I/O GND I/O NAME SDRAM_DATA[30] SDRAM_DATA[31] VSS SDRAM_ADDR[3] VSS SDRAM_ADDR[4] SDRAM_ADDR[2] VDD SDRAM_ADDR[5] VDD SDRAM_ADDR[1] SDRAM_ADDR[6] VDD MCLK VSS VSS VSS SDRAM_ADDR[0] SDRAM_ADDR[7] VDD SDRAM_ADDR[8] SDRAM_ADDR[9] SDRAM_ADDR[10] BA0 VSS WEN CASN RASN CSN VDD VDD SDRAM_DATA[32] SDRAM_DATA[33] SDRAM_DATA[34] VSS SDRAM_DATA[35] SDRAM_DATA[36] SDRAM_DATA[37] VDD SDRAM_DATA[38] SDRAM_DATA[39] VSS SDRAM_DATA[40] PIN 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 TYPE GND I/O I/O PWR I/O PWR I/O GND GND I/O I/O PWR I/O PWR I/O I/O GND I/O I/O PWR I/O I/O GND I/O I/O PWR I/O GND I/O PWR I/O GND GND I/O I/O PWR PWR I/O I/O I/O GND I O NAME VSS SDRAM_DATA[41] SDRAM_DATA[42] VDD SDRAM_DATA[43] VDD SDRAM_DATA[44] VSS VSS SDRAM_DATA[45] SDRAM_DATA[46] VDD SDRAM_DATA[47] VDD SDRAM_DATA[48] SDRAM_DATA[49] VSS SDRAM_DATA[50] SDRAM_DATA[51] VDD SDRAM_DATA[52] SDRAM_DATA[53] VSS SDRAM_DATA[54] SDRAM_DATA[55] VDD SDRAM_DATA[56] VSS SDRAM_DATA[57] VDD SDRAM_DATA[58] VSS VSS SDRAM_DATA[59] SDRAM_DATA[60] VDD VDD SDRAM_DATA[61] SDRAM_DATA[62] SDRAM_DATA[63] VSS VDCLK SCLK
27
GDC21D401B
Package Pin Out(continued)
PIN 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 TYPE PWR O O GND O PWR PWR O O GND O O O GND GND O O O PWR PWR O GND GND O O O O PWR O O PWR O GND O GND O O NAME VDD MBCLK MBFI VSS \FFPN VDD VDD DIS_INFO D_INFO_WIN VSS PDWIN PSTR[0] PSTR[1] VSS VSS PDATA[0] PDATA[1] PDATA[2] VDD VDD PDATA[3] VSS VSS PDATA[4] PDATA[5] PDATA[6] PDATA[7] VDD PDATA[8] PDATA[9] VDD PDATA[10] VSS PDATA[11] VSS PDATA[12] PDATA[13] PIN 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 TYPE O PWR O O O PWR O O GND O O O O PWR O O O O GND GND O O O O PWR PWR I I GND O I O O O I I I NAME PDATA[14] VDD PDATA[15] PDATA[16] PDATA[17] VDD PDATA[18] PDATA[19] VSS PDATA[20] PDATA[21] PDATA[22] PDATA[23] VDD PDATA[24] PDATA[25] PDATA[26] PDATA[27] VSS VSS PDATA[28] PDATA[29] PDATA[30] PDATA[31] VDD VDD PIC_DIS_SYNC P_WAIT VSS DEC_ERROR MCLK_IN FP_FD TEST_OUT[2] MCLK_OUT P_SHARE_IN[8] P_SHARE_IN[9] P_SHARE_IN[10]
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GDC21D401B
7.2 Physical Dimension
PACKAGE CONTROL OUTLINE, 240Pin Hit-spread Quad Flat Package(HQFP), 32x32 mm2 BODY, 1.30/0.38 mm FORM, 3.40 mm THICK 34.80 34.40 32.10 31.90
34.80 34.40
32.10 31.90
TOP VIEW
Figure 13. Physical Dimensions
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