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FMS6410B Dual-Channel Video Drivers with Integrated Filters and Composite Video Summer
October 2006
FMS6410B Dual-Channel Video Drivers with Integrated Filters and Composite Video Summer
Features
7.1MHz fifth-order Y,C filters with composite summer 50dB stopband attenuation at 27MHz on Y, C, and CV
Description
The FMS6410B is a dual Y/C fifth-order Butterworth lowpass video filter optimized for minimum overshoot and flat group delay. The device also contains a summing circuit to generate filtered composite video. In a typical application, the Y and C input signals from DACs are AC coupled into the filters. Both channels have DC restore circuitry to clamp the DC input levels during video sync. The Y and C channels use separate feedback clamps. The clamp pulse is derived from the Y channel. All outputs are capable of driving 2Vpp, AC or DC coupled, into either a single or dual video load. A single video load consists of a series 75 impedance matching resistor connected to a terminated 75 line. This presents a total of 150 of loading to the part. A dual load is two of these in parallel, which presents a total of 75 to the part. The gain of the Y, C, and CV signals is 6dB with 1Vpp input levels. All video channels are clamped during sync to establish the appropriate output voltage reference levels.
outputs Better than 0.1dB flatness to 4.5MHz on Y, C, and CV outputs No external frequency selection components or clocks < 5ns group delay on Y, C, and CV outputs AC-coupled inputs AC- or DC-coupled outputs Capable of PAL frequency selection components or clocks 0.3% differential gain with 0.2 differential phase on Y, C, and CV channels Integrated DC restore circuitry with low tilt Lead-free SOIC-8 package
Applications
Cable and satellite set-top boxes DVD players Personal Video Recorders (PVR) Video On Demand (VOD)
Block Diagrams
VCC 7 Sync Strip Reference and Timing
YIN
1
6dB
8
YOUT
gM
250mV +
+
6
CVOUT
gM
250mV
CIN
4
6dB
5
COUT
3 GND
Figure 1. Block Diagram
(c) 2004 Fairchild Semiconductor Corporation FMS6410B Rev. 1.0.2
www.fairchildsemi.com
FMS6410B Dual-Channel Video Drivers with Integrated Filters and Composite Video Summer
Ordering Information
Part Number
FMS6410BCS FMS6410BCSX
Package
SOIC-8 SOIC-8
Operating Temperature Range
0C to 70C 0C to 70C
Pb-Free
Yes Yes
Container
Rail Reel
Pack Qty.
95 2500
Pin Configuration
FAIRCHILD
Y IN NC GND C IN 1 8 Y OUT V CC CV OUT C OUT
FMS6410B
2 7
8L SOIC
3 4 6 5
Figure 2. Pin Configuration
Pin Assignments
Pin#
1 2 3 4 5 6 7 8
Pin
YIN NC GND CIN COUT CVOUT VCC YOUT
Type
Input
Description
Luminance (luma) input: This pin is typically connected to the luma or composite video output pin from the external video encoder. No connect. Must be tied to ground. Chrominance (chroma) Input: This pin is typically connected to the chroma output pin from the external video encoder. Filtered chrominance video output from the CIN channel. Composite video output: This pin is the sum of YOUT and COUT. +5V supply. Filtered luminance output from the YIN channel.
Input Input Output Output Input Output
Typical Application Diagram
FMS6410B may also be DC-Coupled 0.1F YIN 1 YIN YOUT 8 75 220F YOUT 75 FMS6410B CVOUT 6
75
220F To TV 75
0.1F CIN
4
75 CIN COUT VCC GND 7 3 75 5
220F CVOUT to VCR
75
5V 0.1F
220F COUT 75
10F
Figure 3. AC- or DC-Coupled Application Diagram
(c) 2004 Fairchild Semiconductor Corporation FMS6410B Rev. 1.0.2 2
www.fairchildsemi.com
FMS6410B Dual-Channel Video Drivers with Integrated Filters and Composite Video Summer
Absolute Maximum Ratings
The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table defines the conditions for actual device operation.
Parameter
DC Supply Voltage Analog and Digital I/O Output Current Any One Channel, Do Not Exceed
Min.
-0.3 -0.3
Max.
6.0 Vcc + 0.3 40
Unit
V V mA
Reliability Information
Symbol
TJ TSTG TL JA Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Thermal Resistance, JEDEC Standard Multi-Layer Test Boards, Still Air 115 -65
Parameter
Min.
Typ.
Max.
150 150 300
Unit
C C C C/W
Recommended Operating Conditions
Symbol
TA VCC Supply Voltage Range
Parameter
Operating Temperature Range
Min.
0 4.75
Typ.
5.00
Max.
70 5.25
Unit
C V
(c) 2004 Fairchild Semiconductor Corporation FMS6410B Rev. 1.0.2 3
www.fairchildsemi.com
FMS6410B Dual-Channel Video Drivers with Integrated Filters and Composite Video Summer
DC Electrical Characteristics
TA = 25C, VCC = 5V, VIN = 1Vpp; all inputs are AC coupled with 0.1F; all outputs are AC coupled with 220F into 150 loads; referenced to 400kHz; unless otherwise noted.
Symbol
ICC VIN PSRR Supply
Parameter
Current(1) No Load Input Voltage Maximum Power Supply Rejection Ratio
Conditions
Min.
Typ.
50 1.4 60
Max.
60
Unit
mA Vpp dB
All Channels, DC
Notes: 1. 100% tested at 25C.
AC Electrical Characteristics
TA = 25C, VCC = 5V, VIN = 1Vpp; all inputs are AC coupled with 0.1F; all outputs are AC coupled with 220F into 150 loads; referenced to 400kHz; unless otherwise noted.
Symbol
AV Csync Ysync CVsync tCLAMP fFLAT fC fSB dG dP THD XTALK SNR tpd GD tSKEW tCLGCV tCLDCV Channel
Parameter
Gain(1) sync)(1)
Conditions
All Channels Sync Present on YIN (after 6dB gain) Sync Present on YIN (after 6dB gain) Y Channel, Settled to within 10mV All Channels All Channels All Channels at 27MHz All Channels All Channels VOUT = 1.4Vpp, 3.58MHz at 3.58MHz All Channels, NTC-7 weighting, 4.2MHz LP, 100kHz HP All Channels All Channels at 3.58MHz at 1MHz f = 3.58MHz (Ref. to YIN at 400kHz) f = 3.58MHz (Ref. to YIN at 400kHz)
Min.
5.75
Typ.
6.00 1.0 0.35 0.35 10 0
Max.
6.25 1.3 0.50 0.50
Unit
dB V V V ms dB MHz dB % deg % dB dB ns ns ns
COUT Output Level (during sync)(1) Sync Present on YIN (after 6dB gain) YOUT Output Level (during CVOUT Output Level (during sync)(1) Clamp Response Time Gain Flatness to 4.5MHz -3dB Bandwidth(1) Attenuation(1) Stopband
6.7 42
7.1 50 0.3 0.2 0.3 -50 82 115 4 0
Differential Gain Differential Phase Output Distortion Crosstalk Signal-to-Noise Ratio Propagation Delay Group Delay Deviation Skew Between YOUT and COUT Chroma-Luma Gain CVOUT(1) Chroma-Luma Delay CVOUT
96
100 4
104
% ns
Notes: 1. 100% tested at 25C.
(c) 2004 Fairchild Semiconductor Corporation FMS6410B Rev. 1.0.2 4
www.fairchildsemi.com
FMS6410B Dual-Channel Video Drivers with Integrated Filters and Composite Video Summer
Applications Information
Functional Description
This product is a two-channel, monolithic, continuoustime, video filter designed for reconstructing the luminance and chrominance signals from an S-Video D/A source. Composite video output is generated by summing the Y and C outputs. The chip is designed to have AC-coupled inputs and work with either AC- or DC-coupled outputs. The reconstruction filters provide a fifth-order Butterworth response with group delay equalization. This provides a maximally flat response in terms of delay and amplitude. Each of the three outputs is capable of driving 2Vpp into a 75 load. All channels are clamped during the sync interval to set the appropriate minimum output DC level. With this operation, the effective input time constant is greatly reduced, which allows use of small, low-cost coupling capacitors. The net effect is that the input settles to 10mV in 10ms for any DC shifts present in the input video signal. In most applications, the input coupling capacitors are 0.1F. The Y and C inputs typically sink 1A of current during active video, which normally tilts a horizontal line by 2mV at the Y output. During sync, the clamp restores this leakage current by sourcing an average of 20A over the clamp interval. Any change in the coupling capacitor values affect the amount of tilt per line. Any reduction in tilt comes with an increase in settling time.
Layout Considerations
General layout and supply bypassing play major roles in high-frequency performance and thermal characteristics. Fairchild offers a demonstration board, FMS6410BDEMO, to guide layout and aid device testing and characterization. The FMS6410BDEMO is a fourlayer board with a full power and ground plane. For optimum results, follow the steps below as a basis for highfrequency layout:
Include 10F and 0.1F ceramic bypass capacitors. Place the 10F capacitor within 0.75 inches of the
power pin. Place the 0.1F capacitor within 0.1 inches of the power pin. If using DC-coupled outputs, use a large ground plane to help dissipate heat. Minimize all trace lengths to reduce series inductances.
Output Interface
To obtain the highest quality output signal, place the series termination resistor as close to the device output pin as possible. This greatly reduces the parasitic capacitance and inductance effect on the output of the driver. Place the series termination resistor less than 0.1 inches from the device pin, as shown in Figure 4.
Luminance (Y) I/O
The typical luma input is driven by either a low-impedance source of 1Vpp or the output of a 75 terminated line driven by the output of a current DAC. In either case, the input must be capacitively coupled to allow the syncdetect and DC-restore circuitry to operate properly. All outputs are capable of driving 2Vpp, AC or DC coupled, into either a single or dual video load. A single video load consists of a series 75 impedance matching resistor connected to a terminated 75 line, presenting a total of 150 of loading to the part. A dual load is two of these in parallel, which presents a total of 75 to the part. The gain of the Y, C, and CV signals is 6dB with 1Vpp input levels.
Figure 4. 75 Series Resistor 0.1 Inches from Pin Figure 5 is the schematic representation of a video filter/ driver used in a system as the output driver to a media device. In this case, the composite video signal is terminated by the media device and the S-video output terminations are open. It is very critical to have the series termination resistors close to the output pins of the device to minimize the effects of parasitic capacitance on the filter output driver which may show up as noise on the CV output.
Chrominance (C) I/O
The chrominance input can be driven in the same manner as the luminance input, but is typically only a 0.7Vpp signal. Since the chrominance signal doesn't contain any DC content, the output signal can be AC coupled using a capacitor as small as 0.1F if DC coupling is not desired.
Composite Video (CV) Output
The composite video output driver is same as the other outputs.
(c) 2004 Fairchild Semiconductor Corporation FMS6410B Rev. 1.0.2 5
www.fairchildsemi.com
FMS6410B Dual-Channel Video Drivers with Integrated Filters and Composite Video Summer
Applications Information (Continued)
Fairchild Filter Drive r 75 Ohm Clamp / Bias
LPF
Buf Series Termanatio n Resisto r 0.1 inche s from DUT pin
+
Filter/Driver set for gain of 2 X
S-Video
75 Ohm
RC A JACK
3 1
4 2
Coax ADC 75 Ohm
Summe r Series Termanatio n Resisto r 0.1 inche s from DUT pin
+
Media
Fairchild Filter Drive r 75 Ohm Clamp / Bias
LPF
Buf Series Termanatio n Resisto r 0.1 inche s from DUT pin
Filter/Driver set for gain of 2 X
Figure 5. Schematic Representation of a Video Filter / Driver
(c) 2004 Fairchild Semiconductor Corporation FMS6410B Rev. 1.0.2 6
+
www.fairchildsemi.com
FMS6410B Dual-Channel Video Drivers with Integrated Filters and Composite Video Summer
Physical Dimensions
Figure 6. 8-Lead Small Outline Integrated Circuit (SOIC) Package
(c) 2004 Fairchild Semiconductor Corporation FMS6410B Rev. 1.0.2 7
www.fairchildsemi.com
FMS6410B Dual-Channel Video Drivers with Integrated Filters and Composite Video Summer
www.fairchildsemi.com
(c) 2004 Fairchild Semiconductor Corporation
FMS6410B Rev. 1.0.2
8

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