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| FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges December 2006 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges Features Low power consumption Fairchild proprietary low-power CTL interface LVCMOS parallel I/O interface: tm Description The FIN12AC is a 12-bit serializer capable of running a parallel frequency range between 5MHz and 40MHz. The frequency range is selected by the S1 and S2 control signals. The bi-directional data flow is controlled through use of a direction (DIRI) control pin. The devices can be configured to operate in a unidirectional mode only by hardwiring the DIRI pin. An internal PhaseLocked Loop (PLL) generates the required bit clock frequency for transfer across the serial link. Options exist for dual or single PLL operation, dependent upon system operational parameters. The device has been designed for low power operation and utilizes Fairchild proprietary low-power control Current Transistor Logic (CTL) interface. The device also supports an ultra low power powerdown mode for conserving power in battery-operated applications. - 2mA source / sink current - Over-voltage tolerant control signals Parallel I/O power supply (VDDP) range between 1.65V and 3.6V Analog power supply range of 2.5V to 3.05V Multi-mode operation allows for a single device to operate as Serializer or Deserializer Internal PLL with no external components Standby power-down mode support Small footprint packaging: - 32-terminal MLP and 42-ball BGA Built-in differential termination Supports external CKREF frequencies; 5MHz to 40MHz Serialized data rate up to 560Mb/s Voltage translation from 1.65V to 3.6V Applications Microcontroller or pixel interfaces Image sensors Small displays: LCD, cell phone, digital camera, portable gaming, printer, PDA, video camera, automotive Ordering Information Operating Temperature Range Packing Method Part Number FIN12ACGFX FIN12ACMLX Package 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide 32-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 5mm Square Pb-Free Yes Yes -30C to +70C Tape and Reel -30C to +70C Tape and Reel SerDesTM is a trademark of Fairchild Semiconductor Corporation. (c) 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.0 www.fairchildsemi.com FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges Functional Block Diagram CKREF PLLx_SEL PLL cksint 0 I Word Boundary Generator I 0 + diri_int CKS0+ CKS0- STROBE DP[1:12] Serializer Control Serializer + + cksint + DSO+/DSIDSO-/DSI+ 100 Gated Termination CKSI+ CKSI100 Gated Termination Register Register I Deserializer Deserializer Control CKP 0 WORD CK Generator Control Logic S1 S2 DIRI diri_int Freq Control Direction Control DIRO Power Down Control Figure 1. FIN12AC Block Diagram Connection Diagrams Terminal Assignments for MLP 27 STROBE 26 CKREF 32 DP[3] 31 DP[2] 30 DP[1] 25 DIRO 29 N/C 28 N/C Pin Assignments for BGA 1 24 CKSO+ 23 CKSO22 DSO+/DSI21 DSO-/DSI+ 20 CKSI19 CKSI+ 18 DIRI 17 VDDS 2 3 4 5 6 DP[4] DP[5] DP[6] VDDP CKP DP[7] DP[8] DP[9] 1 2 3 4 5 6 7 8 A B C D E F G (Top View) 10 11 12 13 14 15 (c) 2006 Fairchild Semiconductor Corporation DP[10] DP[11] DP[12] N/C PLLx_SEL S2 S1 VDDA (Top View) Figure 2. Terminal and Pin Assignments 16 9 www.fairchildsemi.com FIN12AC Rev. 1.1.0 2 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges Terminal Descriptions for MLP Pin Name DP[1:12] CKREF STROBE CKP DSO+ / DSIDSO- / DSI+ I/O Type I/O IN IN OUT DIFF-I/O Number of Terminals 12 1 1 1 2 Description of Signals LVCMOS parallel I/O, Direction controlled by DIRI pin LVCMOS clock input and PLL reference LVCMOS strobe signal for latching data into the serializer LVCMOS word clock output. This signal is the regenerated STROBE signal CTL differential serial I/O data signals(1) DSO: Refers to output signal pair DSI: Refers to input signal pair DSO(I)+: Positive signal of DSO(I) pair DSO(I)-: Negative signal of DSO(I) pair CTL differential deserializer input bit clock CKSI: Refers to signal pair CKSI+: Positive signal of CKSI pair CKSI-: Negative signal of CKSI pair CTL differential deserializer output bit clock CKSO: Refers to signal pair CKSO+: Positive signal of CKSO pair CKSO-: Negative signal of CKSO pair Used to define frequency range for the RefClock, CKREF. Used to define PLL multiplication mode. PLLX_SEL = 0 multiplication factor 7-1/3x PLLX_SEL = 1 multiplication factor 7x LVCMOS control input. Used to control direction of data flow: DIRI = "1" Serializer DIRI = "0" Deserializer LVCMOS output, inversion of DIRI Power supply for parallel I/O and translation circuitry Power supply for core and serial I/O Power supply for analog PLL circuitry Use bottom ground plane for ground signals CKSI+ / CKSI- DIFF-IN 2 CKSO+ / CKSO- DIFF-OUT 2 S1 S2 PLLx_SEL IN IN IN 1 1 1 DIRI IN 1 DIRO VDDP VDDS VDDA GND OUT Supply Supply Supply Supply 1 1 1 1 0 Notes: 1. The DSO/DSI serial port pins have been arranged such that if one device is rotated 180 with respect to the other device, the serial connections properly aligns without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross. Pin Assignments for BGA Pin Assignments 1 A B C D E F G DP4 DP6 CKP N/C DP8 DP10 DP12 2 DP2 DP5 N/C DP7 DP9 DP11 N/C 3 N/C DP1 DP3 VDDP GND N/C N/C 4 N/C N/C N/C GND VDDS VDDA PLLx_SEL 5 N/C STROBE CKSO+ DSO-/DSI+ CKSI+ N/C S2 6 CKREF DIRO CKSODSO+/DSICKSIDIRI S1 N/C = No Connect (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 3 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges Control Logic Circuitry The FIN12AC has the ability to be used as a 12-bit serializer or a 12-bit deserializer. Terminals S1 and S2 must be set to accommodate the clock reference input frequency range of the serializer. Table 1 shows the terminal programming of these options based on the S1 and S2 control terminals. The DIRI terminal controls whether the device is the serializer or a deserializer. When DIRI is asserted LOW, the device is configured as a deserializer. When the DIRI terminal is asserted HIGH, the device is configured as a serializer. Changing the state on the DIRI signal reverses the direction of the I/O signals and generates the opposite state signal on DIRO. For unidirectional operation, the DIRI terminal should be hardwired to the HIGH or LOW state and the DIRO terminal should be left floating. For bi-directional operation, the DIRI of the master device is driven by the system and the DIRO signal of the master is used to drive the DIRI of the slave device. put clock period has the same variation as the serializer outputs. Turn-Around Functionality The device passes and inverts the DIRI signal through the device asynchronously to the DIRO signal. Care must be taken by the system designer to ensure that no contention occurs between the deserializer outputs and the other devices on this port. Optimally the peripheral device driving the serializer should be put into a HIGHimpedance state prior to the DIRI signal being asserted. When a device with dedicated data outputs turns from a deserializer to a serializer, the dedicated outputs remain at the last logical value asserted. This value only changes if the device is once again turned into a deserializer and the values are overwritten. Power-Down Mode Mode 0 is used for powering down and resetting the device. When both of the mode signals are driven to a LOW state, the PLL and references are disabled, differential input buffers are shut off, differential output buffers are placed into a HIGH-impedance state, LVCMOS outputs are placed into a HIGH-impedance state, LVCMOS inputs are driven to a valid level internally, and all internal circuitry are reset. The loss of CKREF state is also enabled to ensure that the PLL only powers up if there is a valid CKREF signal. In a typical application mode, signals of the device do not change other than between the desired frequency range and the power-down mode. This allows for system-level power-down functionality to be implemented via a single wire for a SerDes pair. The S1 and S2 selection signals that have their operating mode driven to a "logic 0" should be hardwired to GND. The S1 and S2 signals that have their operating mode driven to a "logic 1" should be connected to a system-level power-down signal. PLL Multiplier The multiply select pin PLLx_SEL determines whether the PLL multiplication factor is 7 times the CKREF frequency or 7-1/3 times the CKREF frequency. Overclocking the PLL increases the range of spread spectrum on the CKREF input clock that can be tolerated. Both of the PLL multiplier modes can work with a nonspread spectrum clock. When operating with the standard 7x multiplier and operating in a CKREF = STROBE mode, the serialized word is 14 data bits long. Each deserializer output period has the same period of the STROBE signal. When operating in the overclocking mode, the average deserializer period is the same as the STROBE signal. The individual periods vary between 14 and 16 data bits long. The pattern repeats every three cycles with two 14-bit cycles, followed by a third 16-bit cycle. The last two bits in the 16-bit cycle are zero. The deserializer out- Table 1. Control Logic Circuitry Mode Number 0 1 PLLx_SEL X 1 0 X 1 S2 0 0 0 0 1 1 1 1 1 1 S1 0 1 1 1 0 0 0 1 1 1 DIRI X 1 1 0 1 1 0 1 1 0 Power-Down Mode Description 12-Bit Serializer, Standard Clocking, 20MHz to 40MHz CKREF 12-Bit Serializer, Over-Clocked PLL, 19MHz to 38.2MHz CKREF 12-Bit Deserializer 12-Bit Serializer, Standard Clocking, 5MHz to 14MHz CKREF 12-Bit Serializer, Over-Clocked PLL, 4.7MHz to 13.3MHz CKREF 12-Bit Deserializer 12-Bit Serializer, Standard Clocking, 8MHz to 28MHz CKREF 12-Bit Serializer, Over-Clocked PLL, 9.5MHz to 26.7MHz CKREF 12-Bit Deserializer 2 0 X 1 3 0 X (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 4 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges Serializer Operation Mode The serializer configurations are described in the following sections. The basic serialization circuitry works similarly in these modes, but the actual data and clock streams differ, dependent on whether CKREF is the same as the STROBE signal. When it is stated that CKREF = STROBE, the CKREF and STROBE signals have an identical frequency of operation, but may or may not be phase aligned. When it is stated that CKREF does not equal STROBE, each signal is distinct and CKREF must be running at a frequency high enough to avoid any loss of data condition. CKREF must never be a lower frequency than STROBE. Serializer Operation: (Figure 3) Modes 1, 2, 3 DIRI = 1, CKREF = STROBE The PLL must receive a stable CKREF signal to achieve lock prior to any valid data being sent. During the PLL phase, STROBE should not be connected to the CKREF signal. Once the PLL is stable and locked, the device can begin to capture and serialize data. Data is captured on the rising edge of the STROBE signal and serialized. The serialized data stream is synchronized and sent source synchronously with a bit clock with an embedded word boundary. When operating in this mode, the internal deserializer circuitry is disabled, including the DS input buffer. The CKSI serial inputs remain active to allow the pass through of the CKSI signal to the CKP output. For more on this mode, please see the section on Passing a Word Clock. If this mode is not needed, the CKSI inputs can either be driven to valid levels or left to float. For lowest power operation, let the CKSI inputs float. WORD n WORD n+1 DP[1:12] CKREF/STROBE DSO CKSO WORD n-1 b12 b13 b14 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b1 b2 b3 WORD n-2 WORD n-1 WORD n Figure 3. Serializer Timing Diagram (CKREF = STROBE) Serializer Operation: (Figure 4) DIRI = 1, CKREF does not = STROBE If the same signal is not used for CKREF and STROBE, the CKREF signal must be run at a higher frequency than the STROBE rate to serialize the data correctly. The actual serial transfer rate remains at 14 times the CKREF frequency. A data value of zero is sent when no valid data is present in the serial bit stream. The operation of the serializer otherwise remains the same. The exact frequency that the reference clock needs is dependent upon the stability of the CKREF and STROBE signal. If the source of the CKREF signal implements spread spectrum technology, the minimum frequency of this spread spectrum clock should be used in calculating the ratio of STROBE frequency to the CKREF frequency. Similarly if the STROBE signal has significant cycle-tocycle variation, the maximum cycle-to-cycle time needs to be factored into the selection of the CKREF frequency. CKREF DP[1:12] STROBE DSO CKSO No Data WORD n-1 No Data WORD n b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b1 b2 b3 WORD n-1 WORD n WORD n+1 Figure 4. Serializer Timing Diagram (CKREF does not = STROBE) (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 5 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges Serializer Operation Mode (Continued) Serializer Operation: (Figure 5) DIRI = 1, No CKREF A third method of serialization uses a free-running bit clock on the CKSI signal. This mode is enabled by grounding the CKREF signal and driving the DIRI signal HIGH. At power-up, the device is configured to accept a serialization clock from CKSI. If a CKREF is received, this device enables the CKREF serialization mode. The device remains in this mode even if CKREF is stopped. To re-enable this mode, the device must be powered down and powered back up with "logic 0" on CKREF. CKSI DP[1:12] STROBE DSO CKSO No Data WORD n-1 No Data WORD n b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b1 b2 b3 WORD n-1 WORD n WORD n+1 Figure 5. Serializer Timing Diagram Using Provided Bit Clock (No CKREF) (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 6 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges Deserializer Operation Mode The operation of the deserializer is only dependent upon the data received on the DSI data signal pair and the CKSI clock signal pair. The following two sections describe the operation of the deserializer under two distinct serializer source conditions. References to the CKREF and STROBE signals refer to the signals associated with the serializer device used in generating the serial data and clock signals that are inputs to the deserializer. When operating in this mode, the internal serializer circuitry is disabled, including the parallel data input buffers. If there is a CKREF signal provided, the CKSO serial clock continues to transmit bit clocks. When S1 and S2 are asserted low, all CMOS outputs are driven low at the output of the deserializer. Deserializer Operation: (Figure 6) DIRI = 0 (Serializer Source: CKREF = STROBE) When the DIRI signal is asserted LOW, the device is configured as a deserializer. Data is captured on the serial port and deserializer through use of the bit clock sent with the data. The word boundary is defined in the actual clock and data signal. Parallel data is generated at the time the word boundary is detected. The falling edge of CKP occurs coincident with the data transition. The rising edge of CKP is generated approximately seven bit times later. When no embedded word boundary occurs, no pulse on CKP is generated and CKP remains HIGH. WORD n WORD n+1 b9 b10 b11 b12 b13 b14 b15 b16 b17 WORD n-1 DSI b12 b13 b14 CKSI CKP DP[1:12] WORD n-2 b1 b2 b3 b4 b5 b6 b7 b8 WORD n-1 WORD n Figure 6. Deserializer Timing Diagram (Serializer Source: CKREF equals STROBE) The logical operation of the deserializer remains the same if the CKREF is equal in frequency to the STROBE or at a higher frequency than the STROBE. The actual serial data stream presented to the deserializer differs because it has nonvalid data bits sent between words. The duty cycle of CKP varies based on the ratio of the frequency of the CKREF signal to the STROBE signal. The frequency of the CKP signal is equal to the STROBE frequency. The falling edge of CKP is coincident with data transition. The LOW time of the CKP signal is equal to 1/2 (seven bit times) of the CKREF period. The CKP HIGH time is equal to STROBE period - half of the CKREF period. Figure 7 is representative of a waveform that could be seen when CKREF is not equal to STROBE. If CKREF is significantly faster, additional non-valid data bits occur between data words. WORD n b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 WORD n+1 Deserializer Operation: (Figure 7) PwrDwn = 1 DIRI = 0 (Serializer Source: CKREF does not = STROBE) WORD n-1 DSI CKSI CKP DP[1:12] WORD n-2 ~7 bit times b12 b13 b14 WORD n-1 WORD n Figure 7. Deserializer Timing Diagram (Serializer Source: CKREF does not = STROBE) (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 7 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges Embedded Word Clock Operation The FIN12AC sends and receives serial data source synchronously with a bit clock. The bit clock has been modified to create a word boundary at the end of each data word. The word boundary has been implemented by skipping a low clock pulse. This appears in the serial clock stream as three consecutive bit times where signal CKSO remains HIGH. To implement this scheme, two extra data bits are required. During the word boundary phase, the data toggles either HIGH-then-LOW or LOWthen-HIGH, dependent upon the last bit of the actual data word. Table 2 provides some examples showing the actual data word and the data word with the word boundary bits added. Note that a 12-bit word is extended to 14 bits during serial transmission. Bit 13 and Bit 14 are defined with respect to Bit 12. Bit 13 is always the inversion of Bit 12 and Bit 14 is the same as Bit 12. This ensures that a "0" "1" and a "1" "0" transition always occurs during the embedded-word phase, where CKSO is HIGH. The serializer generates the word boundary data bits and the boundary clock condition and embeds them into the serial data stream. The deserializer looks for the end of the word boundary condition to capture and transfer the data to the parallel port. The deserializer only uses the embedded word boundary information to find and capture the data. These boundary bits are stripped prior to the word being sent out the parallel port. From Deserializer DP[n] To Serializer From Control Figure 8. LVCMOS I/O Differential I/O Circuitry The FIN12AC employs FSC proprietary CTL I/O technology. CTL is a low-power, low-EMI differential swing I/O technology. The CTL output driver generates a constant output source and sink current. The CTL input receiver senses the current difference and direction from the corresponding output buffer to which it is connected. This differs from LVDS, which uses a constant current source output, but a voltage sense receiver. Like LVDS, an input source termination resistor is required to properly terminate the transmission line. The FIN12AC device incorporates an internal termination resistor on the CKSI receiver and a gated internal termination resistor on the DS input receiver. The gated termination resistor ensures proper termination regardless of direction of data flow. The relatively greater sensitivity of the current sense receiver of CTL allows it to work at much lower current drive and a much lower voltage. During power-down mode, the differential inputs are disabled and powered down and the differential outputs are placed in a HIGH-Z state. CTL inputs have an inherent fail-safe capability that supports floating inputs. When the CKSI input pair of the serializer is unused, it can be left floating reliably. Alternately both of the inputs can be connected to ground. CTL inputs should never be connected to VDD. When the CKSO output of the deserializer is unused, it should be allowed to float. LVCMOS Data I/O The LVCMOS input buffers have a nominal threshold value equal to half VDDP . The input buffers are only operational when the device is operating as a serializer. When the device is operating as a deserializer, the inputs are gated off to conserve power. The LVCMOS 3-STATE output buffers are rated for a source / sink current of 2mA at 1.8V. The outputs are active when the DIRI signal is asserted LOW. When the DIRI signal is asserted HIGH, the bi-directional LVCMOS I/Os are in HIGH-Z state. Under purely capacitive load conditions, the output swings between GND and VDDP. Table 2. Word Boundary Data Bits 12-bit Data Words Hex FFFh 555h xxxh xxxh 12-bit Data Word with Word Boundary Hex 2FFFh 1555h 1xxxh 2xxxh Binary 1111 1111 1111b 0101 01010 0101b 0xxx xxxx xxxxb 1xxx xxxx xxxxb Binary 10 1111 1111 1111b 01 0101 0101 0101b 01 0xxx xxxx xxxxb 10 1xxx xxxx xxxxb (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 8 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges From Serializer From Control To Deserializer + - DS+ DSGated Termination (DS Pins Only) + - Figure 9. Bi-Directional Differential I/O Circuitry Phase-Locked Loop (PLL) Circuitry The CKREF input signal is used to provide a reference to the PLL. The PLL generates internal timing signals capable of transferring data at 14 times the incoming CKREF signal. The output of the PLL is a bit clock used to serialize the data. The bit clock is also sent source synchronously with the serial data stream. There are two ways to disable the PLL. The PLL can be disabled by entering the Mode 0 state (S1 = S2 = 0). The PLL disables immediately upon detecting a LOW on both the S1 and S2 signals. When any of the other modes are entered by asserting S1 or S2 HIGH and by providing a CKREF signal, the PLL powers up and goes through a lock sequence. Wait a specified number of clock cycles prior to capturing valid data into the parallel port and applying CKREF to STROBE. When the SerDes chipset transitions from a power-down state (S1, S2 = 0.0) to a powered state (example S1, S2 = 1, 1), CKP on the deserializer transitions LOW for a short duration and returns HIGH. Following this, the signal level of the deserializer at CKP corresponds to the serializer signal levels. An alternate way of powering down the PLL is by stopping the CKREF signal either HIGH or LOW. Internal circuitry detects the lack of transitions and shuts the PLL and serial I/O down. Internal references are not disabled, allowing for the PLL to power-up and re-lock in fewer clock cycles than when exiting Mode 0. When a transition is seen on the CKREF signal, the PLL is reactivated. Application Mode Diagrams Modes 1, 2, 3: Unidirectional Data Transfer CKREF_M PLL BIT CK Gen. + - CKSO + - CKSI Work CK Gen Deserializer Control CKP_S Serializer Control Register DP[1:12]_M Serializer + - DS Register STROBE_M + - Deserializer DP[1:12]_S Master Device Operating as a Serializer DIR = "1" Slave Device Operating as a Deserializer DIR = "0" Figure 10. Simplified Block Diagram for Unidirectional Serializer and Deserializer Figure 10 shows basic operation when a pair of SerDes is configured in an unidirectional operation mode. Master Operation: 1. During power-up, the device is configured as a serializer based on the value of the DIRI signal. 2. The device accepts CKREF_M word clock and generates a bit clock with embedded word boundary. This bit clock is sent to the slave device through the CKSO port. 3. The device receives parallel data on the rising edge of STROBE_M. 4. The device generates and transmits serialized data on the DS signals, which is source synchronous with CKSO. (c) 2006 Fairchild Semiconductor Corporation 5. The device generates an embedded word clock for each strobe signal. Slave Operation: 1. The device is configured as a deserializer at powerup based on the value of the DIRI signal. 2. The device accepts an embedded word boundary bit clock on CKSI. 3. The device deserializes the DS data stream using the CKSI input clock. 4. The device writes parallel data onto the DP_S port and generates the CKP_S only when a valid data word occurs. www.fairchildsemi.com FIN12AC Rev. 1.1.0 9 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges VDD1 2.775 VDD2 Baseband Processor PIXEL_CLK VDDP VDDA CKREF STROBE CKP DATA[7:0] HSYNC VSYNC VDD1 VDDS VDDS VDDA VDDP CKP PIXEL_CLK FIN12AC FIN12AC LCD Display Module CKSO+ CKSODP[8:1] DSO+/DSIDP[9] DSO-/DSI+ DP[10] CKSIDP[12:11] CKSI+ DIRI DIRO S2 S1 STROBE CKREF CKSI+ CKSIDATA[7:0] DSO-/DSI+ DP[8:1] HSYNC DSO+/DSI- DP[9] DP[10] VSYNC CKSODP[12:11] CKSO+ DIRO S2 S1 DIRI PWRDWN Note: VDD1 does not have to equal VDD2. Figure 11. Unidirectional 8-bit RGB Interface (10MHz to 40MHz Operation) VDD1 2.775 VDD2 Baseband Processor Camera Interface MASTER_CLK PIXEL_CLK YUV[7:0] HSYNC VSYNC VDDP VDDA CKREF STROBE CKP VDDS VDDS VDDA VDDP CKP MASTER_CLK PIXEL_CLK FIN12AC FIN12AC CKREF STROBE CMOS Image Sensor CKSO+ CKSODP[8:1] DSO+/DSIDP[9] DSO-/DSI+ DP[10] CKSIDP[12:11] CKSI+ DIRI DIRO S2 S1 CKSI+ CKSIDSO-/DSI+ DP[8:1] DSO+/DSI- DP[9] DP[10] CKSOCKSO+ DP[12:11] DIRO S2 S1 DATA[7:0] HSYNC VSYNC VDD2 DIRI PWRDWN MODE0 MODE1 Note: VDD1 does not have to equal VDD2. Figure 12. Unidirectional 8-bit YUV Sensor with Master Clock on Base (10MHz to 40MHz Operation) (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 10 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges STROBE Pass-Through Mode For some applications, it is desirable to pass a word clock across a differential signal pair in the opposite direction of serialization. The FIN12AC supports this mode of operation. Figure 5 in the application section illustrates how to configure the devices for this mode. The following describes how to enable this functionality. For the deserializer: 1. DIRI = LOW 2. CKREF = LOW 3. Word clock should be connected to the STROBE. This passes the STROBE signal out the CKSO port. For the serializer: 1. Connect CKSO of the deserializer to CKSI of the serializer. 2. CKSI passes the signal to CKP. When PLL-bypass mode is used, the bit clock toggles on the CKP signal. Table 3. Control I/O Mode Number 0 1, 2, 3 1, 2, 3 DIRI x 0 1 DIRO Z 1 0 CKSO Z CKSO = STROBE Serializer Output Bit Clock CKP Z Mode of Operation Power Down Mode: S2 = 0, S1 = 0 Deserializer Deserializer: Any active mode Output STROBE CKSI Serializer: Any active mode Flex Circuit Design Guidelines The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex cable. The following best practices should be used when developing the flex cabling or Flex PCB: Keep all four differential wires the same length. Allow no noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential wires. Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom. Do not place test points on differential serial wires. Use differential serial wires a minimum of 2cm away from the antenna. (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 11 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges Absolute Maximum Ratings The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table defines the conditions for actual device operation. Symbol VDD Supply Voltage All Input/Output Voltage Parameter Min. -0.5 -0.5 Continuous -65 Max. +4.6 +4.6 +150 +150 +260 >3 >15 Unit V V C C C kV kV LVDS Output Short-Circuit Duration TSTG TJ TL Storage Temperature Range Maximum Junction Temperature Lead Temperature (Soldering, 4 seconds) Rating Human Body Model, 1.5k, 100pF ESD All Pins S1, S2, CKSO, CKSI, DSO, DSI, VDDA, VDDS, VDDP (as specified in IEC61000-4-2) Recommended Operating Conditions Symbol VDDA, VDDS Supply Voltage VDDP TA VDDA-PP Supply Voltage Operating Temperature Supply Noise Voltage Parameter Min. 2.5 1.65 -30 Max. 3.3 3.6 +70 100 Unit V V C mVp-p (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 12 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges DC Electrical Characteristics Over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol LVCMOS I/O VIH VIL VOH Parameter Input High Voltage Input Low Voltage Output High Voltage Test Conditions Min. 0.65 x VDDP GND Typ.(2) Max. VDDP 0.35 x VDDP Unit V V IOH = -2.0mA VDDP = 3.3 0.30 VDDP = 2.5 0.20 VDDP = 1.8 0.15 0.75 x VDDP VOL Output Low Voltage IOL = 2.0mA VDDP = 3.3 0.30 VDDP = 2.5 0.20 VDDP = 1.8 0.15 0.25 x VDDP V IIN IODH IODL IOZ IIZ VICM VGO Input Current VIN = 0V to 3.6V VOS = 1.0V, Figure 13 VOS = 1.0V, Figure 13 CKSO, DSO = 0V to VDDS S2 = S1 = 0V CKSI, DSI = 0V to VDDS S2 = S1 = 0V VDDS = 2.775 5% see Figure 14 -5.0 5.0 A Differential I/O Output HIGH Source Current Output LOW Sink Current Disabled Output Leakage Current Disabled Input Leakage Current Input Common Mode Range Input Voltage Ground Off-set Relative to Driver(3) CKSI Internal Receiver Termination Resistor CKSI Internal Receiver Termination Resistor -1.75 0.950 1.0 1.0 VGO + 0.80 0 5.0 5.0 mA mA A A V V RTRM RTRM VID = 50mV, VIC = 925mV, DIRI = 0 | CKSI+ - CKSI- | = VID VID = 50mV, VIC = 925mV, DIRI = 0 | DSI+ - DSI- | = VID 80.0 80.0 100 100 120 120 Notes: 2. Typical values are given for VDD = 2.775V and TA = 25C. Positive current values refer to the current flowing into the device and negative values refer to current flowing out of pins. Voltages are referenced to GROUND unless otherwise specified (except VOD and VOD). 3. VGO is the difference in device ground levels between the CTL driver and the CTL receiver. (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 13 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges Power Supply Currents Symbol IDDA1 IDDA2 IDDS1 IDDS2 IDD_PD IDD_SER1 Parameter VDDA Serializer Static Supply Current VDDA Deserializer Static Supply Current VDDS Serializer Static Supply Current VDDS Deserializer Static Supply Current VDD Power-Down Supply Current IDD_PD = IDDA + IDDS + IDDP 14:1 Dynamic Serializer Power Supply Current(4) IDD_SER1 = IDDA + IDDS + IDDP Test Conditions All DP and Control Inputs at 0V or VDD NOCKREF, S2 = 0, S1 = 1, DIR = 1 All DP and Control Inputs at 0V or VDD NOCKREF, S2 = 0, S1 = 1, DIR = 0 All DP and Control Inputs at 0V or VDD NOCKREF, S2 = 0, S1 = 1, DIR = 1 All DP and Control Inputs at 0V or VDD NOCKREF, S2 = 0, S1 = 1, DIR = 0 S1 = S2 = 0 All Inputs at GND or VDD CKREF = STROBE S2 = H S1 = L DIRI = H See Figure 16 S2 = H S1 = H 5MHz 14MHz 10MHz 28MHz Min. Typ.(4) Max. Unit 437 528 4.4 5.5 1.0 8.5 15.0 9.5 17.0 11.0 17.0 6.5 7.5 7.0 10.0 8.5 11.5 mA A A mA mA A mA S2 = L 20MHz S1 = H 40MHz IDD_DES1 14:1 Dynamic Deserializer Power Supply Current(4) IDD_DES1 = IDDA + IDDS + IDDP CKREF = STROBE S2 = H S1 = L DIRI = L See Figure 16 S2 = H S1 = H 5MHz 14MHz 10MHz 28MHz S2 = L 20MHz S1 = H 40MHz Notes: 4. The worst-case test pattern produces a maximum toggling of internal digital circuits, CTL I/O and LVCMOS I/O with the PLL operating at the reference frequency unless otherwise specified. Maximum power is measured at the maximum VDD values. Minimum values are measured at the minimum VDD values. Typical values are measured at VDD = 2.5V. (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 14 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges AC Electrical Characteristics Characteristics at recommended over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol tTCP Parameter CKREF Clock Period (5MHz - 40MHz) CKREF Frequency Relative to STROBE Frequency CKREF Clock High Time CKREF Clock Low Time LVCMOS Input Transition Time STROBE Pulse Width HIGH/LOW Maximum Serial Data Rate Test Conditions CKREF = STROBE S2=1 S1=0 See Figure 19 S2=1 S1=1 S2=0 S1=1 CKREF does not = STROBE Min. 71.0 35.0 25.0 Typ.(5) T Max. 200 100 50.0 40 14 28 Unit ns Serializer Input Operating Conditions REF S2=1 S1=0 1.1 x S2=1 S1=0 fSTROBE S2=0 S1=1 0.2 0.2 0.5 0.5 MHz tCPWH tCPWL tCLKT tSPWH fMAX T T 90.0 ns ns Mb/s (T x 12)/14 540 196 392 See Figure 19 See Figure 19 CKREF x 14 S2=0 S1=1 S2=1 S1=0 S2=1 S1=1 (T x 4)/14 280 70 140 2.5 2.0 tSTC tHTC tTCCD DP(n) Setup to STROBE DP(n) Hold to STROBE Transmitter Clock Input to Clock Output Delay CKSO Position Relative to DS DIRI = 1 See Figure 8 (f = 5MHz) ns ns Serializer AC Electrical Characteristics DIRI = 1, a=(1/f)/14 CKREF = STROBE, See Figure 22 See Figure 25(6) 23a+1.5 21a+6.5 ns tSPOS tTPLLS0 tTPLLD0 tTPLLD1 tRCOP tRCOL tRCOH -200 200 ps PLL AC Electrical Characteristics Serializer Phase-Lock Loop Stabilization Time PLL Disable Time Loss of Clock PLL Power-Down Time See Figure 21 See Figure 26 See Figure 27(7) 200 30.0 20.0 s s ns Deserializer AC Electrical Characteristics Deserializer Clock Output (CKP OUT) Period CKP OUT Low Time CKP OUT High Time See Figure 20 See Figure 20 (Rising Edge Strobe) Serializer source STROBE = CKREF where a = (1/f)/14(9) See Figure 20 (Rising Edge Strobe) where a = (1/f)/14(9) CL = 5pF See Figure 17 17.8 7a-3 7a-3 T 200 7a+3 7a+3 ns ns ns tPDV tROLH tROHL Data Valid to CKP LOW Output Rise Time (20% to 80%) Output Fall Time (80% to 20%) 7a-3 3.5 3.5 7a+3 7.0 7.0 ns ns ns (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 15 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges Notes: 5. Typical values are given for VDD = 2.775V and TA = 25C. Positive current values refer to the current flowing into device and negative values refer to current flowing out of pins. Voltages are referenced to GROUND unless otherwise specified (except VOD and VOD). 6. Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO). Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid. 7. The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies dependent upon the operating mode of the device. 8. Signals are transmitted from the serializer source synchronously. Note that, in some cases, data is transmitted when the clock remains at a HIGH state. Skew should only be measured when data and clock are transitioning at the same time. Total measured input skew would be a combination of output skew from the serializer, load variations, and ISI and jitter effects. 9. Rising edge of CKP appears approximately 13 bit times after the falling edge of the CKP output. Falling edge of CKP occurs approximately 8 bit times after a data transition or 6 bit times after the falling edge of CKSO. Variation of the data with respect to the CKP signal is due to internal propagation delay differences of the data and CKP path and propagation delay differences on the various data pins. Note that if the CKREF is not equal to STROBE for the serializer, the CKP signal does not maintain a 50% duty cycle.The low time of CKP remains 13 bit times. Control Logic Timing Controls Symbol tPHL_DIR, tPLH_DIR tPLZ, tPHZ tPZL, tPZH tPLZ, tPHZ tPZL, tPZH tPLZ, tPHZ tPZL, tPZH Parameter Propagation Delay DIRI-to-DIRO Propagation Delay DIRI-to-DP Propagation Delay DIRI-to-DP Deserializer Disable Time S0 or S1 to DP Deserializer Enable Time S0 or S1 to DP Serializer Disable Time S0 or S1 to CKSO, DS Serializer Enable Time S0 or S1 to CKSO, DS Test Conditions DIRI LOW-to-HIGH or HIGH-to-LOW DIRI LOW-to-HIGH DIRI HIGH-to-LOW DIRI = 0, S1(2) = 0 and S2(1) = LOW-to-HIGH Figure 29 DIRI = 0, S1(2) = 0 and S2(1) = LOW-to-HIGH Figure 29(10) DIRI = 1, S1(2) = 0 and S2(1) = HIGH-to-LOW Figure 28 DIRI = 1, S1(2) and S2(1) = LOW-to-HIGH Figure 28 Min. Typ. Max. Units 17.0 25.0 25.0 25.0 2.0 25.0 65.0 ns ns ns ns s ns ns Notes: 10. Serializer enable time includes the amount of time required for internal voltage and current references to stabilize. This time is significantly less than the PLL lock time and does not limit overall system startup time. Capacitance Symbol CIN CIO CIO-DIFF Parameter Test Conditions Min. Typ. Max. Units 2.0 2.0 2.0 pF pF pF Capacitance of Input Only Signals, CKREF, DIRI = 1, S1 = 0, S2=0, STROBE, S1, S2, DIRI VDD = 2.5V Capacitance of Parallel Port Pins DP[1:12] Capacitance of Differential I/O Signals DIRI = 1, S1 = 0, S2=0, VDD = 2.5V DIRI = 1, S2=0, S1 = 0, VDD = 2.5V (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 16 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges AC Loading and Waveforms DS+ RL/2 Input RL/2 DSVOS VOD DUT + - 100 Termination DUT + - + - VGO Figure 13. Differential CTL Output DC Test Circuit Figure 14. CTL Input Common Mode Test Circuit T DP[1:12] CKREF CKS0CKS0+ DS+ DSb13 b14 b1 0 b2 1 b6 0 b7 1 b8 0 b11 0 b12 1 b1 1 b2 0 b6 1 b7 0 b8 1 b11 1 b12 0 b1 b2 666h 999h 666h Note: The Worst Case test pattern produces a maximum toggling of internal digital circuits, CTL I/O and LVCMOS I/O with the PLL operating at the reference frequency unless otherwise specified. Maximum power is measured at the maximum VDD values. Minimum values are measured at the minimum VDD values. Typical values are measured at VDD = 2.5V. Figure 15. "Worst Case" Serializer Test Pattern tTLH VDIFF 20% 80% 80% tTHL 20% tROLH 80% DPn 20% 80% tROHL 20% VDIFF = (DS+) - (DS-) + - DPn 5pF 1000 DS+ 5 pF DS100 Figure 16. CTL Output Load and Transition Times Figure 17. LVCMOS Output Load and Transition Times AC Loading and Waveforms (Continued) (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 17 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges Setup Time STROBE DP[1:12] tSTC tCLKT 90% Data tHTC tCLKT 90% 10% tTCP CKREF 50% VIH VIL tCPWH tCPWL 10% Hold Time STROBE DP[1:12] Data 50% Setup: MODE0 = "0" or "1", MODE1 = "1", SER/DES = "1" Figure 18. Serial Setup and Hold Time Figure 19. LVCMOS Clock Parameters Data Time CKP DP[1:12] Data tPDV tTPLS0 tRCOP VDD/VDDA 50% 25% tRCOL CKREF 50% 75% tRCOH S1 or S2 CKREF CKS0 Note: CKREF Signal is free running. Setup: DIRI = "0", CKSI and DS are valid signals. Figure 20. Deserializer Data Valid Window Time and Clock Output Parameters Figure 21. Serializer PLL Lock Time tTCCD STROBE CKS0CKS0+ Note: STROBE = CKREF VDD/2 VDIFF = 0 tRCCD CKSICKSI+ CKP VDIFF = 0 VDD/2 Figure 22. Serializer Clock Propagation Delay Figure 23. Deserializer Clock Propagation Delay (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 18 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges AC Loading and Waveforms (Continued) tS_DS CKSICKSI+ DSI+ DSIVDIFF=0 tH_DS CKSOCKSO+ DSO+ DSO- VDIFF = 0 VDIFF = 0 VID / 2 VDIFF=0 VID/2 tSPOS Figure 25. Differential Output Signal Skew Figure 24. Differential Input Setup and Hold Times tTPPLD0 CKREF tTPPLD1 S1 or S2 CKS0 Figure 27. PLL Power-Down Time CKS0 Note: CKREF Signal can be stopped either High or LOW. Figure 26. PLL Loss of Clock Disable Time tPLZ(HZ) S1 or S2 DS+,CKS0+ DS-,CKS0- tPZL(ZH) tPLZ(HZ) S1 or S2 tPZL(ZH) HIGHZ DP Note: If S1(2) transitioning, then S2(1) must = 0 for test to be valid. Note: CKREF must be active and PLL must be stable. Figure 28. Serializer Enable and Disable Time Figure 29. Deserializer Enable and Disable Times (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 19 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges Tape and Reel Specification BGA Embossed Tape Dimension Dimensions are in millimeters. T P0 D P2 E F K0 Wc B0 W Tc A0 P1 D1 User Direction of Feed Package 3.5 x 4.5 A0 0.1 TBD B0 0.1 TBD D 0.05 1.55 D1 Min. 1.5 E 0.1 1.75 F 0.1 5.5 K0 0.1 1.1 P1 Typ. 8.0 P0 Typ. 4.0 P2 0/05 2.0 T Typ. 0.3 TC 0.005 0.07 W 0.3 12.0 WC Typ. 9.3 Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement requirements (see sketches A, B, and C). Shipping Reel Dimension Dimensions are in millimeters. 10 maximum Typical component cavity center line Typical component center line A0 Sketch B (Top View) 1.0mm maximum B0 10 maximum component rotation Sketch A (Side or Front Sectional View) 1.0mm maximum Sketch C (Top View) Component Rotation Component lateral movement Component Rotation W2 max Measured at Hub W1 Measured at Hub B Min Dia C Dia D min Dia A max Dia N DETAIL AA See detail AA W3 Tape Width 8 12 16 Dia A Max. 330 330 330 Dim B Min. 1.5 1.5 1.5 Dia C +0.5/-0.2 13.0 13.0 13.0 Dia D Min. 20.2 20.2 20.2 Dim N Min. 178 178 178 Dim W1 +2.0/-0 8.4 12.4 16.4 Dim W2 Max. 14.4 18.4 22.4 Dim W3 (LSL-USL) 7.9 ~ 10.4 11.9 ~ 15.4 15.9 ~ 19.4 (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 20 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges Tape and Reel Specification (Continued) MLP Embossed Tape Dimension Dimensions are in millimeters. T P0 D P2 E F K0 Wc B0 W Tc A0 P1 D1 User Direction of Feed Package 5x5 6x6 A0 0.1 5.35 6.30 B0 0.1 5.35 6.30 D 0.05 1.55 1.55 D1 Min. 1.5 1.5 E 0.1 1.75 1.75 F 0.1 5.5 5.5 K0 0.1 1.4 1.4 P1 Typ. 8 8 P0 Typ. 4 4 P2 0/05 2.0 2.0 T Typ. 0.3 0.3 TC 0.005 0.07 0.07 W 0.3 12 12 WC Typ. 9.3 9.3 Notes: Ao, Bo, and Ko dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement requirements (see sketches A, B, and C). Shipping Reel Dimensions Dimensions are in millimeters. 10 maximum Typical component cavity center line Typical component center line A0 Sketch B (Top View) 1.0mm maximum B0 10 maximum component rotation Sketch A (Side or Front Sectional View) 1.0mm maximum Sketch C (Top View) Component Rotation Component lateral movement Component Rotation W2 max Measured at Hub W1 Measured at Hub B Min Dia C Dia D min Dia A max Dia N DETAIL AA See detail AA W3 Tape Width 8 12 16 FIN12AC Rev. 1.1.0 Dia A Max. 330 330 330 Dim B Min. 1.5 1.5 1.5 Dia C +0.5/-0.2 13 13 13 Dia D Min. 20.2 20.2 20.2 21 Dim N Min. 178 178 178 Dim W1 +2.0/-0 8.4 12.4 16.4 Dim W2 Max. 14.4 18.4 22.4 Dim W3 (LSL-USL) 7.9 ~ 10.4 11.9 ~ 15.4 15.9 ~ 19.4 www.fairchildsemi.com (c) 2006 Fairchild Semiconductor Corporation FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges Physical Dimensions Dimensions are in millimeters unless otherwise noted. 2X 0.10 C 3.50 2X 0.10 C (0.35) (0.6) 2.5 (0.5) (0.75) TERMINAL A1 CORNER INDEX AREA 4.50 0.5 3.0 0.5 O0.30.05 BOTTOM VIEW X42 0.15 0.05 CAB C (QA CONTROL VALUE) 0.890.082 0.450.05 0.210.04 1.00 MAX 0.10 C C SEATING PLANE 0.08 C 0.230.05 0.2+0.1 -0.0 LAND PATTERN RECOMMENDATION Figure 30. Pb-Free 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 22 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 31. Pb-Free 32-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 5mm Square (c) 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 23 FIN12AC SerDesTM Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges www.fairchildsemi.com (c) 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.0 24 |
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