View FBGA-SD_1238916.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FBGA-SD
Fine Pitch Ball Grid Array - Stacked Die
* FBGA-SD: Laminate substrate based enabling 2 & 4 layers of routing flexibility * FBGA-T-SD: Single metal layer tape based substrate with dense routing & good electrical performance * Available in 1.4mm (LFBGA-SD), 1.2mm (TFBGASD/TFBGA-T-SD), 1.0mm (VFBGA-SD/VFBGA-TSD) & 0.80mm (WFBGA-SD) maximum package thickness * Stacking of die allows for more functionality in an array molded, cost effective, space saving package solution
FEATURES
* 2 die to 7 die stack with spacer capability * 5 x 5mm to 23 x 23mm body size * Package height at 1.0, 1.2, 1.4 and 1.7mm max. * Flexible die stacking options ("pyramid," "same die," etc.) * 0.5mm to 1.0mm ball pitch, Eutectic and Lead-free solder ball * Flash/SRAM/PSRAM/Logic/Analog combinations * JEDEC standard package outlines * Die thinning to 75um (3mils) capability * Low loop wire bonding; reverse and die to die * Up to 2mm die overhang per side * Halogen-free and Low-K wafer compatible BOM * Ball counts up to 450 balls
DESCRIPTION
STATS ChipPAC's Fine Pitch Ball Grid Array Stacked Die (FBGA-SD) offering includes LFBGA-SD, TFBGA-SD, VFBGA-SD and WFBGA-SD packages. Tape versions of VFBGA-SD and TFBGA-SD are also available. STATS ChipPAC's chip stack technology offers the flexibility of stacking 2 to 7 die in a single package. Die to die bonding capability enables device and signal integration to improve electrical performance and reduce overall package I/O requirements. Wafer thinning technology, overhang wire bond technology and the use of spacers between stacked die provide the flexibility to stack almost any desirable configuration of die in one package. This capability uses existing assembly infrastructure, which results in more functional integration with lower overall package cost. The use of the latest packaging materials allows this package to meet JEDEC Moisture Resistance Test Level 2a with Lead-free reflow conditions. This is an ideal package for cell phone applications where Digital, Flash, SRAM, PSRAM and Logic are stacked into a single package.
APPLICATIONS
* Suitable for a variety of applications including memory integration (ASIC or Logic) * Chipset integration (Analog/Digital), mixed technologies integration (Baseband/RF) * Handheld products (Cellular Phones, Pagers, MP3 Players, GPS) * Consumer electronics (Internet applications, Digital Cameras/Camcorders) * Computers (Network PCs) * PC peripherals (Disk Drivers, DC-R/RW, Mini Disk, DVD Drivers)
www.statschippac.com
FBGA-SD
Fine Pitch Ball Grid Array - Stacked Die
SPECIFICATIONS
Die Thickness Mold Cap Thickness Marking Packing Options 75-165m (3-6.5 mils) 0.45-0.9mm Laser JEDEC tray/tape and reel
RELIABILITY
Moisture Sensitivity Level Temperature Cycling High Temperature Storage Pressure Cooker Test Temperature/Humidity Test Unbiased HAST JEDEC Level 2A, 260C reflow Condition C (-65C to 150C, 1000 cycles 150C, 1000 hrs 121C/100% RH/2 atm, 168 hrs 85C/85% RH, 1000 hrs 130C/85% RH, 2 atm, 96 hrs
ELECTRICAL PERFORMANCE
Electrical parasitic data is highly dependent on the package layout. 3D electrical simulation can be used on the specific package design to provide the best prediction of electrical behavior. First order approximations can be calculated using parasitics per unit length for the constituents of the signal path. Data below is for a frequency of 100MHz and assumes 1.0 mil gold bonding wire. Conductor Component Wire Net (2L) Total (2L) Wire Net (4L) Total (4L) Length (mm) 2 2-7 4-9 2 2-7 4-9 Resistance (mOhms) 120 34 -119 154 - 239 120 34 - 119 154 - 239 Inductance (nH) 1.65 1.30 - 4.55 2.95 - 6.20 1.65 0.90 - 3.15 2.55 - 4.80 Inductance Mutual (nH) 0.45 - 0.85 0.26 - 2.28 0.71 - 3.13 0.45 - 0.85 0.18 - 1.58 0.63 - 2.43 Capacitance (pF) 0.10 0.25 - 0.95 0.35 - 1.05 0.10 0.35 - 1.10 0.45 - 1.20 Capacitance Mutual (pF) 0.01 - 0.02 0.06 - 0.42 0.07 - 0.44 0.01 - 0.02 0.06 - 0.42 0.07 - 0.44
Note: Net = Total Trace Length + Via + Solder Ball.
CROSS-SECTION
Die Mold compound
PACKAGE CONFIGURATIONS
Package Type LFBGA-SD TFBGA-SD VFBGA-SD WFBGA-SD TFBGA-T-SD VFBGA-T-SD Pkg Thickness (typical) mm Body Size (mm) Ball Count Ball Pitch (mm)
1.7, 1.4 max Range: 4x4 ~ 23x23 1.2 max Common Sizes: 5x10, 7x9, 8x10, 40-450 1.0 max 8x11, 8x14, 10x12, 10x14, 0.8 max 13x13, 15x15, 16x16, 17x17 1.2 max 1.0 max 4x4 ~ 16x16 40-280
0.5 - 0.8
0.5 - 0.8
Substrate Wire bonds Solder balls 2 die
5 die
(3 functional die + 2 spacer die)* (4 functional die + 1 spacer die)
3 die
(2 functional die + 1 spacer die)
6 die
(4 functional die + 2 spacer die)* (5 functional die +1 spacer die)
4 die
(3 functional die + 1 spacer die)
7 die
(4 functional die + 3 spacer die)* (5 functional die + 2 spacer die) * Shown in illustration.
Corporate Office 10 Ang Mo Kio St. 65, #05-17/20 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823 Global Offices USA 510-979-8000 JAPAN 81-3-5789-5850 CHINA 86-21-5976-5858 MALAYSIA 603-4257-6222 KOREA 82-31-639-8911 TAIWAN 886-3-593-6565 UK 44-1483-413-700 NETHERLANDS 31-38-333-2023
The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Ltd. All other product names and other company names herein are for identification purposes only and may be the trademarks or registered trademarks of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document. STATS ChipPAC reserves the right to change the information at any time and without notice.
(c)Copyright 2006. STATS ChipPAC Ltd. All rights reserved. May 2006

▲Up To Search▲

Price & Availability of FBGA-SD

	To Download FBGA-SD Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .