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Low Voltage, CMOS Multimedia Switch ADG790
FEATURES
Single-chip audio/video/data switching solution Wide bandwidth section Rail-to-rail signal switching capability Compliant with full speed USB 2.0 signaling (3.6 V p-p) Compliant with high speed USB 2.0 signaling (400 mV p-p) Supports USB data rates up to 480 Mbps 550 MHz, 3 dB bandwidth Low RON: 5.9 typical Excellent matching between channels Low distortion section Low RON: 3.9 typical 230 MHz, 3 dB bandwidth (SPDT) 160 MHz, 3 dB bandwidth (4:1 multiplexers) Single-supply operation: 1.65 V to 3.6 V Typical power consumption: <0.1 W Pb-free packaging: 30-ball WLCSP (3 mm x 2.5 mm)
FUNCTIONAL BLOCK DIAGRAM
ADG790
WIDE BANDWIDTH SECTION LOW DISTORTION SECTION S5A S5B S1A S1B D1 S2A S2B D2 S3A S3B D3 S5C S5D D5 S6A S6B S6C S6D D6 S4A S4B D4 DECODER
06357-001
APPLICATIONS
Cellular phones PMPs MP3 players Audio/video/data/USB switching
VDD
IN1
IN2
IN3
S/D GND
Figure 1.
GENERAL DESCRIPTION
The ADG790 is a single-chip, CMOS switching solution that comprises four SPDT switches and two 4:1 multiplexers. The internal architecture of the device provides two switching sections, a wide bandwidth section and a low distortion section. The wide bandwidth section contains three SPDT switches that exhibit low on resistance with excellent flatness and channel matching. This, combined with wide bandwidth, makes the three-SPDT-switch configuration ideal for high frequency signals, such as full speed (12 Mbps) and high speed (480 Mbps) USB signals and high resolution video signals. The low distortion section contains a single SPDT switch and two 4:1 multiplexers that exhibit very low on resistance and excellent flatness, making these switches ideal for a wide range of applications, including low distortion audio applications and low resolution video (CVBS and S-Video) applications. All switches conduct equally well in both directions when on and block signals up to the supply rails when off. A 4-wire parallel interface controls the operation of the device and allows the user to control switches from both sections simultaneously. This simplifies the design and provides a cost-effective, single-chip switching solution for portable devices where multiple signals share a single port connector. The shutdown (S/D) pin allows the user to disable all four SPDT switches and force the 4:1 multiplexers into the S5B and S6B positions, respectively. The ADG790 is packaged in a compact, 30-ball WLCSP (6 x 5 ball array) with a total area of 7.5 mm2 (3 mm x 2.5 mm). This tiny package size and its low power consumption make the ADG790 an ideal solution for portable devices.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
ADG790 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Terminology ...................................................................................... 7 Typical Performance Characteristics ............................................. 8 Test Circuits..................................................................................... 11 Theory of Operation ...................................................................... 13 Wide Bandwidth Section........................................................... 13 Low Distortion Section.............................................................. 13 Control Interface ........................................................................ 13 Evaluation Board ............................................................................ 14 Using the ADG790 Evaluation Board ..................................... 14 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17
REVISION HISTORY
1/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG790 SPECIFICATIONS
VDD = 2.7 V to 3.6 V, GND = 0 V, TA = -40C to +85C, all switch sections unless otherwise noted. Table 1.
Parameter ANALOG SWITCH Analog Signal Range On Resistance Symbol Test Conditions/Comments Min 0 RON VDD = 2.7 V, VS = 0 V to VDD, IDS = 10 mA (see Figure 18) Wide bandwidth section 2 Low distortion section 3 VDD = 2.7 V, VS = 0 V to VDD, IDS = 10 mA (see Figure 18) Wide bandwidth section2 Low distortion section3 VDD = 2.7 V, VS = 0 V to VDD, IDS = 10 mA Wide bandwidth section2 Low distortion section3 (SPDT) Low distortion section3 (4:1 multiplexers) LEAKAGE CURRENTS Source Off Leakage Channel On Leakage DIGITAL INPUTS (IN1, IN2, IN3, S/D) Input High Voltage Input Low Voltage Input High/Input Low Current Digital Input Capacitance DYNAMIC CHARACTERISTICS 5 tON tOFF Propagation Delay IS (OFF) ID, IS (ON) VINH VINL IINL, IINH CIN tON tOFF tD VDD = 3.6 V, VS = 0 V or 3.6 V, VD = 3.6 V or 0 V (see Figure 19) VDD = 3.6 V, VS = VD = 0 V or 3.6 V (see Figure 20) 2.0 VIN = VINL or VINH 0.005 6 20 9 0.3 0.65 0.4 20 40 11 -0.57 6.2 -74 -77 1.2 0.65 550 230 160 0.07 0.08 0.18 0.8 0.1 5.9 3.9 2.0 0.74 Typ 1 Max VDD 8.8 5.5 3.6 1.6 Unit V
On Resistance Flatness
RFLAT(ON)
On Resistance Matching Between Channels 4
RON
0.52 0.1 0.3

10 10
nA nA V V A pF ns ns ns ns ns ps ps ns pC pC dB dB % % MHz MHz MHz % % %
Propagation Delay Skew
tSKEW
Break-Before-Make Time Delay Charge Injection
tBBM QINJ
Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion
THD + N
-3 dB Bandwidth
Differential Gain Error
RL = 50 , CL = 35 pF, VS = VDD/2 or 0 V (see Figure 24) RL = 50 , CL = 35 pF, VS = VDD/2 or 0 V (see Figure 24) RL = 50 , CL = 35 pF Wide bandwidth section2 Low distortion section3 (SPDT) Low distortion section3 (4:1 multiplexers) RL = 50 , CL = 35 pF Wide bandwidth section2 Low distortion section3 (4:1 multiplexers) RL = 50 , CL = 35 pF, VS1 = VS2 = VDD/2 (see Figure 25) VS = 0 V, RS = 0 , CL = 1 nF (see Figure 26) Wide bandwidth section2 Low distortion section3 RL = 50 , CL = 5 pF, f = 1 MHz (see Figure 21) RL = 50 , CL = 5 pF, f = 1 MHz (see Figure 22) RL = 32 , f = 20 Hz to 20 kHz, VS = 2 V p-p Wide bandwidth section2 Low distortion section3 RL = 50 , CL = 5 pF (see Figure 23) Wide bandwidth section2 Low distortion section3 (SPDT) Low distortion section3 (4:1 multiplexers) CCIR330 test signal Wide bandwidth section2 Low distortion section3 (SPDT) Low distortion section3 (4:1 multiplexers)
Rev. 0 | Page 3 of 20
32 15 0.46 0.95 0.65
5
ADG790
Parameter Differential Phase Error Symbol Test Conditions/Comments CCIR330 test signal Wide bandwidth section2 Low distortion section3 (SPDT) Low distortion section3 (4:1 multiplexers) f= 10 kHz, no decoupling capacitors Wide bandwidth section2 Low distortion section3 Wide bandwidth section2 Low distortion section3 (SPDT) Wide bandwidth section2 Low distortion section3 (SPDT) Low distortion section3 (4:1 multiplexers) Min Typ 1 0.13 0.08 0.19 -90 3.5 11 5.5 14 8.5 19 32 1.65 VDD = 3.6 V, digital inputs tied to 0 V or 3.6 V 0.1 3.6 1 Max Unit Degrees Degrees Degrees dB pF pF pF pF pF pF pF V A
Power Supply Rejection Ratio Source Off Capacitance Drain Off Capacitance Source/Drain On Capacitance
PSRR CS (OFF) CD (OFF) CD, CS (ON)
POWER REQUIREMENTS Supply Voltage Supply Current
1 2
VDD IDD
All typical values are at TA = 25C, VDD = 3.3 V. Refers to all switches connected to Pin D1, Pin D2, and Pin D3. 3 Refers to all switches connected to Pin D4 (SPDT), Pin D5, and Pin D6 (4:1 multiplexers). 4 Refers to the on resistance matching between the same channels (SxA and SxB, for example) from different multiplexers for the wide bandwidth section and the 4:1 multiplexers from the low distortion section. For the SPDT switch from the low distortion section, it refers to the matching between the S4A and S4B channels. 5 Guaranteed by design; not subject to production test.
Rev. 0 | Page 4 of 20
ADG790 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 2.
Parameter VDD to GND Analog and Digital Pins1 Peak Current, S or D Continuous Current, S or D Operating Temperature Range Storage Temperature Range Junction Temperature Thermal Impedance (JA)2 Reflow Soldering (Pb Free) Peak Temperature Time at Peak Temperature
1
Rating -0.3 V to +4.6 V -0.3 V to VDD + 0.3 V or 10 mA, whichever occurs first 100 mA (pulsed at 1 ms, 10% duty cycle maximum) 30 mA -40C to +85C -65C to +125C 150C 80C/W 260C (+0C/-5C) As per JEDEC J-STD-20
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
Overvoltages at IN, S, or D are clamped by internal diodes. Limit current to the maximum ratings given. 2 Measured with the device soldered on a 4-layer board.
Rev. 0 | Page 5 of 20
ADG790 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1 CORNER 1 A B C D E F S1A D1 S1B S2B D2 S2A 2 S5A S5B GND GND S6B S6A 3 D5 IN1 IN2 IN3 S/D D6 4 S5C S5D VDD GND S6D S6C 5 S4A D4 S4B S3B D3 S3A
06357-002
TOP VIEW (BALL SIDE DOWN) Not to Scale
Figure 2. 30-Ball WLCSP (CB-30-1)
Table 3. Pin Function Descriptions
Ball Name A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C2 C3 C4 C5 D1 D2 D3 D4 D5 E1 E2 E3 E4 E5 F1 F2 F3 F4 F5 Mnemonic S1A S5A D5 S5C S4A D1 S5B IN1 S5D D4 S1B GND IN2 VDD S4B S2B GND IN3 GND S3B D2 S6B S/D S6D D3 S2A S6A D6 S6C S3A Description Source Terminal for Mux 1 (Wide Bandwidth Section). Can be an input or an output. Source Terminal for Mux 5 (Low Distortion Section). Can be an input or an output. Drain Terminal for Mux 5 (Low Distortion Section). Can be an input or an output. Source Terminal for Mux 5 (Low Distortion Section). Can be an input or an output. Source Terminal for Mux 4 (Low Distortion Section). Can be an input or an output. Drain Terminal for Mux 1 (Wide Bandwidth Section). Can be an input or an output. Source Terminal for Mux 5 (Low Distortion Section). Can be an input or an output. Logic Control Input. Source Terminal for Mux 5 (Low Distortion Section). Can be an input or an output. Drain Terminal for Mux 4 (Low Distortion Section). Can be an input or an output. Source Terminal for Mux 1 (Wide Bandwidth Section). Can be an input or an output. Ground (0 V) Reference. Logic Control Input. Most Positive Power Supply Terminal. Source Terminal for Mux 4 (Low Distortion Section). Can be an input or an output. Source Terminal for Mux 2 (Wide Bandwidth Section). Can be an input or an output. Ground (0 V) Reference. Logic Control Input. Ground (0 V) Reference. Source Terminal for Mux 3 (Wide Bandwidth Section). Can be an input or an output. Drain Terminal for Mux 2 (Wide Bandwidth Section). Can be an input or an output. Source Terminal for Mux 6 (Low Distortion Section). Can be an input or an output. Shutdown Logic Control Input. Source Terminal for Mux 6 (Low Distortion Section). Can be an input or an output. Drain Terminal for Mux 3 (Wide Bandwidth Section). Can be an input or an output. Source Terminal for Mux 2 (Wide Bandwidth Section). Can be an input or an output. Source Terminal for Mux 6 (Low Distortion Section). Can be an input or an output. Drain Terminal for Mux 6 (Low Distortion Section). Can be an input or an output. Source Terminal for Mux 6 (Low Distortion Section). Can be an input or an output. Source Terminal for Mux 3 (Wide Bandwidth Section). Can be an input or an output.
Rev. 0 | Page 6 of 20
ADG790 TERMINOLOGY
IDD Positive supply current. VD (VS) Analog voltage on Terminal D and Terminal S. RON Ohmic resistance between Terminal D and Terminal S. RFLAT (ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured. RON On resistance match between any two channels. IS (OFF) Source leakage current with the switch off. ID, IS (ON) Channel leakage current with the switch on. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. CS (OFF) Off switch source capacitance. Measured with reference to ground. CD, CS (ON) On switch capacitance. Measured with reference to ground. CIN Digital input capacitance. tON Delay time between the 50% and the 90% points of the digital input and switch on condition. tOFF Delay time between the 50% and the 10% points of the digital input and switch off condition. tBBM On or off time measured between the 80% points of both switches when switching from one to the other. tD Signal propagation delay through the switch measured between the 50% points of the input signal and its corresponding output signal. tSKEW Difference in propagation delay between the selected inputs on the 4:1 multiplexers or any two SPDT switches from the wide bandwidth section. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during on-off switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. -3 dB Bandwidth The frequency at which the output is attenuated by 3 dB. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonic amplitudes plus signal noise to the fundamental. Differential Gain Error The measure of how much color saturation shift occurs when the luminance level changes. Both attenuation and amplification can occur; therefore, the largest amplitude change between any two levels is specified and expressed in percent. Differential Phase Error The measure of how much hue shift occurs when the luminance level changes. It can be a negative or a positive value and is expressed in degrees of subcarrier phase.
Rev. 0 | Page 7 of 20
ADG790 TYPICAL PERFORMANCE CHARACTERISTICS
7.5 7.0 6.5 6.0 5.5 5.0 4.5 VDD = 3.6V 4.0 0 0.5 1.0 1.5 2.0 VS (V) 2.5 3.0 3.5 VDD = 3.3V TA = 25C IDS = 10mA
4.5 4.3 4.1
VDD = 2.7V
VDD = 3.3V IDS = 10mA
3.9 3.7
RON ()
RON ()
3.5 3.3 3.1 2.9 TA = +85C
06357-039
2.7 2.5 0 0.5
TA = -40C 1.0 1.5 VS (V) 2.0
2.5
3.0
Figure 3. On Resistance vs. Source Voltage, Wide Bandwidth Section
6.5 VDD = 3.3V IDS = 10mA 6.0
20 18 16
Figure 6. On Resistance vs. Temperature, Low Distortion Section
tOFF
tON/tOFF (ns)
5.5
RON ()
14 12 10 8
5.0
TA = +85C
4.5
06357-040
tON
TA = -40C 4.0 0 0.5 1.0 1.5 VS (V) 2.0 2.5 3.0
4 -40
-20
0
20
40
60
80
TEMPERATURE (C)
Figure 4. On Resistance vs. Temperature, Wide Bandwidth Section
Figure 7. tON/tOFF Times vs. Temperature
4.5
VDD = 2.7V
TA = 25C IDS = 10mA
-1 -3
ATTENUATION (dB)
VDD = 3.3V TA = 25C
WIDE BANDWIDTH SECTION LOW DISTORTION SECTION
4.0
RON ()
-5 -7 -9 -11
3.5 VDD = 3.3V 3.0
06357-041
2.5
0
0.5
1.0
1.5
2.0 VS (V)
2.5
3.0
3.5
-15 0.01
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 5. On Resistance vs. Source Voltage, Low Distortion Section
Figure 8. On Response vs. Frequency, Low Distortion Section (SPDT)
Rev. 0 | Page 8 of 20
06357-029
VDD = 3.6V
-13
06357-028
TA = +25C
6
VDD = 3.3V TA = 25C RL = 50 CL = 35pF
06357-042
TA = +25C
ADG790
0 -2 -4 VDD = 3.3V TA = 25C
-10 -20 -30 VDD = 3.3V TA = 25C WIDE BANDWIDTH AND LOW DISTORTION SECTIONS
ATTENUATION (dB)
-6 -8 -10 -12 -14 -16 -18 -20 0.01 0.1 1 10 100
06357-030
ATTENUATION (dB)
-40 -50 -60 -70 -80 -90 -100 -110 0.0001 0.001 0.01 0.1 1 10 100
06357-033
1000
FREQUENCY (MHz)
1000
FREQUENCY (MHz)
Figure 9. On Response vs. Frequency, Low Distortion Section (4:1 Multiplexers)
-20
Figure 12. Off Isolation vs. Frequency
ATTENUATION (dB)
VDD = 3.3V -30 TA = 25C WIDE BANDWIDTH AND LOW DISTORTION SECTIONS -40 INPUT SIGNAL = 0dBm DC BIAS = 0.5V -50 -60 -70 -80 -90 -100 -110
06357-034
06357-021
-120 0.0001
0.001
0.01
0.1
1
10
100
1000
X = 20ns/DIV Y = 835mV/DIV
FREQUENCY (MHz)
Figure 10. USB 1.1 Eye Diagram
1.3 1.2
Figure 13. Crosstalk vs. Frequency
WIDE BANDWIDTH SECTION 1.1 1.0 0.9 0.8 0.7
06357-035
THD + N (%)
VDD = 3.3V RL = 32 VS = 2V p-p TA = 25C DC BIAS = 1.65V
0.6
06357-022
LOW DISTORTION SECTION
0.5 10
100
1000 FREQUENCY (Hz)
10000
100000
X = 250ps/DIV Y = 100mV/DIV
Figure 11. USB 2.0 Eye Diagram
Figure 14. THD + N vs. Frequency
Rev. 0 | Page 9 of 20
ADG790
500 450 400 350
PSRR (dB)
IDD (A)
VDD = 3.3V TA = 25C
0
-20
-40
300 250 200 150 100
06357-036
VDD = 3.3V TA = 25C WIDE BANDWIDTH AND LOW DISTORTION SECTIONS. 0dBm SIGNAL SUPERIMPOSED ON SUPPLY VOLTAGE. NO DECOUPLING CAPACITORS USED.
-60
-80
-100
06357-038
50 0 0 0.5 1.0 1.5 VIN (V) 2.0 2.5 3.0
-120 0.0001
0.001
0.01
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 15. Supply Current vs. Input Logic Level
8 7 6 5
QINJ (pC)
Figure 17. Power Supply Rejection Ratio vs. Frequency
LOW DISTORTION SECTION
4 3 2 1
06357-037
VDD = 3.3V CL = 1nF TA = 25C
WIDE BANDWIDTH SECTION
0 -1
0
0.5
1.0
1.5 VS (V)
2.0
2.5
3.0
Figure 16. Charge Injection vs. Source Voltage
Rev. 0 | Page 10 of 20
ADG790 TEST CIRCUITS
VDD
IDS
NETWORK ANALYZER
0.1F
V1 S D
VDD SxA
VOUT
RL 50 50 VS
SxB
Dx
06357-003
VS
RON = V1/IDS
RL 50
GND
Figure 18. On Resistance
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
IS (OFF) A VS ID (OFF) A
06357-004
VOUT VS
S
D
Figure 22. Channel-to-Channel Crosstalk
VDD
VD
0.1F
VDD
NETWORK ANALYZER 50 VS VOUT
Figure 19. Off Leakage
SxB SxA Dx
NC
S
D
ID (ON) A
GND
06357-005
RL 50
VD NC = NO CONNECT
INSERTION LOSS = 20 log
VOUT WITH SWITCH VOUT WITHOUT SWITCH
Figure 20. On Leakage
VDD 0.1F NETWORK ANALYZER 50 VS VOUT
Figure 23. -3 dB Bandwidth
VDD
NC
SxB
SxA Dx
50
GND
RL 50
VS
NC = NO CONNECT
Figure 21. Off Isolation
06357-009
OFF ISOLATION = 20 log
VOUT
Rev. 0 | Page 11 of 20
06357-011
06357-010
ADG790
VDD 0.1F
VDD SxA VS INx GND SxB Dx RL 50 VOUT CL 35pF
VIN 50% 90% VOUT 10% 50%
Figure 24. Switching Times (tON, tOFF)
VDD 0.1F
VDD SxA SxB VS INx Dx RL 50 VOUT CL 35pF
VIN 0V VS VOUT
50% 80%
50% 80%
tBBM
GND
tBBM
06357-007
Figure 25. Break-Before-Make Time Delay (tBBM)
VDD 0.1F
VDD Dx VS SxA SxB NC CL 1nF GND VOUT
SxB TO Dx ON VIN SxB TO Dx OFF VOUT QINJ = CL x VOUT
INx
VOUT
NC = NO CONNECT
Figure 26. Charge Injection
Rev. 0 | Page 12 of 20
06357-008
06357-006
tON
tOFF
ADG790 THEORY OF OPERATION
The ADG790 is a single-chip, CMOS switching solution that comprises four SPDT switches and two 4:1 multiplexers. The internal architecture used by the device groups the switches into two sections, each optimized to provide the best performance in terms of bandwidth and distortion. The on-chip parallel interface controls the operation of all switches, allowing the user to control switches from both sections simultaneously. resistance and flatness while maintaining a wide bandwidth that makes them suitable for a wide range of applications, including low distortion audio and standard definition video signals. The channels from the 4:1 multiplexers are matched to provide optimal performance when used with differential signals such as S-Video.
CONTROL INTERFACE
The operation of the ADG790 is controlled via a 4-wire parallel interface. The logic levels applied to the IN1, IN2, and IN3 pins control the operation of the switches from both the wide bandwidth and low distortion sections, as shown in Table 4. The shutdown pin (S/D) allows the user to disable all four SPDT switches and force the 4:1 multiplexers into the S5B and S6B positions, respectively. This function can be used to set up a low speed communication protocol between the circuitry from both sides of the device, which allows automatic configuration of the switching function. For example, in modern handset applications, where a single connector is used as a multifunction communication port, the S5B-D5 and S6B-D6 configuration obtained by setting the S/D pin high can be used to detect the type of peripheral device connected to the handset. The ADG790 then automatically routes the required signals to the communication port connector.
WIDE BANDWIDTH SECTION
The wide bandwidth section contains three SPDT switches S1A/S1B-D1, S2A/S2B-D2, and S3A/S3B-D3. These switches use a CMOS topology that ensures, besides low on resistance and excellent flatness, the ability to switch signals up to the supply rails. This, combined with the low switch capacitance, provides the wide bandwidth required when switching high frequency signals. The three SPDT switches are also optimized to provide low propagation delay and excellent matching between the channels, making the ADG790 ideal for applications that use multiple signals, such as universal USB switches (full and high speed), or RGB video signals, such as VGA.
LOW DISTORTION SECTION
The low distortion section contains a single SPDT switch (S4A/S4B-D4) and two 4:1 multiplexers (S5A/S5B/S5C/S5D-D5 and S6A/S6B/S6C/S6D-D6, respectively). The switches from this section also use a CMOS topology that exhibits very low on Table 4. Truth Table
Logic Control Inputs S1A-D1 S2A-D2 S3A-D3 S5D-D5 S6D-D6 Off Off On Off Off Off On Off Off
Switch Status
S/D 1 0 0 0 0 0 0 0 0
1
IN1 X1 0 0 0 0 1 1 1 1
IN2 X1 0 0 1 1 0 0 1 1
IN3 X1 0 1 0 1 0 1 0 1
S1B-D1 S2B-D2 S3B-D3 Off On Off On On On Off On On
S4A-D4 Off Off On On On On Off Off Off
S4B-D4 Off On Off Off Off Off On On On
S5A-D5 S6A-D6 Off Off Off Off Off On Off On Off
S5B-D5 S6B-D6 On Off Off On Off Off Off Off On
S5C-D5 S6C-D6 Off On Off Off On Off Off Off Off
X = logic state doesn't matter.
Rev. 0 | Page 13 of 20
ADG790 EVALUATION BOARD
The ADG790 evaluation board allows designers to evaluate the high performance of the device with a minimum of effort. The EVAL-ADG790 includes a printed circuit board populated with the ADG790; it can be used to evaluate the performance of the device. It interfaces to the USB port of a PC, allowing the user to easily program the ADG790 through the USB port using the software provided with the board. Schematics of the evaluation board are shown in Figure 27 and Figure 28. The software runs on any PC that has Microsoft(R) Windows(R) 2000 or Windows(R) XP installed.
USING THE ADG790 EVALUATION BOARD
The ADG790 evaluation board is a test system designed to simplify the evaluation of the device. Each input/output of the part comes with a standardized socket to allow connection to and from USB, CVBS, S-Video, and VGA signal sources. A data sheet for the ADG790 evaluation board is also available with full information on setup and operation.
Rev. 0 | Page 14 of 20
DVDD R6 0 DVDD DVDD DVDD DVDD + C4 2.2F C14 0.1F R9 2.2k R8 2.2k
DVDD
DVDD
R4 100k C3 0.1F
R5 100k
C1 + 10F
3
C2 0.1F
7 11 17 27 32 43 55
U2 CY7C68013-56LFC DVDD 24LC64
1 A0 V CC 2 A1 WP 3 A2 SCL 4 VSS SDA 8 7 6 5
AVCC A0 A1 A2 A3
VCC
18 19 20 21 22 23 24 25 45 46 47 48 49 50 51 52
U3
PB0/FD0 PB1/FD1 PB2/FD2 42 PB3/FD3 44 RESET PB4/FD4 *WAKEUP PB5/FD5 PB6/FD6 54 CLKOUT PB7/FD7 PD0/FD8 29 30 CTL0/*FLAGA PD1/FD9 31 CTL1/*FLAGB PD2/FD10 CTL2/*FLAGC PD3/FD11 PD4/FD12 PD5/FD13 33 PA0/ INT0 PD6/FD14 34 PD7/FD15 35 PA1/ INT1 PA2/*SLOE 36 37 PA3/*WU2 38 PA4/FIFOADR0 SDA 39 PA5/FIFOADR1 SCL PA6/*PKTEND
16 15 40
GND
10 12 26 28 41 53 56
06357-013
Figure 27. EVAL-ADG790 Schematic USB Controller Section
PA7/*FLAGD/SLCS RDY1/*SLWR XTALOUT XTALIN 5 Y1 24MHz GND IO SHIELD D+ D- VBUS DVDD C5 C6 C7 C8 C9 C10 C11 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F USB-MINI-B J14
5 4
Rev. 0 | Page 15 of 20
1 RDY0/*SLRD 2 13 IFCLK 14 RESERVED
5V USB ADP3303AR-3.3
8 IN 7 IN 5 1 2 6 3
DVDD
DMINUS 9 DPLUS 8
OUT OUT SD ERR GND NR +
4 3 2 1 4
+ U4 C16 0.1F C15 10F C17 0.1F
AGND
6
C19 10F C13 12pF
R7 10k
C12 12pF
R10 1k D1 GREEN
ADG790
ADG790
PHONO_DUAL
3
T1 T3 T33 DVDD IO1_I USB2.OID/VGAR_O D1 D2 D3 D4 D5 D6 IO2/VGAV/S-VIDEOC/RX_O IO1/VGAV/S-VIDEOC/RX_O T19 T18 VBUS USB2.OD-/VGAG_O U1 USB2.OD+/VGAB_O
4 3 2 1
J1 TOP
2
T21 T22 T23 VGA R_O J13-1 J13-2 J13-3 T24 T25 J13-13 J13-14 VGA G_O VGA B_O
1
BOTTOM USB2.OD-_I T2 T4 VGAB_I USB2.OD+_I TX_I VGAR_I USBID_I RX_I MIC_I CVBS_I TX_I IO1_I SVIDEOY_I MIC_I RX_I IO2_I T7 T8 SVIDEOC_I VGAV_I VBUS USB2.OD-_I USB2.OD+_I A3 A2 A1 A0 T32 T20 USBID_I T15 USB2.OID/VGAR_O
4
IO2_I C1 F1 D1 F5 D5 A5 C5 A2 B2 A4 B4 F2 E2 F4 E4 S6D IN1 IN2 IN3 S/D B3 C3 D3 E3
6
C2 GND D2 GND D4 GND VDD C4 B1 E1 E5 B5 A3 F3 IO1/VGAH/S-VIDEOY/TX_O IO1/VGAH/S-VIDEOY/TX_O MIC/CVBS_O HSYNC_O VSYNC_O USB2.OID/VGAR_O USB2.OD+/VGAB_O USB2.OD+/VGAB_O USB2.OD-/VGAG_O USB2.OD-/VGAG_O
GND VGAG_I S1B S2A S2B S3A S3B S4A S4B S5A S5B S5C S5D D- D+ GND SH SH J11 USB S6A S6B S6C
5
A1 S1A
PHONO_DUAL
3
J2 TOP
2
1
GND BOTTOM T5 T6 CVBS_I VGAH_I VDD R1 75
PHONO_DUAL
3
J3 TOP
2
J13-4 J13-5 J13-6 J13-7 J13-8
1
GND BOTTOM
ADG790
VDD
1
D-
2
J4 USB
D+
3
USB2.OID PHONO_DUAL
3
GND
4
SH T14 T11 T10 T9
1 2 2 4 1 3
5
06357-014
Figure 28. EVAL-ADG790 Schematic Switch Section
Rev. 0 | Page 16 of 20
J6 SVIDEOC_I SVIDEOY_I R2 75 R3 75 MINI-DIN-4 VGAR_I VGAG_I VGAB_I T13 T12 VGAH_I VGAV_I IO2/VGAV/S-VIDEOC/RX_O IO1/VGAH/S-VIDEOY/TX_O SVIDEOC_O SVIDEOY_O T16 T17
4 3 2 1 4 3 2 1 3
SH
6
J5 TOP
2 1
GND BOTTOM
T26 IO2/VGAV/S-VIDEOC/RX_O IO1/VGAH/S-VIDEOY/TX_O IO2_O IO1_O T28 IO2/VGAV/S-VIDEOC/RX_O J12 MINI-DIN-4 IO1/VGAH/S-VIDEOY/TX_O RX_O TX_O T30 MIC/CVBS_O MIC/CVBS_O MIC_O CVBS_O T31 T29 T27
PHONO_DUAL
2
J7-1
J8 BOTTOM
3 1
J7-2
GND TOP PHONO_DUAL
2
J7-3
J7-13
J9 BOTTOM
3 1
J7-14
GND TOP PHONO_DUAL
2
J7-4
J7-5
J7-6
J10 BOTTOM
3 1
J7-7
J7-8
GND TOP
ADG790 OUTLINE DIMENSIONS
2.56 2.50 2.44 0.65 0.59 0.53 SEATING PLANE
5 4 3 2 1 A
BALL A1 CORNER
3.06 3.00 2.94
0.36 0.32 0.28
B C D
0.50 BALL PITCH
E F
(BALL SIDE DOWN)
(BALL SIDE UP)
Figure 29. 30-Ball Wafer Level Chip Scale Package [WLCSP] (CB-30-1) Dimensions shown in millimeters
ORDERING GUIDE
Model ADG790BCBZ-REEL 1 EVAL-ADG790EBZ1
1
Temperature Range -40C to +85C
Package Description 30-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board
Package Option CB-30-1
Z = Pb-free part.
Rev. 0 | Page 17 of 20
092106- A
TOP VIEW
0.28 0.24 0.20
BOTTOM VIEW
ADG790 NOTES
Rev. 0 | Page 18 of 20
ADG790 NOTES
Rev. 0 | Page 19 of 20
ADG790 NOTES
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06357-0-1/07(0)
Rev. 0 | Page 20 of 20

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