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EM73880 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary Prelim
GENERAL DESCRIPTION
EM73880 is an advanced single chip CMOS 4-bit micro-controller. It contains 8K-byte ROM, 244-nibble RAM, 4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernel function. EM73880 also contains 6 interrupt sources, 1 input port, 2 bidirection ports, LCD display (32x4), and one high speed timer/counter,sound generator, and speech synthesizer. EM73880 has plentiful operating modes (SLOW, IDLE, STOP) intended to reduce the power consumption.
FEATURES
* Operation voltage * Clock source * * * * * * * * * * * * : 2.4V to 3.6V. : Dual clock system. Low-frequency oscillator (32.768 KHz) could be Crystal or RC oscillator high-frequency oscillator is a built-in for 4.6 MHz. Instruction set : 107 powerful instructions. Instruction cycle time : 1.7us for 4.6 MHz (high speed clock). 244 s for 32768 Hz (low speed clock). ROM capacity : 8192 X 8 bits. RAM capacity : 244 X 4 bits. Input port : 1 port (P0). P0(0..3) and IDLE releasing function are available by mask option. Bidirection port : 2 ports (P4, P8). P4.1 is shared with HTC external input. P8(0..3) and IDLE releasing function are available by mask option. 12-bit timer/counter : Two 12-bit timer/counters are programmable for timer, event counter and pulse width measurement. High speed timer/counter : One 8-bit high speed timer/counters is programmable for auto load timer, melody output and pulse width measurement. Speech synthesizer : 160K Speech ROM. Built-in time base counter : 22 stages. Subroutine nesting : Up to 13 levels. Interrupt : External . . . . . 1 input interrupt sources. Internal . . . . . . 2 Timer overflow interrupts, 1 time base interrupt. 1 high speed timer/counter overflow interrupt. 1 Speech ending interrupt. LCD driver : 32 X 4 dots, 1/4,1/3,1/2, static 4 kinds of duty Type selectable, 1/2 bias, 1/3 bias, 2 kinds bias Type selectable. Power saving function : SLOW, IDLE, STOP operation mode. Package type : Chip form. . . . .63 pins.
* * *
APPLICATIONS
EM73880 is suitable for application in family applicance, consumer products, hand held games and the toy controller.
* This specification are subject to be changed without notice.
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FUNCTION BLOCK DIAGRAM
RESET
CLK LXOUT LXIN
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Reset Control
Int. Clock Generator
Clock Generator (slow)
Timing Generator
Clock Mode Control
System Control Data pointer Interrupt Control Time Base Instruction Decoder Instruction Register Stack pointer ACC
Data Bus
ALU Flag Z C S HR
Stack RAM LR P0.0/WAKEUP0 P0.1/WAKEUP1 P0.2/WAKEUP2 P0.3/WAKEUP3
ROM Timer/Counter (TA,TB) PC
VA VB V1 V2 V3
I/O Control
LCD
HTC
Speech Synthesizer
PWM
COM0~COM3
SEG0~SEG31
BZ1
PIN DESCRIPTIONS
Symbol V DD, V DD2 VSS RESET Pin-type Function Power supply (+) / speech synthesizer power supply(+) Power supply (-) RESET-A System reset input signal, low active mask option : none pull-up OSC-G Capacitor connecting pin for internal high frequency OSC. OSC-B/OSC-H Crstal/RC connecting pin for low speed clock source OSC-B Crstal/RC connecting pin for low speed clock source INPUT-K 4-bit input port with IDLE releasing function mask option : wakeup enable, negative edge release, pull-up wakeup enable, negative edge release, none wakeup enable, positive edge release, pull-down wakeup enable, positive edge release, none wakeup disable, pull-up wakeup disable, pull-down wakeup disable, none I/O-R 1-bit bidirection I/O port
CLK LXIN LXOUT P0(0..3)/WAKEUP0..3
P4.0
* This specification are subject to be changed without notice.
P4.0 P4.1/TRGH P4.2 P4.3 P8.0/WAKEUPA P8.1(TRGB)/WAKEUPB P8.2(INT0)/WAKEUPC P8.3(TRGA)/WAKEUPD
BZ2
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PIN DESCRIPTIONS
Symbol P4.1/TRGH Pin-type I/O-Q
inary Prelim
Function 1-bit bidirection I/O port with HTC external input mask option : NMOS open-drain PMOS open-drain low current push-pull normal current push-pull high current push-pull 2-bit bidirection I/O port with high current source mask option : NMOS open-drain PMOS open-drain low current push-pull normal current push-pull high current push-pull 2-bit bidirection I/O port with external interrupt source input only P8.2 and IDLE releasing function mask option : wakeup enable, low current push-pull wakeup enable, normal current push-pull wakeup disable, open-drain wakeup disable, low current push-pull wakeup disable, normal current push-pull 2-bit bidirection I/O port with time/counter A,B external input and IDLE releasing function mask option : wakeup enable, low current push-pull wakeup enable, normal current push-pull wakeup disable, open-drain wakeup disable, low current push-pull wakeup disable, normal current push-pull Speech output pin Connect the capacitors for LCD bias voltage LCD common output pins LCD segment output pins Tie Vss as package type, no connecting as COB type
P4(2,3)
I/O-Q
P8.0/WAKEUPA, P8.2/INT0/WAKEUPC
I/O-S
P8.1(TRGB)/WAKEUPB I/O-S P8.3(TRGA)/WAKEUPD
BZ1, BZ2 VA,VB, V1, V2, V3 COM0~COM3 SEG0~SEG31 TEST
FUNCTION DESCRIPTIONS
PROGRAM ROM (8K X 8 bits) 8 K x 8 bits program ROM contains user's program and some fixed data. The basic structure of program ROM can be divided into 6 parts. 1. Address 000h: Reset start address. 2. Address 002h - 00Ch : 6 kinds of interrupt service routine entry addresses. 3. Address 00Eh-086h : SCALL subroutine entry address, only available at 00Eh,016h,01Eh,026h, 02Eh, 036h, 03Eh, 046h, 04Eh, 056h, 05Eh, 066h, 06Eh, 076h, 07Eh, 086h. 4. Address 000h - 7FFh : LCALL subroutine entry address 5. Address 000h - 1FFFh : Except used as above function, the other region can be used as user's program region. 6. Address 1000h - 1FFFh : Fixed data stortage area.
* This specification are subject to be changed without notice.
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address 000h 002h 004h 006h 008h 00Ah 00Ch 00Eh 086h 800h .
8192 x 8 bits Reset start address INT0; External interrupt service routine entry address HTCI; High speed timer interrupt service entry address TRGA; Timer/counterA interrupt service routine entry address TRGB; Timer/counter B interrupt service routine entry address TBI; Time base interrupt service routine entry address SPI SCALL, subroutine call entry address 1000
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LCALL entry address
. .
FFFh Bank1
fixed data area
1FFF User's program and fixed data are stored in the program ROM. User's program is according the PC value to send next executed instruction code . Fixed data can be read out. The program counter is a 13-bit binary counter. The PC can defined 8K ROM. Table -look-up instruction is depended on the Data Pointer (DP) to indicate to ROM address, then to get the ROM code data. The fixed data only can be put in bank1. LDAX LDAXI Acc ROM[DP]L Acc ROM[DP]H,DP+1
DP is a 12-bit data register which can store the program ROM address to be the pointer for the ROM code data. First, user load ROM address into DP by instruction "STADPL, STADPM, STADPH", then user can get the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI" PROGRAM EXAMPLE: Read out the ROM code of address 1777h by table-look-up instruction.
LDIA #07h; STADPL ; DP2-0 07h STADPM ; DP5-3 07h STADPH ; DP8-6 07h, Load DP=777h : LDL #00h; LDH #03h; LDAX ; ACC 6h STAMI ; RAM[30] 6h LDAXI ; ACC 5h STAM ; RAM[31] 5h ; ORG 1777H DATA 56H; :
DATA RAM ( 244-nibble ) There is total 244 - nibble data RAM from address 00 to F3h Data RAM includes 3 parts: zero page region, stacks and data area.
* This specification are subject to be changed without notice.
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Increment Address 00h~0Fh 10h~1Fh 20h~2Fh 30h~3Fh 40h~4Fh : B0h ~ BFh C0h ~ CFh D0h ~ DFh E0h ~ EFh F0h ~ F3h zero page
LCD display RAM
level 0 level 4 level 8 level C
level 1 level 5 level 9
level 2 level 6 level A
level 3 level 7 level B
LCD display RAM: RAM address from 20h ~ 3Fh are the LCD display RAM area, the RAM data of this region can't be operated by instruction LDHL xx and EXHL. ZERO- PAGE: From 00h to 0Fh is the location of zero-page . It is used as the pointer in zero -page addressing mode for the instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y". PROGRAM EXAMPLE: To wirte immediate data "07h" to address "03h" of RAM and to clear bit 2 of RAM.
STD #07h, 03h ; RAM[03] 07h CLR 0Eh,2 ; RAM[0Eh]2 0
STACK: There are 13 - level (maximum) stack for user using for subroutine (including interrupt and CALL). User can assign any level be the starting stack by giving the level number to stack pointer (SP). When user using any instruction of CALL or subroutine, before entry the subroutine, the previous PC address will be saved into stack until return from those subroutines ,the PC value will be restored by the data saved in stack. DATA AREA: Except the special area used by user, the whole RAM can be used as data area for storing and loading general data. ADDRESSING MODE (1) Indirect addressing mode: Indirect addressing mode indicates the RAM address by specified HL register. For example: LDAM ; Acc RAM[HL]
STAM ; RAM[HL] Acc
(2) Direct addressing mode: Direct addressing mode indicates the RAM address by immediate data.
* This specification are subject to be changed without notice.
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For example: LDA x ; Acc RAM[x]
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STA x ; RAM[x] Acc
(3) Zero-page addressing mode For zero-page region, user can using direct addressing to write or do any arithematic, comparsion or bit manupulated operation directly. For example: STD #k,y ; RAM[y] #k
ADD #k,y; RAM[y] RAM[y] + #k
PROGRAM COUNTER (8K ROM) Program counter ( PC ) is composed by a 13-bit counter, which indicates the next executed address for the instruction of program ROM. For a 8K - byte size ROM, PC can indicate address form 0000h - 1FFFh, for BRANCH and CALL instrcutions, PC is changed by instruction indicating. (1) Branch instruction: SBR a Object code: 00aa aaaa Condition: SF=1; PC PC 11-6.a ( branch condition satisified ) PC
Hold original PC value+1 a
a
a
a
a
a
SF=0; PC PC +1( branch condition not satisified) PC Original PC value + 1
LBR a Object code: 1100 aaaa aaaa aaaa Condition: SF=1; PC a ( branch condition satisified) PC a a a a a a a a a a a a
SF=0 ; PC PC + 2 ( branch condition not satisified ) PC Original PC value + 2
* This specification are subject to be changed without notice.
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(2) Subroutine instruction: SCALL a Object code: 1110 nnnn Condition : PC a ; a=8n+6 ; n=1..15 ; a=86h, n=0 PC 0 0 0 0 a a a a a a a a
LCALL a Object code: 0100 0 aaa aaaa aaaa Condition: PC a PC 0 a a a a a a a a a a a
RET Object code: 0100 1111 Condition: PC STACK[SP]; SP + 1 PC The return address stored in stack
RT I Object code: 0100 1101 Condition : FLAG. PC STACK[SP]; EI 1; SP + 1 PC The return address stored in stack
* This specification are subject to be changed without notice.
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(3) Interrupt acceptance operation: When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into PC,The interrupt vectors are as following: INT0 (External interrupt from P8.2) PC 0 0 0 0 0 0 0 0 0 0 1 0
HTC (High speed counter) PC 0 0 0 0 0 0 0 0 0 1 0 0
TRGA (Timer A overflow interrupt) PC 0 0 0 0 0 0 0 0 0 1 1 0
TRGB (Time B overflow interrupt) PC 0 0 0 0 0 0 0 0 1 0 0 0
TBI (Time base interrupt) PC 0 0 0 0 0 0 0 0 1 0 1 0
SPI (Speech Interrupt) PC 0 (4) Reset operation: PC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
(5) Other operations: For 1-byte instruction execution: PC + 1 For 2-byte instruction execution: PC + 2 For 3-byte instruction execution: PC + 3 ACCUMULATOR Accumulator is a 4-bit data register for temporary data . For the arithematic, logic and comparative opertion .., ACC plays a role which holds the source data and result .
* This specification are subject to be changed without notice.
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FLAGS There are three kinds of flag, CF ( Carry flag ), ZF ( Zero flag ), SF ( Status flag ), these 3 1-bit flags are affected by the arithematic, logic and comparative .... operation . All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after RTI instruction executed . (1) Carry Flag ( CF ) The carry flag is affected by following operation: a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will be "1", in another word, if the operation has no carry-out, CF will be "0". b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a borrow, in the CF will be "0", in another word, if no borrow-in, CF will be "1". c. Comparision: CF is as a borrow-in indicator for Comparision operation as the same as subtraction operation. d. Rotation: CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after rotation. e. CF test instruction : For TFCFC instruction, the content of CF sends into SF then clear itself "0". For TTSFC instruction, the content of CF sends into SF then set itself "1". (2) Zero Flag ( ZF ) ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be "1", otherwise, the ZF will be "0". (3) Status Flag ( SF ) The SF is affected by instruction operation and system status . a. SF is initiated to "1" for reset condition . b. Branch instruction is decided by SF, when SF=1, branch condition will be satisified, otherwise, branch condition will not be satisified by SF = 0 . PROGRAM EXAMPLE: Check following arithematic operation for CF, ZF, SF
CF ZF 1 0 0 0 0 SF 1 1 1 0 0
LDIA #00h; LDIA #03h; ADDA #05h; ADDA #0Dh; ADDA #0Eh;
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ALU The arithematic operation of 4 - bit data is performed in ALU unit. There are 2 flags can be affected by the result of ALU operation, ZF and SF . The operation of ALU can be affected by CF only . ALU STRUCTURE ALU supported user arithematic operation function, including : addition, subtraction and rotaion.
DATA BUS
ALU
ZF CF SF
ALU FUNCTION (1) Addition: For instruction ADDAM, ADCAM, ADDM #k, ADD #k,y .... ALU supports addition function. The addition operation can affect CF and ZF. For addition operation, if the result is "0", ZF will be "1", otherwise, not equal "0", ZF will be "0", When the addition operation has a carry-out. CF will be "1", otherwise, CF will be "0". EXAMPLE:
Operation 3+4=7 7+F=6 0+0=0 8+8=0 Carry 0 1 0 1 Zero 0 0 1 1
(2) Subtraction: For instruction SUBM #k, SUBA #k, SBCAM, DECM... ALU supports user subtraction function . The subtraction operation can affect CF and ZF, For subtraction operation, if the result is negative, CF will be "0", it means a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result of subtraction operation is "0", the ZF will be "1", otherwise, ZF will be "1". EXAMPLE:
Operation 8-4=4 7-F= -8(1000) 9-9=0 Carry Zero 1 0 0 0 1 1
* This specification are subject to be changed without notice.
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inary Prelim
(3) Rotation: There are two kinds of rotation operation, one is rotation left, the other is rotation right. RLCA instruction rotates Acc value to left, shift the CF value into the LSB bit of Acc and the shift out data will be hold in CF.
MSB LSB ACC CF
RRCA instruction operation rotates Acc value to right, shift the CF value into the MSB bit of Acc and the shift out data will be hold in CF.
MSB LSB ACC CF
PROGRAM EXAMPLE: To rotate Acc right and shift a "1" into the MSB bit of Acc .
TTCFS; CF 1 RRCA; rotate Acc right and shift CF=1 into MSB.
HL REGISTER HL register are two 4-bit registers, they are used as a pair of pointer for the address of RAM memory and also 2 independent temporary 4-bit data registers. For some instruction, L register can be a pointer to indicate the pin number ( Port4 ) . HL REGISTER STRUCTURE
3210
3210
H REGISTER L REGISTER
* This specification are subject to be changed without notice.
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HL REGISTER FUNCTION (1) For instruction : LDL #k, LDH #k, THA, THL, INCL, DECL, EXAL, EXAH, HL register used as a temporary register . PROGRAM EXAMPLE: Load immediate data "5h" into L register, "Dh" into H register.
LDL #05h; LDH #0Dh;
(2) For instruction LDAM, STAM, STAMI .., HL register used as a pointer for the address of RAM memory. PROGRAM EXAMPLE: Store immediate data #Ah into RAM of address 35h.
LDL #5h; LDH #3h; STDMI #0Ah; RAM[35] Ah
(3) For instruction : SELP, CLPL, TFPL, L regieter be a pointer to indicate the bit of I/O port. When LR = 0 indicate P4.0 PROGRAM EXAMPLE: To set bit 0 of Port4 to "1"
LDL #00h; SEPL ; P4.0 1
STACK POINTER (SP) Stack pointer is a 4-bit register which stores the present stack level number. Before using stack, user must set the SP value first, CPU will not initiate the SP value after reset condition . When a new subroutine is accepted, the SP will be decreased one automatically, in another word, if returning from a subroutine, the SP will be increased one . The data transfer between ACC and SP is by instruction of "LDASP" and "STASP". DATA POINTER (DP) Data pointer is a 12-bit register which stores the address of ROM can indicate the ROM code data specified by user (refer to data ROM). CLOCK AND TIMING GENERATOR The clock generator is supported by a dual clock system, the slow clock source comes from crystal (resonator) or RC oscillation is decided by mask option, and it's 32.768 KHz. The high freq OSC is built by a internal clock source that will be 4.6 MHz. CLOCK GENERATOR STRUCTURE There are two clock generator for system clock control. P14 is the status register for the CPU status. P16, P19 and P22 are the system clock mode control ports.
* This specification are subject to be changed without notice.
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inary Prelim
CLK 0.022uF
High-frequency generator
LXIN
fc
P14
LXOUT
Low-frequency generator
fs
System clock mode control
P16 P19 P22
Mask option for choose Crystal or RC oscillator
System control
VDD R LXIN
20PF LXIN
LXOUT open LXOUT
Crystal connection
RC oscillator connection R=1.2M
SYSTEM CLOCK MODE CONTROL The system clock mode controller can start or stop the high-frequency and low-frequency clock oscillator and switch between the basic clocks. EM73880 has four operation modes (NORMAL, SLOW,IDLE and STOP operation modes).
STOP operation mode High osc : stopped Low osc : stopped
I/O wakeup Reset
Command (P16)
Reset
NORMAL operation mode
High osc : oscillating Low osc : oscillating Command (P22) Command (P22)
Command (P16)
Reset release
RESET operation
Reset
SLOW operation mode
High osc : stopped Low osc : oscillating
Reset
Command (P19)
I/O or internal timer wakeup
IDLE (CPU stops)
High osc : stopped Low osc : oscillating
Operation Mode Oscillator NORMAL High, Low frequency SLOW Low frequency IDLE Low frequency STOP None
System Clock High frequency clock Low frequency clock CPU stops CPU stops
Available function LCD, HST, Speech sound LCD, HST LCD All disable
One instruction cycle 8 / fc 8 / fs 11.30.2001 13
* This specification are subject to be changed without notice.
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NORMAL OPERATION MODE The 4-bit c is in the NORMAL operation mode when the CPU is reseted. This mode is a dual clock system (high-frequency and low-frequency clocks oscillating). It can be changed to SLOW or STOP operation mode by the command register (P22 or P16). LCD display and high speed timer/counter with melody output are available for the NORMAL operation mode. SLOW OPERATION MODE The SLOW operation mode is a single clock system (low-frequency clock oscillating). It can be changed to the DUAL operation mode with the commoand register (P22), STOP operation mode with P16 and IDLE operation mode with P19. LCD display and high speed timer/counter with melody output are available for the SLOW operation mode. P22
3 * 2 1 SOM 0
Initial value : 0000
SOM 000 1**
Select operation mode NORMAL operation mode SLOW operation mode
P14
3 *
2 WKS
1 0 LFS CPUS
Initial value : *000
LFS 0 1 WKS 0 1
Low-frequency status LXIN source is not stable LXIN source is stable Wakeup status Wakeup not by internal timer Wakeup by internal timer
CPUS 0 1
CPU status NORMAL operation mode SLOW operation mode
Port14 is the status register for CPU. P14.0 (CPU status) and P14.1 (Low-frequency status) are read-only bits. p14.2 (wakeup status) will be set to '1' when CPU is wake-up by internal timer. P14.2 will be cleared to '0' when user out data to P14. IDLE OPERATION MODE The IDLE operation mode suspends all SLOW operations except for the low-frequency clock and LCD driver. It retains the internal status with low power consumption without stopping the clock function and LCD display. LCD display is available for the IDLE operation mode. Sound generator is disabled in this mode. The IDLE operation mode will be wakeup and return to the SLOW operation mode by the internal timing generator or I/O pins (P0(0..3)/WAKEUP 0..3 or P8(0..3)/WAKEUPA..D).
* This specification are subject to be changed without notice.
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P19
3 IDME
2
1
0 SIDR
inary Prelim Initial value : 0000
SIDR 00 01 10 11 Select IDLE releasing condition P0(0..3), P8(0..3) pin input P0(0..3), P8(0..3) pin input and 1 sec signal P0(0..3), P8(0..3) pin input and 0.5 sec signal P0(0..3), P8(0..3) pin input and 15.625 ms signal
IDME 01 **
Enable IDLE mode Enable IDLE mode Reserved
STOP OPERATION MODE The STOP operation mode suspends system operation and holds the internal status immediately before the suspension with low power consumption. This mode will be released by reset or I/O pins (P0(0..3)/ WAKEUP 0..3 or P8(0..3)/WAKEUP A..D). LCD display and high speed timer/counter with melody output are disabled in the mode. P16
3 2 SPME 1 0 SWWT
Initial value : 0000
SPME 01 **
Enable STOP mode Enable STOP mode Reserved
SWWT 00 01 10 11
Set wake-up warm-up time 212/fs 2 10/ fs 214/fs Reserved
TIME BASE INTERRUPT (TBI ) The time base can be used to generate a fixed frequency interrupt. There are 8 kinds of frequencies can be selected by setting P25
P25 3 2 1 0 initial value : 0000
0 0 0 0 0 1 1 1 1 1
P25 0x 10 10 11 11 10 10 11 11 0x
x 0 1 0 1 0 1 0 1 x
NORMAL operation mode Interrupt disable Interrupt frequency LXIN / 23 Hz Interrupt frequency LXIN / 24 Hz Interrupt frequency LXIN / 25 Hz Interrupt frequency LXIN / 214 Hz Interrupt frequency LXIN / 21 Hz Interrupt frequency LXIN / 26 Hz Interrupt frequency LXIN / 28 Hz Interrupt frequency LXIN / 210 Hz Reserved
SLOW operation mode Interrupt disable Reserved Reserved Reserved Interrupt frequency LXIN / 214 Hz Reserved Interrupt frequency LXIN / 26 Hz Interrupt frequency LXIN / 28 Hz Interrupt frequency LXIN / 210 Hz Reserved
TIMER / COUNTER ( TIMERA, TIMERB) Timer/counters can support user three special functions: 1. Even counter 2. Timer. 3. Pulse-width measurement. * This specification are subject to be changed without notice.
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These three functions can be executed by 2 timer/counter independently. For timerA, the counter data is saved in timer register TAH, TAM, TAL, which user can set counter initial value and read the counter value by instruction "LDATAH(M,L), STATAH(M,L)" and timer register is TBH, TBM, TBL and W/R instruction "LDATBH (M,L), STATBH (M,L)". The basic structure of timer/counter is composed by two same structure counter, these two counters can be set initial value and send counter value to timer register, P28 and P29 are the command ports for timerA and timer B, user can choose different operation mode and different internal clock rate by setting these two ports. When timer/counter overflow, it will generate a TRGA(B) interrupt request to interrupt control unit.
INTERRUPT CONTROL TRGA request DATA BUS 12 BIT COUNTER 12 BIT COUNTER TRGB request
P8.3/ TRGA internal clock
EVENT COUNTER CONTROL
EVENT COUNTER CONTROL
P8.1/ TRGB
TIMER CONTROL
PULSE-WIDTH MEASUREMENT CONTROL
TIMER CONTROL
PULSE-WIDTH MEASUREMENT CONTROL
MUX
internal clock high speed timer/counter
P28
TMSA
IPSA
P29
TMSB
IPSB
TIMER/COUNTER CONTROL P8.1/TRGB, P8.3/TRGA are the external timer inputs for timerB and timerA, they are used in event counter and pulse-width measurement mode. Timer/counter command port: P28 is the command port for timer/counterA and P29 is for the timer/ counterB.
Port 28 3 2 1 0 TIMER/COUNTER MODE SELECTION Function description Stop Event counter mode Timer mode Pulse width measurement mode TMSA IPSA TMSA (B) 00 01 Port 29 3 2 1 0 IPSB 11 10
Initial state: 0000
TMSB
Initial state: 0000
INTERNAL PULSE-RATE SELECTION IPSA NORMAL mode SLOW mode Reserved 00 LXIN/23 Hz 01 LXIN/27 Hz LXIN/27 Hz 11 10 LXIN/2 Hz LXIN/211 Hz 11 LXIN/215 Hz LXIN/215 Hz
INTERNAL PULSE-RATE SELECTION IPSB NORMAL mode SLOW mode 00 Depend on high speed timer/counter 01 LXIN/25 Hz LXIN/25 Hz 9 10 LXIN/2 Hz LXIN/29 Hz 11 LXIN/213 Hz LXIN/213 Hz
* This specification are subject to be changed without notice.
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TIMER/COUNTER FUNCTION
inary Prelim
Timer/counterA can be programmable for timer, event counter and pulse width measurement. Each timer/ counter can execute any one of these functions independly. EVENT COUNTER MODE For event counter mode, timer/counter increases one at any rising edge of P8.1/TRGB for timerB (P8.3/ TRGA for timer A). When timerB (timerA) counts overflow, it will give interrupt control an interrupt request TRGB (TRGA).
P8.1/TRGB (P8.3/TRGA)
TimerB (TimerA) value n
n+1
n+2
n+3
n+4
n+5
n+6
PROGRAM EXAMPLE: Enable timerA with P28
LDIA #0100B; OUTA P28; Enable timerA with event counter mode
TIMER MODE For timer mode ,timer/counter increase one at any rising edge of internal pulse . User can choose 4 kinds of internal pulse rate by setting IPSB for timerB (IPSA for timerA). When timer/counter counts overflow, TRGB (TRGA) will be generated to interrupt control unit.
Internal pulse
TimerB (TimerA )value
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
PROGRAM EXAMPLE: To generate TRGA interrupt request after 60 ms with system clock LXlN=32KHz
LDIA #0100B; EXAE; enable mask 2 EICIL 110111B; interrupt latch 0, enable EI LDIA #0AH; STATAL; LDIA #00H; STATAM; LDIA #0FH; STATAH; LDIA #1000B; OUTA P28; enable timerA with internal pulse rate: LXIN/23 Hz
NOTE:
The preset value of timer/counter register is calculated as following procedure. Internal pulse rate: LXIN/23 ; LXIN = 32KHz The time of timer counter count one = 23 /LXIN = 8/32768=0.244ms The number of internal pulse to get timer overflow = 60 ms/ 0.244ms = 245.901= 0F6H The preset value of timer/counter register = 1000H - 0F6H = 0F0AH
PULSE WIDTH MEASUREMENT MODE
* This specification are subject to be changed without notice.
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For the pulse width measurement mode, the counter only incresed by the rising edge of internal pulse rate as external timer/counter input (P8.1/TRGB, P8.3/TRGA), interrupt request will be generated as soon as timer/counter count overflow.
P8.1/TRGB(P8.3/TRGA)
Internal pulse
TimerB(TimerA) value
n
n+1
n+2
n+3
n+4
n+5
PROGRAM EXAMPLE : Enable timerA by pulse width measurement mode .
LDIA #1100b; OUTA P28; Enable timerA with pulse width measurement mode.
HIGH SPEED TIMER/COUNTER 8-bit high speed timer/counter (HTC) supports three special functions : auto load timer, melody output and pulse width measurement modes. The HTC is available for the NORMAL and SLOW operation mode. The HTC can be set initial value and send counter value to counter registers (P11 and P10), P31 is the command port for HTC, user can choose different operation mode and different internal clockrate by setting the port. The timer/counter increase one at the rising edge of internal pulse. The HTC can generate an overflow interrupt (HTCI) when it overflows.
O2 FHTC P31(3,2) 8-bit binary counter P31(1,0) XIN P4.1/TRGH Input data Data bus P11 P10 Overflow HTCI interrupt Timer/counter B
Reload
P31 is the command register of the 8-bit high speed timer/counter. P31
3 2 HTMS 1 HIPS 0
Initial value : 0000
HTMS 0 0 1 1 0 1 0 1
Mode selection Stop Event counter mode Auto load timer mode Pulse width measurement mode
HIPS 0 0 1 1 0 1 0 1
Clock rate selection NORMAL mode SLOW mode LXIN/20 Hz LXIN/20 Hz LXIN/22 Hz LXIN/22 Hz 4 CLK/2 Hz Reserved CLK/26 Hz Reserved * CLK=4.6MHz
P11 and P10 are the counter registers of the 8-bit high speed timer/counter. P10 is the lower nibble register and P11 is the higher nibble register. (HT is the value of counter registers.) P11
3 2 1 0 Higher nibble register
P10
3 2 1 0 Lower nibble register
Initial value : 0000 0000 (HT)
* This specification are subject to be changed without notice.
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EM73880 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary Prelim
The value of 8-bit binary up counter can be presetted by P10 and P11. The value of registers can loaded into the HTC when the counter starts counting or occurs overflow. If user write value to the registers before the next overflow occurs, the preset value can be changed. The preset value will be changed when users output the different data to P10. Thus, the data must be output to P11 before P10 when users want to change the preset value. The count value of HTC can be read from P10 and P11. The value is unstable when user read the value during counting. Thus, user must disable the counter before reading the value. The P4.1/RGH pin will be the input pin in the event counter and pulse width measurement mode. User must output high to P4. 1/TRGH and then it can be the HTC external input pin. When the HTC is disabled, the P4. 1 pin is a normal I/O pin. INTERRUPT FUNCTION There are 6 interrupt sources, 2 external interrupt sources, 4 internal interrupt sources . Multiple interrupts are admitted according the priority .
Type Interrupt source Priority Interrupt Interrupt Program ROM Latch Enable condition entry address 1 2 3 4 5 6 IL5 IL4 IL3 IL2 IL1 IL0 EI=1 EI=1, MASK3=1 EI=1, MASK2=1 EI=1, MASK1=1 EI=1,MASK0=1 002H 004H 006H 008H 00AH 00CH
External Internal Internal Internal Internal Internal
External interrupt(INT0) High speed timer overflow interrupt (HTCI) TimerA overflow interrupt (TRGA) TimerB overflow interrupt (TRGB) Time base interrupt(TBI) SPI (Speech interrupt)
INTERRUPT STRUCTURE
MASK0 MASK1 MASK1 MASK2 MASK3 SPI r0 Reset by system reset and program instruction IL0 TBI r1 IL1 TRGB r2 IL2 TRGA r3 IL3 HTCI r4 IL4 INT0 r5 IL5
Priority checker Reset by system reset and program instruction Set by program instruction EI
Entry address generator
Interrupt request
Interrupt entry address
* This specification are subject to be changed without notice.
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Interrupt controller: IL0-IL5
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: Interrupt latch . Hold all interrupt requests from all interrupt sources. ILr can not be set by program, but can be reset by program or system reset, so IL only can decide which interrupt source can be accepted. : Except INT0 ,MASK register can promit or inhibit all interrupt sources. : Enable interrupt Flip-Flop can promit or inhibit all interrupt sources, when interrupt happened, EI is cleared to "0" automatically, after RTI instruction happened, EI will be set to "1" again .
MASK0-MASK3 EI
Priority checker: Check interrupt priority when multiple interrupts happened. INTERRUPT FUNCTION The procedure of interrupt operation: 1. Push PC and all flags to stack. 2. Set interrupt entry address into PC. 3. Set SF= 1. 4. Clear EI to inhibit other interrupts happened. 5. Clear the IL for which interrupt source has already be accepted. 6. To excute interrupt subroutine from the interrupt entry address. 7. CPU accept RTI, restore PC and flags from stack . Set EI to accept other interrupt requests. PROGRAM EXAMPLE: To enable interrupt of "INT0, TRGA"
LDIA #1100B; EXAE; set mask register "1100B" EICIL 111111B ; enable interrupt F.F.
SPEECH SYNTHESIZER OPERATES PROCEDURE 1. Send the speech start address to the address latch by writing P6 four times. 2. Choose the sampling rate, enable the speech synthesizer by writing P5. 3. The ROM address counters send the ROM address A6 .. A18 to the speech ROM. 4. ACT is the speech acknowledge signal. When the speech synthesizer has voice output. ACT is high . When ACT is changed from high to low, the speech synthesizer can generate the speech ending interrupt SPI. The ACT signal can be read from P5.3.
* This specification are subject to be changed without notice.
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inary Prelim
SPEECH SYNTHESIZER CONTROL Speech sample rate control register (P5 write) : 3 2 1 0 Initial value : *000 SINT SR SR 000 001 010 011 100 101 111 SINT 0 1 Sample rate selection PWM on CLK/64/1/3 CLK/64/1/4 CLK/64/2/3 CLK/64/2/4 CLK/64/3/3 CLK/64/3/4 PWM off Sample rate 24K 18K 12K 9K 8K 6K
port 5 -- initialization is "*111". port 6 -- initialization is pointed to the lownibble of start address latch. CLK=4.6 MHz
Select interrupt source Select HTC overflow interrupt Select speech ending interrupt
Speech active flag (P5 read) : 3 2 1 0 ACT * * *
Initial value : 0***
ACT is the speech acknowledge signal. When the speech synthesizer has voice output, ACT is high. When ACT is high low, the speech synthesizer can generate the speech ending interrupt SPI, or when HTC overflow interrupt SPI. Speech start address register (P6 write) : 3 2 1 Port 6 0 Initial value : 1111
P6L1 A9 A8
A7
A6
P6L2 A13 A12 A11 A10
P6L3 A17 A16 A15 A14
P6L4 -
-
-
-
Send the speech start address to the speech synthesizer by writing P6 four times. There is a pointer counter to point the address latch (P6L1, P6L2, P6L3, P6L4). It will increase one when write P6. So, the first time writing P6 to P6L1, the second time is P6L2, the third time is P6L3, the fourth time is P6L4 and the fifth time is P6L1 latch again, ... etc. The pointer counter point to P6L1 when CPU is reset or P5 is writen. In the NORMAL operation mode, the speech synthesizer is available. In the other operation modes, it is disable.
* This specification are subject to be changed without notice.
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MELODY (SOUND EFFECT) CONTROL One channel melody/sound effect output, controlled by port 23, 24, 17, and 30. There is a built-in sound effect. It includes the tone generator and random generator. The tone generator is a binary down counter and the random generator is a 9-bit liner feedback shift register.
P30 P23,P24 f2 CLK/8
4 kinds of divider
f1
Tone generator
/2
/2 Output control PWM ckt.
f2x2
Random generator
Sound effect command register (P30) There are 4 kinds of basic frequency for sound generator which can be selected by P30. The output of sound effect is tone and random combination. Port30 3 2 1 0
BFREQ SMODE Initial value : 0000
BFREQ Basic frequency (f1) select 0 0 CLK/4 0 1 CLK/8 1 0 CLK/16 1 1 CLK/32 (CLK=4.6MHz) Tone frequency register (P23, P24)
SMODE 00 01 10 11
Sound generator mode Disable Tone output Random output Tone+random output
The 8-bit tone frequency register is P24 and P23. The tone frequency will be changed when user output the different data to P23. Thus, the data must be output to P24 before P23 when users want to change the 8-bit tone frequency (TF). Port24 Port23
3 2 1 0 3 2 1 0 Initial value : 1111 1111 Higher nibble register Lower nibble register
** f1=CLK/2X, f2=f1/(TF+1)/2, TF=1~255, TF0 ** Example : CLK=4.6 MHz, BFREQ=11, TF=00110001B. f1=143.75K Hz, f2=143.75K Hz/50/2=1430 Hz
* This specification are subject to be changed without notice.
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inary Prelim
Random generator f(x)=x9+x4+1
1 2 3
+
4 5 6 7 8 9
Volume control register (P17) The are 16 levels of volume for sound generator. P17 is the volume control register. Port17 Initial value : 1111 3 2 1 0 VCR VCR ts/tp 1 1 1 1 15/16 ts 1 1 1 0 14/16 1 tp= : : CLK/64 (CLK=4.6MHz) 0 0 0 1 1/16 tp 0 0 0 0 0/16 PROGRAM EXAMPLE:
LDIA OUTA LDIA OUTA LDIA OUTA LDIA OUTA #1101B P30 #0111B P17 #0011B P24 #0001B P23 ; basic frequency : CLK/32, tone output ; volume control ; 1430 Hz tone output
WATCH-DOG-TIMER (WDT) Watch-dog-timer can help user to detect the malfunction (runaway) of CPU and give system a timeup signal every certain time . User can use the time up signal to give system a reset signal when system is fail. This function is available by mask option. If the mask option of WDT is enabled, it will stop counting when CPU is reseted or in the STOP operation mode. The basic structure of Watch-Dog-Timer control is composed by a 4-stage binary counter and a control unit . The WDT counter counts for a certain time to check the CPU status, if there is no malfunction happened, the counter will be cleared and continue counting . Otherwise, if there is a malfunction happened, the WDT control will send a WDT signal ( low active ) to reset CPU. The WDT checking period is assign by P21 ( WDT command port ).
WDT counter LXIN/213 0 1 2 3 RESET pin counter clear request mask option WDT control
P21 WDT command port
* This specification are subject to be changed without notice.
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P21 is the control port of watch-dog-timer, and the WDT time up signal is connected to RESET. Port 21
CWC
3
*
2
*
1
0
WDT
Initial value :0000
CWC 0 1 WDT 0 1
Clear watchdog timer counter Clear counter then return to 1 Nothing Set watch-dog-timer detect time 3 x 213/LXIN = 3 x 213/32K Hz = 0.75 sec 7 x 213/LXIN = 7 x 213/32K Hz = 1.75 sec
PROGRAM EXAMPLE To enable WDT with 7 x 213/LXIN detection time.
LDIA #0001B OUTA P21; set WDT detection time and clear WDT counter : :
LCD DRIVER EM73880 can directly drive the liquid crystal display (LCD) and has 32 segment, 4 common output pins (1/ 2 bias, 1/3 bias). There are total 32x4 dots can be display. The V1, V2, V3, VA, VB, VDD and VSS pins are the LCD bias generator. CONTROL OF LCD DRIVER The LCD driver control command register is P27. When LDC is 0, the LCD is disabled, and user could change Duty in this situation only the COM and SEG pins are VSS. When LDC is 1, the LCD driver enables. When the CPU is reseted or during the STOP operation mode, the LCD driver is disabled. Port27 321 0 Initial value : 0000
LDC DUTY
LDC 0 1
LCD display control DUTY LCD display disable and change Duty 0 0 0 LCD display enable 001 010 011 100 101 11*
Driving method select 1/4 duty (1/3 bias) 1/4 duty (1/2 bias) 1/3 duty (1/3 bias) 1/3 duty (1/2 bias) 1/2 duty (1/2 bias) Static Reserved
* This specification are subject to be changed without notice.
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inary Prelim
The LCD display data is stored in the display data area of the data memory (RAM). The display data area begins with address 20H during reset. The LCD display data area ia as below : RAM address 20H 21H 22H : : 3EH 3FH COM3 bit3 COM2 bit2 COM1 bit1 COM0 bit0
SEG0 SEG1 SEG2 : : SEG30 SEG31
The relation between LCD display data and driving method Driving method bit3 bit2 bit1 1/4 duty COM3 COM2 COM1 1/3 duty COM2 COM1 1/2 duty COM1 Static -
bit0 COM0 COM0 COM0 COM0
LCD frame frequency : According to the drive method to set the frame frequency. Duty Frame frequency (Hz) 1/4 duty 64 x (4/4) = 64 1/3 duty 64 x (4/3) = 85 1/2 duty 64 x (4/2) = 128 Static 64
PROGRAM EXAMPLE : LDIA #0001B ; 1/4 duty, 1/2 bias OUTA P27 LDIA #1001B ; enable LCD OUTA P27
* This specification are subject to be changed without notice.
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LCD DRIVING METHODS There are six kinds of driving methods can be selected by DUTY (P27.0~P27.2). The drivinf waveforms of LCD driver are as below :
* VDD=3V
(1) 1/4 duty (1/3 bias) VLCD=VDD
VDD V3 V2 VA VB COM0 V1 VSS
V3 V2 V1 Vss V3 V2 V1 Vss V3 V2 V1 Vss V3 V2 V1 Vss V3 V2 V1 Vss V3 V2 V1 Vss -V1 -V2 -V3 V3 V2 V1 Vss -V1 -V2 -V3 V3 V2 V1 Vss V3 V2 V1 Vss -V1 -V2 -V3 V3 V2 V1 Vss -V1 -V2 -V3
VLCD=3/2VDD
3V 2V 1V VA VB VDD V3 V2 V1 VSS 4.5V 3V 1.5V
(2 ) 1/3 duty (1/3 bias) VLCD=VDD
VDD V3 V2 VA VB V1 VSS
V3 V2 V1 Vss V3 V2 V1 Vss V3 V2 V1 Vss
VLCD=3/2VDD
VDD V3 V2 VA VB V1 VSS 4.5V 3V 1.5V
3V 2V 1V
COM1
COM2
COM3
SEG0
SEG0-COM0 ON
SEG0-COM1 OFF
Frame
Frame
(3) 1/4 duty (1/2 bias) VLCD=VDD
VDD V3 V2 VA VB COM0 COM1 COM2 V1 VSS
V3 V1 Vss V3 V1 Vss V3 V1 Vss V3 V1 Vss
(4) 1/3 duty (1/2 bias) VLCD=VDD
VDD V3 V2 VA VB V1 VSS
V3 V1 Vss V3 V1 Vss V3 V1 Vss
(5) 1/2 duty (1/2 bias) VLCD=VDD
VDD V3 V2 VA VB V1 VSS
V3 V1 Vss V3 V1 Vss
(6) static VLCD=VDD
VDD V3 V2 VA VB
V3 Vss
3V 1.5V
3V 1.5V
3V 1.5V
3V 1.5V
V1 VSS
COM3 SEG0 SEG0-COM0 ON SEG0-COM1 OFF
Frame
ON
V3 V1 Vss V3 V1 Vss -V1 -V3 V3 V1 Vss -V1 -V3 V3 V1 Vss V3 V1 Vss -V1 -V3 V3 V1 Vss -V1 -V3 Frame V3 V1 Vss V3 V1 Vss -V1 -V3 V3 V1 Vss -V1 -V3 Frame
OFF
V3 V1 Vss
V3 Vss -V3 V3 Vss -V3
Frame
* This specification are subject to be changed without notice.
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inary Prelim
RESETTING FUNCTION When CPU in normal working condition and RESET pin holds in low level for three instruction cycles at least, then CPU begins to initialize the whole internal states, and when RESET pin changes to high level, CPU begins to work in normal condition. The CPU internal state during reset condition is as following table : Hardware condition in RESET state Program counter Status flag Interrupt enable flip-flop ( EI ) MASK0 ,1, 2, 3 Interrupt latch ( IL ) P4, P5, P10, 11,14, 16, 19, 25, 27, 28, 29, 31 P4, 8, 17, 23, 24 Both oscillator Initial value 0000h 01h 00h 00h 00h 00h 0Fh Start oscillation
The RESET pin is a hysteresis input pin and it has a pull-up resistor available by mask option. The simplest RESET circuit is connect RESET pin with a capacitor to VSS and a diode to VDD.
RESET
* This specification are subject to be changed without notice.
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EM73880 I/O PORT DESCRIPTION :
Port 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Input function Input port , wakeup function ---Input port Speech active signal --Input port, wakeup function, -----CPU status -Output function ---Output port, P4.1/HST Speech sample rate control register Speech address address -Output port -High speed timer/counter High speed timer/counter --Clear P14.0 to 0 -STOP mode control register Volumn control register -IDLE mode control register -WDT counter Slow mode control register --Timebase control register -LCD control register Timer/counter A control register Timer/counter B control register -HTC control register Note
E
E I
E I I E I I
--
E
low nibble high nibble
I
I I
I
I
I I I I I
* This specification are subject to be changed without notice.
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EM73880 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
ABSOLUTE MAXIMUM RATINGS
Items Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature Sym. VDD VIN VO PD TOPR TSTG
inary Prelim
Ratings -0.5V to 6V -0.5V to VDD+0.5V -0.5V to VDD+0.5V 300mW 0oC to 50oC -55oC to 125oC Conditions
TOPR=50oC
RECOMMANDED OPERATING CONDITIONS
Items Supply Voltage Input Voltage Operating Frequency Sym. V DD V IH V IL FC Fs Ratings 2.2V to 3.6V 0.90xVDD to VDD 0V to 0.10xVDD 4.6MHz 32KHz Condition
CLK LXIN, LXOUT
DC ELECTRICAL CHARACTERISTICS (VDD=30.3V, VSS=0V, TOPR=25oC) Parameters
Supply current
Sym.
I DD
Min.
-
Typ.
700 12 7 10 5 0.1 20 -20 -40 2.6 2.4 0.1 100
Max. Unit
1200 20 15 15 10 1
0.75VDD 0.40VDD
Conditions
VDD=3.3V,no load,NORMAL mode, Fc=4.6MHz, Fs=32KHz VDD=3.3V,no load,SLOW mode,RC osc. (R=1.2M) VDD=3.3V,no load,SLOW mode,Crystal osc. (Fs=32KHz) VDD=3.3V,IDLE mode,RC osc.(R=1.2M) VDD=3.3V,IDLE mode,Crystal osc. VDD=3.3V, STOP mode RESET, P0, P8 P0, Pull-down, VIH=VDD P0, Pull-up, VIH=VSS P0, None RESET, Open-drain, VDD=3.3V,VIH=3.3/0V Low current Push-pull, VDD=3.3V,VIL=0.4V High current push-pull, SOUND, VDD=2.7V, IOH=-1mA Normal current push-pull, VDD=2.7V, IOH=-60A VDD=2.7V,IOL=1mA Open-drain, VDD=3.3V, VO=3.3V RESET
A A A A A A V V A A A A A V V V A K
Hysteresis voltage Input current
VHYS+ VHYSI IH
0.50VDD 0.20VDD
Output voltage
I IL V OH
-30 2.4 2.0
30 1 1 -70 0.3 1 300
Leakage current Input resistor
V OL ILO R IN
50
* This specification are subject to be changed without notice.
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DC ELECTRICAL CHARACTERISTICS (VDD=30.3V, VSS=0V, TOPR=25oC) Parameters
LCD bias voltage (1/2 bias) LCD bias voltage (1/3 bias) Output current of BZ1, BZ2
Sym.
V1 V2 V3 V1 V2 V3 I OH I OL
1 1
Min.
Typ.
1 1 1
Max. Unit
V V V V 2 /3VDD+0.1 V VDD+0.1 V mA mA
/2VDD+0.1 /2VDD+0.1 VDD+0.1
Conditions
I1=5A I2=5A I3=5A I1=5A I2=5A I3=5A VDD=3V, VBZ=1.5V
/2VDD-0.1 /2VDD /2VDD-0.1 1/2VDD VDD 1 /3VDD-0.1 1/3VDD 2 /3VDD-0.1 2/3VDD VDD
30 30
-
* This specification are subject to be changed without notice.
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EM73880 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
RESET PIN TYPE
TYPE RESET-A
inary Prelim
RESET
mask option
OSCILLATION PIN TYPE
TYPE OSC-B
LXIN
TYPE OSC-D
Crystal Osc.
LXOUT
CLK
Internal OSC.
TYPE OSC-H
VDD
LXIN
RC Osc.
INPUT PIN TYPE
TYPE INPUT-K
positive edge input data detector
WAKEUP mask option negative edge detector
: mask option
I/O PIN TYPE
TYPE I/O-N TYPE I/O-Q
: mask option
: mask option
* This specification are subject to be changed without notice.
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TYPE I/O-R
path B path A Input data
TYPE I/O-S
Special function control input Input data
Output data latch
path B path A
SEL
TYPE I/O-Q
Output data latch
Output data Special function output
TYPE I/O-N
Output data
: mask option
WAKEUP function mask option
Path A : Path B :
For set and clear bit of port instructions, data goes through path A from output data latch to CPU. For input and test instructions, data from output pin go through path B to CPU and the output data latch will be set to high.
* This specification are subject to be changed without notice.
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EM73880 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT PAD DIAGRAM
inary Prelim
COM0 COM1 COM2 COM3
SEG0
SEG1
SEG2
SEG3
VSS
VA
VB
V1
V2
V3
11 12 13 14
9
8
7
6
5
4
3
2
1
68
67 66
65
64 63
SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26
LXOUT LXIN VDD P4.3 P4.2 P4.1 P4.0
62 60 59 58
15 16 17 18 (0,0)
57 56 55 54 53
BZ1
19
EM73880
52 51 50 49
BZ2 VDD2 P8.3 P8.2 P8.1 P8.0
20 21
48 47 46
22 23 24 25 28 29 30 31 32 33 34 35 36 37 38 39
45 43 42 41 40
RESET
P0.3
P0.2
P0.1
P0.0
SEG31
SEG30
SEG29
SEG28
Unit : m Chip Size : 2490 x 2960 m Note : For PCB layout, IC substrate must be floated or connected to VSS.
* This specification are subject to be changed without notice.
SEG27
CLK
TEST
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Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol COM3 COM2 COM1 COM0 VB VA V3 V2 V1 VSS LXOUT LXIN VDD P4.3 P4.2 P4.1 P4.0 BZ1 BZ2 VDD2 P8.3 P8.2 P8.1 P8.0 X 357.5 237.0 82.4 -38.2 -192.8 -313.4 -468.0 -588.5 -743.2 -934.0 -1079.9 -1079.9 -1055.5 -1078.5 -1078.5 -1078.5 -1078.5 -1091.5 -1091.5 -1094.9 -1074.7 -1074.7 -1074.7 -1074.7 Y 1322.4 1322.4 1322.4 1322.4 1322.4 1322.4 1322.4 1322.4 1322.4 1294.8 1019.3 898.8 745.5 526.5 404.4 282.2 160.1 -67.4 -424.5 -666.2 -902.5 -1024.7 -1146.8 -1267.3
/RESET CLK TEST P0.3 P0.2 P0.1 P0.0 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26
-812.3 -654.9 -487.7 -322.5 -154.2 15.9 184.3 346.6 467.2 621.8 742.4 897.0 1085.0
-1327.4 -1327.4 -1327.4 -1327.4 -1327.4 -1327.4 -1327.4 -1327.4 -1327.4 -1327.4 -1327.4 -1327.4 -1329.4
* This specification are subject to be changed without notice.
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EM73880 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary Prelim
Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Symbol SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 X 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 1085.0 907.9 787.4 632.7 512.2 Y -1028.8 -1088.3 -967.8 -847.2 -726.7 -606.1 -485.6 -365.1 -244.5 -124.0 -3.4 117.1 237.6 358.2 478.7 599.3 719.8 840.3 960.9 1081.4 1202.0 1322.5 1322.4 1322.4 1322.4 1322.4
* This specification are subject to be changed without notice.
11.30.2001
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EM73880 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
INSTRUCTION TABLE
(1) Data Transfer Mnemonic LDA x LDAM LDAX LDAXI LDH #k LDHL x LDIA #k LDL #k STA x STAM STAMD STAMI STD #k,y STDMI #k THA TLA (2) Rotate Mnemonic RLCA RRCA Object code ( binary ) 0101 0000 0101 0001 Object code ( binary ) 0110 1010 xxxx xxxx 0101 1010 0110 0101 0110 0111 1001 kkkk 0100 1110 xxxx xx00 1101 kkkk 1000 kkkk 0110 1001 xxxx xxxx 0101 1001 0111 1101 0111 1111 0100 1000 kkkk yyyy 1010 kkkk 0111 0110 0111 0100
ry elimina Pr
Operation description AccRAM[x] Acc RAM[HL] AccROM[DP] L AccROM[DP] H,DP+1 HRk LRRAM[x],HRRAM[x+1] Acck LRk RAM[x]Acc RAM[HL]Acc RAM[HL]Acc, LR-1 RAM[HL]Acc, LR+1 RAM[y]k RAM[HL]k, LR+1 AccHR AccLR
Byte 2 1 1 1 1 2 1 1 2 1 1 1 2 1 1 1
Cycle 2 1 2 2 1 2 1 1 2 1 1 1 2 1 1 1
Flag C Z Z Z Z Z Z Z Z Z Z Z
S 1 1 1 1 1 1 1 1 1 1 C C' 1 C' 1 1
Operation description CFAcc CFAcc
Byte 1 1
Cycle 1 1
Flag C Z C Z C Z
S C' C'
(3) Arithmetic operation 3) Mnemonic ADCAM ADD #k,y ADDA #k ADDAM ADDH #k ADDL #k ADDM #k DECA DECL DECM INCA Object code ( binary ) 0111 0100 0110 0111 0110 0110 0110 0101 0111 0101 0101 0000 1001 kkkk yyyy 1110 0101 kkkk 0001 1110 1001 kkkk 1110 0001 kkkk 1110 1101 kkkk 1100 1100 1101 1110 Operation description AccAcc + RAM[HL] + CF RAM[y]RAM[y] +k AccAcc+k AccAcc + RAM[HL] HRHR+k LRLR+k RAM[HL]RAM[HL] +k AccAcc-1 LRLR-1 RAM[HL]RAM[HL] -1 AccAcc + 1 Byte 1 2 2 1 2 2 2 1 1 1 1 Cycle 1 2 2 1 2 2 2 1 1 1 1 C C Flag Z Z Z Z Z Z Z Z Z Z Z Z
S C' C' C' C' C' C' C' C C C C'
* This specification are subject to be changed without notice.
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EM73880 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary Prelim
INCL INCM SUBA #k SBCAM SUBM #k 0111 1110 0101 1111 0110 1110 0111 kkkk 0111 0010 0110 1110 1111 kkkk LRLR + 1 RAM[HL]RAM[HL]+1 Acck-Acc AccRAM[HLl - Acc - CF' RAM[HL]k - RAM[HL] 1 1 2 1 2 1 1 2 1 2 C Z Z Z Z Z C' C' C C C
(4) Logical operation
Mnemonic ANDA #k ANDAM ANDM #k ORA #k ORAM ORM #k XORAM (5) Exchange Mnemonic Object code ( binary ) Operation description Byte Cycle Flag C Z Object code ( binary ) 0110 0111 0110 0110 0111 0110 0111 1110 0110 kkkk 1011 1110 1110 kkkk 1110 0100 kkkk 1000 1110 1100 kkkk 1001 Operation description AccAcc&k AccAcc & RAM[HL] RAM[HL]RAM[HL]&k AccAcc k Acc Acc RAM[HL] RAM[HL]RAM[HL] k AccAcc^RAM[HL]
-----
Byte 2 1 2 2 1 2 1
Cycle 2 1 2 2 1 2 1
Flag C Z Z Z Z Z Z Z Z
S Z' Z' Z' Z' Z' Z' Z'
S
EXA x EXAH EXAL EXAM EXHL x
0110 1000 xxxx xxxx 0110 0110 0110 0100 0101 1000 0100 1100 xxxx xx00
AccRAM[x] AccHR AccLR AccRAM[HL] LRRAM[x], HRRAM[x+1]
2 1 1 1 2
2 2 2 1 2
-
Z Z Z Z -
1 1 1 1 1
(6) Branch
Mnemonic Object code ( binary ) Operation description Byte Cycle Flag C Z
S
SBR a LBR a (7) Compare
Mnemonic
00aa aaaa 1100 aaaa aaaa aaaa
If SF=1 then PCPC11-6.a5-0 else null If SF= 1 then PCa else null
1 2
1 2
-
-
1 1
Object code ( binary )
Operation description
Byte
Cycle C
Flag Z
S
CMP #k,y CMPA x CMPAM CMPH #k CMPIA #k CMPL #k
0100 1011 kkkk yyyy 0110 1011 xxxx xxxx 0111 0011 0110 1110 1011 kkkk 1011 kkkk 0110 1110 0011 kkkk
k-RAM[y] RAM[x]-Acc RAM[HL] - Acc k - HR k - Acc k-LR
2 2 1 2 1 2
2 2 1 2 1 2
C C C C -
Z Z Z Z Z Z
Z' Z' Z' C Z' C
37
* This specification are subject to be changed without notice.
11.30.2001
EM73880 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
(8) Bit manipulation Mnemonic CLM CLP CLPL CLR SEM SEP SEPL SET TF TFA TFM TFP TFPL TT TTP b p,b y,b b p,b y,b y,b b b p,b y,b p,b Object code ( binary ) 1111 00bb 0110 1101 11bb pppp 0110 0000 0110 1100 11bb yyyy 1111 01bb 0110 1101 01bb pppp 0110 0010 0110 1100 01bb yyyy 0110 1100 00bb yyyy 1111 10bb 1111 11bb 0110 1101 00bb pppp 0110 0001 0110 1100 10bb yyyy 0110 1101 10bb pppp
ry elimina Pr
Operation description RAM[HL]b0 PORT[p]b0 PORT[LR3-2+4]LR1-00 RAM[y]b0 RAM[HL]b1 PORT[p]b1 PORT[LR3-2+4]LRl-01 RAM[y]b1 SFRAM[y]b' SFAccb' SFRAM[HL]b' SFPORT[p]b' SFPORT[LR3-2+4]LR1-0' SFRAM[y]b SFPORT[p]b Byte 1 2 1 2 1 2 1 2 2 1 1 2 1 2 2 Cycle 1 2 2 2 1 2 2 2 2 1 1 2 2 2 2 C Flag Z S 1 1 1 1 1 1 1 1 * * * * * * *
(9) Subroutine Mnemonic LCALL a SCALL a Object code ( binary ) 0100 0aaa aaaa aaaa 1110 nnnn Operation description STACK[SP]PC, SPSP -1, PCa STACK[SP]PC, SPSP - 1, PCa,
a = 8n +6 (n=1~15),0086h (n =0)
Byte 2 1
Cycle 2 2 C -
Flag Z -
S -
RET (10) Input/output Mnemonic INA INM OUT OUTA OUTM p p #k,p p p
0100 1111
SPSP + 1, PCSTACK[SP]
1
2
-
-
-
Object code ( binary ) 0110 1111 0100 pppp 0110 1111 1100 pppp 0100 1010 kkkk pppp 0110 1111 000p pppp 0110 1111 100p pppp
Operation description AccPORT[p] RAM[HL]PORT[p] PORT[p]k PORT[p]Acc PORT[p]RAM[HL]
Byte 2 2 2 2 2
Cycle 2 2 2 2 2 C -
Flag Z Z -
S Z' Z' 1 1 1
(11) Flag manipulation Mnemonic TFCFC Object code ( binary ) 0101 0011 Operation description SFCF', CF0 Byte 1 Cycle 1 C 0 Flag Z -
S *
* This specification are subject to be changed without notice.
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EM73880 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
inary Prelim
TGS TTCFS TZS 0101 0100 0101 0010 0101 1011 SFGF SFCF, CF1 SFZF 1 1 1 1 1 1 1 * * *
(12) Interrupt control Mnemonic CIL r DICIL r EICIL r EXAE RTI Object code ( binary ) 0110 0011 11rr rrrr 0110 0011 10rr rrrr 0110 0011 01rr rrrr 0111 0101 0100 1101 Operation description ILIL & r EIF0,ILIL&r EIF1,ILIL&r MASKAcc SPSP+1,FLAG.PC STACK[SP],EIF 1 Byte 2 2 2 1 1 Cycle 2 2 2 1 2 C * Flag Z *
S 1 1 1 1 *
(13) CPU control Mnemonic NOP Object code ( binary ) 0101 0110 Operation description no operation Byte 1 Cycle 1 Flag C Z -
S -
(14) Timer/Counter & Data pointer & Stack pointer control Mnemonic LDADPL LDADPM LDADPH LDASP LDATAL LDATAM LDATAH LDATBL LDATBM LDATBH STADPL STADPM STADPH STASP STATAL STATAM STATAH STATBL STATBM STATBH Object code ( binary ) 0110 1010 1111 1100 0101 0110 1111 1101 0101 0110 1111 1110 0101 0110 1111 1111 0110 1010 1111 0100 0101 0110 1111 0101 0101 0110 1111 0110 0110 1010 1111 1000 0101 0110 1111 1001 0101 0110 1111 1010 0110 1001 1111 1100 0110 1001 1111 1101 0110 1001 1111 1110 0110 1001 1111 1111 0110 1001 1111 0100 0110 1001 1111 0101 0110 1001 1111 0110 0110 1001 1111 1000 0110 1001 1111 1001 0110 1001 1111 1010 Operation description Acc[DP]L Acc[DP]M Acc[DP]H AccSP Acc[TA]L Acc[TA]M Acc[TA]H Acc[TB]L Acc[TB]M Acc[TB]H [DP]LAcc [DP]MAcc [DP]HAcc SPAcc [TA]LAcc [TA]MAcc [TA]HAcc [ TB]LAcc [TB]MAcc [TB]HAcc Byte 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C Flag Z Z Z Z Z Z Z Z Z Z Z -
S 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
* This specification are subject to be changed without notice.
11.30.2001
39
EM73880 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
ry elimina Pr
**** SYMBOL DESCRIPTION
Symbol HR PC SP ACC CF SF EI MASK RAM[HL] ROM[DP]L [DP]L [DP]H [TA]M([TB]M) + & ^ . x p r
LR 1-0 LR3-2
Description H register Program counter Stack pointer Accumulator Carry flag Status flag Enable interrupt register Interrupt mask Timer/counter A Data memory (address : HL ) Low 4-bit of program memory Low 4-bit of data pointer register High 4-bit of data pointer register Middle 4-bit of timer/counter A (timer/counter B) register Transfer Addition Logic AND Logic XOR Concatenation 8-bit RAM address 4-bit or 5-bit port address 6-bit interrupt latch Contents of bit assigned by bit 1 to 0 of LR Bit 3 to 2 of LR
Symbol LR DP STACK[SP] FLAG ZF IL PORT[p] RAM[x] ROM[DP]H [DP]M [TA]L([TB]L) [TA]H([TB]H) --
Description L register Data pointer Stack specified by SP All flags Zero flag Interrupt latch Port ( address : p ) Timer/counter B Data memory (address : x ) High 4-bit of program memory Middle 4-bit of data pointer register Low 4-bit of timer/counter A (timer/counter B) register High 4-bit of timer/counter A (timer/counter B) register Exchange Substraction Logic OR Inverse operation 4-bit immediate data 4-bit zero-page address Bit address Bit 11 to 6 of program counter Bit 5 to 0 of destination address for branch instruction
' #k y b PC11-6 a5-0
* This specification are subject to be changed without notice.
11.30.2001
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