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EL5525
Data Sheet August 1, 2005 FN7393.1
PRELIMINARY
18-Channel TFT-LCD Reference Voltage Generator
The EL5525 is designed to produce the reference voltages required in TFT-LCD applications. Each output is programmed to the required voltage with 10 bits of resolution. Reference pins determine the high and low voltages of the output range, which are capable of swinging to either supply rail. Programming of each output is performed using the serial interface. A serial out pin enables daisy chaining of multiple devices. A number of the EL5525 can be stacked for applications requiring more than 18 outputs. The reference inputs can be tied to the rails, enabling each part to output the full voltage range, or alternatively, they can be connected to external resistors to split the output range and enable finer resolutions of the outputs. The EL5525 has 18 outputs and comes in a 38-pin HTSSOP package. It is specified for operation over the full -40C to +85C temperature range.
Features
* 18-channel reference outputs * Accuracy of 0.1% * Supply voltage of 4.5V to 16.5V * Digital supply 3.3V to 5V * Low supply current of 15mA * Rail-to-rail capability * Internal thermal protection * Pb-Free plus anneal available (RoHS compliant)
Applications
* TFT-LCD drive circuits * Reference voltage generators
Pinout
EL5525 (38-PIN HTSSOP) TOP VIEW
ENA 1 38 OUTA 37 OUTB 36 OUTC 35 GND 34 OUTD 33 OUTE 32 OUTF 31 OUTG 30 OUTH THERMAL PAD 29 OUTI 28 GND 27 OUTJ 26 OUTK 25 OUTL 24 GND 23 OUTM 22 OUTN 21 OUTO 20 OUTP
Ordering Information
PART NUMBER EL5525IRE EL5525IRE-T7 EL5525IRE-T13 EL5525IREZ (See Note) EL5525IREZ-T7 (See Note) PACKAGE 38-Pin HTSSOP 38-Pin HTSSOP 38-Pin HTSSOP 38-Pin HTSSOP (Pb-Free) 38-Pin HTSSOP (Pb-Free) TAPE & REEL 7" 13" 7" 13" PKG. DWG. # MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048
SDI 2 SCLK 3 SDO 4 EXT_OSC 5 VS 6 VSD 7 NC 8 NC 9 OSC_SELECT 10 VS 11 REFH 12 REFL 13 GND 14 CAP 15 VS 16 NC 17 OUTR 18 OUTQ 19
EL5525IREZ-T13 38-Pin HTSSOP (See Note) (Pb-Free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004-2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL5525
Absolute Maximum Ratings (TA = 25C)
Supply Voltage between VS and GND. . . . . . 4.5V(min) to 18V(max) Supply Voltage between VSD and GND 3V(min) to VS and +7(max) Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER SUPPLY IS ISD ANALOG VOL VOH ISC PSRR tD VAC VMIS VDROOP RINH REG BG DIGITAL VIH VIL FCLK tS tH tLC tCE tDCO RSDIN TPULSE Duty Cycle F_OSC INL DNL Supply Current
VS = 15V, VSD = 5V, VREFH = 13V, VREFL = 2V, RL = 1.5k and CL = 200pF to 0V, TA = 25C, unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
No load
15 0.17
18 0.35
mA mA
Digital Supply Current
Output Swing Low Output Swing High Short Circuit Current Power Supply Rejection Ratio Program to Out Delay Accuracy Referred to the Ideal Value Channel to Channel Mismatch Droop Voltage Input Resistance @ VREFH, VREFL Load Regulation Band Gap
Sinking 5mA (VREFH = 15V, VREFL = 0) Sourcing 5mA (VREFH = 15V, VREFL = 0) RL = 10 VS+ is moved from 14V to 16V 14.85 100 45
50 14.95 140 60 4
150
mV V mA dB ms mV mV
Code = 512 Code = 512
20 2 1 34 2
mV/ms k
IOUT = 5mA step 1.1
0.5 1.3
1.5 1.6
mV/mA V
Logic 1 Input Voltage Logic 0 Input Voltage Clock Frequency Setup Time Hold Time Load to Clock Time Clock to Load Line Clock to Out Delay Time SDIN Input Resistance Minimum Pulse Width for EXT_OSC Signal Duty Cycle for EXT_OSC Signal Internal Refresh Oscillator Frequency Integral Nonlinearity Error Differential Nonlinearity Error OSC_Select = 0 Negative edge of SCLK
2 1 5 20 20 20 20 10 1 5 50 21 1.3 0.5
V V MHz ns ns ns ns ns G s % kHz LSB LSB
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FN7393.1 August 1, 2005
EL5525 Pin Descriptions
PIN NUMBER 1 2 3 4 5 6, 11, 16 7 8, 9, 17 10 12 13 14, 24, 28, 35 15 18 19 20 21 22 23 25 26 27 29 30 31 32 33 34 36 37 38 PIN NAME ENA SDI SCLK SDO EXT_OSC VS VSD NC OSC_SELECT REFH REFL GND CAP OUTR OUTQ OUTP OUTO OUTN OUTM OUTL OUTK OUTJ OUTI OUTH OUTG OUTF OUTE OUTD OUTC OUTB OUTA Analog Input Analog Input Power Analog Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output PIN TYPE Logic Input Logic Input Logic Input Logic Output Input/Output Power Power PIN DESCRIPTION Chip select, low enables data input to logic Serial data input Serial data clock Serial data output Oscillator pin for synchronizing Positive supply voltage for analog circuits (4.5V - 16.5V) Positive power supply for digital circuites (3.3V - 5V) Not connected Oscillator select, "0" = internal, "1" = external High reference voltage Low reference voltage Ground Decoupling capacitor for internal reference Channel R output voltage Channel Q output voltage Channel P output voltage Channel O output voltage Channel N output voltage Channel M output voltage Channel L output voltage Channel K output voltage Channel J output voltage Channel I output voltage Channel H output voltage Channel G output voltage Channel F output voltage Channel E output voltage Channel D output voltage Channel C output voltage Channel B output voltage Channel A output voltage
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EL5525 Typical Performance Curves
DIFFERENTIAL NONLINEARITY (LSB) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 10 VS=15V VSD=5V 210 VREFH=13V VREFL=2V 410 610 810 1010 INL (LSB) 0.5 REFH=13V, REFL=2V 1.5
1
0 -0.5
-1 0 200 400 600 CODE 800 1000 1200
INPUT CODE
FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE
FIGURE 2. INTEGRAL NONLINEARITY ERROR
VS=VREFH=15V
VS=VREFH=15V
0mA 5mA CL=4.7nF RS=20 5V
5mA/DIV
5mA 0mA CL=1nF RS=20 5mA/DIV
200mV/DIV CL=1nF RS=20 CL=180pF M=400ns/DIV CL=180pF M=400ns/DIV CL=4.7nF RS=20
200mV/DIV
FIGURE 3. TRANSIENT LOAD REGULATION (SOURCING)
FIGURE 4. TRANSIENT LOAD REGULATION (SINKING)
SCLK
SCLK SDA ENA OUTA
SDA ENA
OUTA M=200s/DIV M=200s/DIV
FIGURE 5. LARGE SIGNAL RESPONSE (RISING FROM 0V TO 8V)
FIGURE 6. SMALL SIGNAL RESPONSE (FALLING FROM 200mV TO 100mV)
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EL5525 General Description
The EL5525 provides a versatile method of providing the reference voltages that are used in setting the transfer characteristics of LCD display panels. The V/T (Voltage/Transmission) curve of the LCD panel requires that a correction is applied to make it linear; however, if the panel is to be used in more than one application, the final curve may differ for different applications. By using the EL5525, the V/T curve can be changed to optimize its characteristics according to the required application of the display product. Each of the eight reference voltage outputs can be set with a 10-bit resolution. These outputs can be driven to within 50mV of the power rails of the EL5525. As all of the output buffers are identical, it is also possible to use the EL5525 for applications other than LCDs where multiple voltage references are required that can be set to 10 bit accuracy. chip. While the ENA is held low, the 16m-bit data is loaded to the SDI input of the first chip. The first 16-bit data will go to the last chip and the last 16-bit data will go to the first chip. While the ENA is held high, all addressed outputs will be updated simultaneously. The Serial Timing Diagram and parameters table show the timing requirements for three-wire signals. The serial data has a minimum length of 16 bits, the MSB (most significant bit) is the first bit in the signal. The bits are allocated to the following functions (also refer to the Control Bits Logic Table) * Bit 15 is always set to a zero * Bits 14 through 10 select the channel to be written to, these are binary coded with channel A = 0, and channel R = 17 * The 10-bit data is on bits 9 through 0. Some examples of data words are shown in the table of Serial Programming Examples
TABLE 1. CONTROL BITS LOGIC TABLE BIT B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 NAME Test A4 A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION Always 0 Channel Address Channel Address Channel Address Channel Address Channel Address Data Data Data Data Data Data Data Data Data Data
Digital Interface
The EL5525 uses a simple 3-wire SPI compliant digital interface to program the outputs. The EL5525 can support the clock rate up to 5MHz.
Serial Interface
The EL5525 is programmed through a three-wire serial interface. The start and stop conditions are defined by the ENA signal. While the ENA is low, the data on the SDI (serial data input) pin is shifted into the 16-bit shift register on the positive edge of the SCLK (serial clock) signal. The MSB (bit 15) is loaded first and the LSB (bit 0) is loaded last (see Table 1). After the full 16-bit data has been loaded, the ENA is pulled high and the addressed output channel is updated. The SCLK is disabled internally when the ENA is high. The SCLK must be low before the ENA is pulled low. To facilitate the system designs that use multiple EL5525 chips, a buffered serial output of the shift register (SDO pin) is available. Data appears on the SDO pin at the 16th falling SCLK edge after being applied to the SDI pin. To control the multiple EL5525 chips from a single three-wire serial port, just connect the ENA pins and the SCLK pins together, connect the SDO pin to the SDI pin on the next
Serial Timing Diagram
ENA
tHE
tSE
T
tr
tf
tHE
tSE
SCLK tSD tHD tw
SDI
B15 MSB
B14
B13
B12-B2
B1
B0 t LSB
LOAD MSB FIRST, LSB LAST
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EL5525
TABLE 2. SERIAL TIMING PARAMETERS PARAMETER T tr/tf tHE tSE tHD tSD tW RECOMMENDED OPERATING RANGE 200ns 0.05 * T 10ns 10ns 10ns 10ns 0.50 * T Clock Period Clock Rise/Fall Time ENA Hold Time ENA Setup Time Data Hold Time Data Setup Time Clock Pulse Width DESCRIPTION
TABLE 3. SERIAL PROGRAMMING EXAMPLES CONTROL C1 0 0 0 0 0 0 0 0 0 0 0 1 CHANNEL ADDRESS A4 A3 0 0 0 0 0 0 A2 0 0 0 0 1 0 A1 0 0 0 1 1 0 A0 0 0 0 1 1 1 D9 0 1 1 1 0 0 D8 0 1 0 0 0 0 D7 0 1 0 0 0 0 D6 0 1 0 0 0 0 DATA D5 0 1 0 0 0 0 D4 0 1 0 0 1 1 D3 0 1 0 0 1 1 D2 0 1 0 0 1 1 D1 0 1 0 0 1 1 D0 0 1 0 1 1 1 CONDITION Channel A, Value = 0 Channel A, Value = 1023 Channel A, Value = 512 Channel C, Value = 513 Channel H, Value = 31 Channel R, Value = 31
Analog Section
TRANSFER FUNCTION The transfer function is:
data V OUT ( IDEAL ) = V REFL + ------------ x ( V REFH - V REFL ) 1024
where data is the decimal value of the 10-bit data binary input code. The output voltages from the EL5525 will be derived from the reference voltages present at the VREFL and VREFH pins. The impedance between those two pins is about 32k. Care should be taken that the system design holds these two reference voltages within the limits of the power rails of the EL5525. GND < VREFH VS and GND VREFL VREFH. CLOCK OSCILLATOR The EL5525 requires an internal clock or external clock to refresh its outputs. The outputs are refreshed at the falling OSC clock edges. The output refreshed switches open at the rising edges of the OSC clock. The driving load shouldn't be changed at the rising edges of the OSC clock. Otherwise, it will generate a voltage error at the outputs. This clock may be input or output via the clock pin labeled EXT_OSC. The internal clock is provided by an internal oscillator running at approximately 21kHz and can be output to the EXT_OSC pin. In a 2 chip system, if the driving loads are stable, one chip may be programmed to use the internal oscillator; then the OSC pin will output the clock from the internal oscillator. The second chip may have the OSC pin connected to this clock source.
For transient load application, the external clock Mode should be used to ensure all functions are synchronized together. The positive edge of the external clock to the OSC pin should be timed to avoid the transient load effect. The Application Drawing shows the LCD H rate signal used, here the positive clock edge is timed to avoid the transient load of the column driver circuits. After power on, the chip will start with the internal oscillator mode. At this time, the EXT_OSC pin will be in a high impedance condition to prevent contention. By setting pin 10 to high, the chip is on external clock mode. Setting pin 10 to low, the chip is on internal clock mode.
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EL5525 Block Diagram
REFH
OUTA OUTB OUTC OUTD 18 CHANNEL REGISTERS VOLTAGE SOURCES OUTE OUTP OUTQ OUTR REFL CAP SDI SCLK ENA CONTROL IF SDO
OSC_SELECT
EXT_OSC
CHANNEL OUTPUTS Each of the channel outputs has a rail-to-rail buffer. This enables all channels to have the capability to drive to within 50mV of the power rails, (see Electrical Characteristics for details). When driving large capacitive loads, a series resistor should be placed in series with the output. (Usually between 5 and 50). Each of the channels is updated on a continuous cycle, the time for the new data to appear at a specific output will depend on the exact timing relationship of the incoming data to this cycle. The best-case scenario is when the data has just been captured and then passed on to the output stage immediately; this can be as short as 48s. In the worst-case scenario, this will be 860s for EL5525, when the data has just missed the cycle at f_OSC = 21kHz. When a large change in output voltage is required, the change will occur in 2V steps, thus the requisite number of timing cycles will be added to the overall update time. This means that a large change of 16V can take between 6.8ms and 7.2ms depending on the absolute timing relative to the update cycle. 7
Output Stage and the Use of External Oscillator
Simplified output sample and hold amp stage for one channel
CH 1.3V + S1 1.3V S2 OSC
+ -
VOUT
VIN
+ -
FIGURE 7.
The output voltage is generated from the DAC, which is VIN in the above circuit. The refreshed switches are controlled by the internal or external oscillator signal. When the OSC clock signal is low, switches S1 and S2 are closed. The output VOUT = VIN and at the same time the sample and hold cap CH is being charged. When the OSC clock signal is high, the refreshed switches S1 and S2 are opened and the output voltage is maintained by CH. This refreshed process will repeat every 18 clock cycles for each channel. The time takes to update the output depends on the timing at the VIN
FN7393.1 August 1, 2005
EL5525
and the state of the switches. It can take 1 to 18 clock cycles to update each output. For the sample and hold capacitor CH to maintain the correct output voltage, the driving load shouldn't be changed at the rising edge of the OSC signal. Since at the rising edge of the OSC clock, the refreshed switches are being opened, if the load changes at that time, it will generate an error output voltage. For a fixed load condition, the internal oscillator can be used. For the transient load condition, the external OSC mode should be used to avoid the conflict between the rising edge of the OSC signal and the changing load. So a timing delay circuit will be needed to delay the OSC signal and avoid the rising edge of the OSC signal and changing the load at the same time. TRANSIENT LOAD RESPONSE CHANNEL TO CHANNEL REFRESH
FIGURE 9.
Ch1 --- Output1 Ch3 --- Output2 Ch2 --- EXT_OSC At the falling edge of the OSC, output 1 is being refreshed and one clock cycle later, output 2 is being refreshed. The spike you see here is the response of the output amplifier when the refreshed switches are closed. When driving a big capacitor load, there will be ringing at the spikes because the phase margin of the amplifier is decreased. The speed of the external OSC signal shouldn't be greater than 70kHz because for the worst condition, it will take at least 4s to charge the sample and hold capacitor CH. The pulse width has to be at least 4s long. From our lab test, the duty cycle of the OSC signal must be greater than 30%. POWER DISSIPATION With the 30mA maximum continues output drive capability for each channel, it is possible to exceed the 125C absolute maximum junction temperature. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the part to remain in the safe operation. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA
FIGURE 8.
Channel 3 --- sinking and sourcing 5mA current Channel 2 --- EXT_OSC signal Channel 1 --- VOUT Here, the OSC signal is synchronized to the load signal. The rising edge of the OSC signal is then delayed by some amount of time and gives enough time for CH to be charged to a new voltage before the switches are opened.
where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation in the package
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EL5525
The maximum power dissipation actually produced by the IC is the total quiescent supply current times the total power supply voltage and plus the power in the IC due to the loads.
P DMAX = V S x I S + [ ( V S - V OUT i ) x I LOAD i ]
THERMAL SHUTDOWN The EL5525 has an internal thermal shutdown circuitry that prevents overheating of the part. When the junction temperature goes up to about 150C, the part will be disabled. When the junction temperature drops down to about 120C, the part will be enabled. With this feature, any short circuit at the outputs will enable the thermal shutdown circuitry to disable the part. POWER SUPPLY BYPASSING AND PRINTED CIRCUIT BOARD LAYOUT Good printed circuit board layout is necessary for optimum performance. A low impedance and clean analog ground plane should be used for the EL5525. The traces from the two ground pins to the ground plane must be very short. The thermal pad of the EL5525 should be connected to the analog ground plane. Lead length should be as short as possible and all power supply pins must be well bypassed. A 0.1F ceramic capacitor must be place very close to the VS, VREFH, VREFL, and CAP pins. A 4.7F local bypass tantalum capacitor should be placed to the VS, VREFH, and VREFL pins.
when sourcing, and:
P DMAX = V S x I S + ( V OUT i x I LOAD i )
when sinking. Where: * i = 18 * VS = Supply voltage * IS = Quiescent current * VOUTi = Output voltage of the i channel * ILOADi = Load current of the i channel By setting the two PDMAX equations equal to each other, we can solve for the RLOADs to avoid the device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat.
Application Drawing
+10V
HIGH REFERENCE VOLTAGE 0.1F +12V 0.1F
REFH
OUTA
COLUMN (SOURCE) DRIVER
VS
OUTB
MICROCONTROLLER
+5V 0.1F
VSD
OUTC
LCD PANEL
OUTD SDI SCK LCD TIMING CONTROLLER HORIZONTAL RATE ENA SDO OSC CAP 0.1F +1V 0.1F 5V OSC_SET OUTQ REFL GND OUTR OUTF OUTE
EL5525
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FN7393.1 August 1, 2005
-HTSSOP
Package Outline Drawing
10
EL5525
FN7393.1 August 1, 2005
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
EL5525
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN7393.1 August 1, 2005

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