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EL5176
Data Sheet August 3, 2005 FN7343.2
250MHz Differential Twisted-Pair Driver
The EL5176 is a high bandwidth amplifier with an output in differential form. It is primarily targeted for applications such as driving twisted-pair lines or any application where common mode injection is likely to occur. The input signal can be in either single-ended or differential form but the output is always in differential form. On the EL5176, two feedback inputs provide the user with the ability to set the device gain (stable at minimum gain of one). The output common mode level is set by the reference pin (REF), which has a -3dB bandwidth of over 50MHz. Generally, this pin is grounded but it can be tied to any voltage reference. Both outputs (OUT+, OUT-) are short circuit protected to withstand temporary overload condition. The EL5176 is available in the 10-pin MSOP package and is specified for operation over the full -40C to +85C temperature range. See also EL5171 (EL5176 in 8-pin MSOP.)
Features
* Fully differential inputs, outputs, and feedback * Differential input range 2.3V * 250MHz 3dB bandwidth * 800V/s slew rate * Low distortion at 20MHz * Single 5V or dual 5V supplies * 40mA maximum output current * Low power - 8mA typical supply current * Pb-Free plus anneal available (RoHS compliant)
Applications
* Twisted-pair drivers * Differential line drivers * VGA over twisted-pair * ADSL/HDSL drivers * Single ended to differential amplification * Transmission of analog signals in a noisy environment
Ordering Information
PART NUMBER EL5176IY EL5176IY-T7 EL5176IY-T13 EL5176IYZ (See Note) EL5176IYZ-T7 (See Note) EL5176IYZ-T13 (See Note) PACKAGE 10-Pin MSOP 10-Pin MSOP 10-Pin MSOP 10-Pin MSOP (Pb-free) 10-Pin MSOP (Pb-free) 10-Pin MSOP (Pb-free) TAPE & REEL 7" 13" 7" 13" PKG. DWG. # MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043
Pinout
EL5176 (10-PIN MSOP) TOP VIEW
FBP 1 IN+ 2 REF 3 IN- 4 FBN 5 + 10 OUT+ 9 VS8 VS+ 7 EN 6 OUT-
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003-2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL5176
Absolute Maximum Ratings (TA = 25C)
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER AC PERFORMANCE BW -3dB Bandwidth
VS+ = +5V, VS- = -5V, TA = 25C, VIN = 0V, RLD = 1k, RF = 0, RG = OPEN, CLD = 2.7pF, Unless Otherwise Specified DESCRIPTION CONDITIONS MIN TYP MAX UNIT
AV = 1, CLD = 2.7pF AV = 2, RF = 500, CLD = 2.7pF AV = 10, RF = 500, CLD = 2.7pF
250 60 10 50 600 540 800 700 10 20 100 1000 1000
MHz MHz MHz MHz V/s V/s ns ns MHz MHz V/s V/s nV/Hz pA/Hz dBc dBc dBc dBc %
BW SR
0.1dB Bandwidth Slew Rate - Rise Slew Rate - Fall
AV = 1, CLD = 2.7pF VOUT = 3VP-P, 20% to 80% VOUT = 3VP-P, 20% to 80% VOUT = 2VP-P
TSTL TOVR GBWP
Settling Time to 0.1% Output Overdrive Recovery Time Gain Bandwidth Product
VREFBW (-3dB) VREF -3dB Bandwidth VREFSR+ VREFSRVN IN HD2 VREF Slew Rate - Rise VREF Slew Rate - Fall Input Voltage Noise Input Current Noise Second Harmonic Distortion
AV =1, CLD = 2.7pF VOUT = 2VP-P, 20% to 80% VOUT = 2VP-P, 20% to 80% at 10kHz at 10kHz VOUT = 2VP-P, 5MHz VOUT = 2VP-P, 20MHz
50 90 50 26 2 -94 -94 -77 -75 0.1 0.5
HD3
Third Harmonic Distortion
VOUT = 2VP-P, 5MHz VOUT = 2VP-P, 20MHz
dG d
Differential Gain at 3.58MHz Differential Phase at 3.58MHz
RL = 300, AV = 2 RL = 300, AV = 2
INPUT CHARACTERISTICS VOS IIN IREF RIN CIN DMIR CMIR+ CMIRVREFIN+ VREFINVREFOS Input Referred Offset Voltage Input Bias Current (VIN+, VIN-) Input Bias Current (VREF) Differential Input Resistance Differential Input Capacitance Differential Mode Input Range Common Mode Positive Input Range at VIN+, VINCommon Mode Negative Input Range at VIN+, VINPositive Reference Input Voltage Range Negative Reference Input Voltage Range Output Offset Relative to VREF VIN+ = VIN- = 0V VIN+ = VIN- = 0V 3.5 2.1 3.1 -14 0.5 1.5 -6 1.3 300 1 2.3 3.4 -4.5 3.8 -3.3 60 -3 100 -4.2 2.5 25 -3 4 mV A A k pF V V V V V mV
FN7343.2 August 3, 2005
2
EL5176
Electrical Specifications
PARAMETER CMRR Gain VS+ = +5V, VS- = -5V, TA = 25C, VIN = 0V, RLD = 1k, RF = 0, RG = OPEN, CLD = 2.7pF, Unless Otherwise Specified (Continued) DESCRIPTION Input Common Mode Rejection Ratio Gain Accuracy CONDITIONS VIN = 2.5V VIN = 1 MIN 65 0.981 TYP 82 0.996 1.011 MAX UNIT dB V
OUTPUT CHARACTERISTICS VOUT Positive Output Swing Negative Output Swing IOUT(Max) Maximum Source Output Current Maximum Sink Output Current RL = 10, VIN+ = 1.1V, VIN- = -1.1V, VREF = 0 35 RL = 500 to GND 3.6 3.9 -3.8 50 -40 -30 -3.5 V V mA mA
ROUT SUPPLY VSUPPLY IS(ON) IS(OFF)+ IS(OFF)PSRR ENABLE tEN tDS VIH VIL IIH-EN IIL-EN
Output Impedance
130
m
Supply Operating Range Power Supply Current - Per Channel Positive Power Supply Current - Disabled Negative Power Supply Current - Disabled Power Supply Rejection Ratio
VS+ to VS-
4.75 6.8 7.5 80 -200 -120 84
11 8.2 120
V mA A A dB
EN pin tied to 4.8V
VS from 4.5V to 5.5V
70
Enable Time Disable Time EN Pin Voltage for Power-Up EN Pin Voltage for Shut-Down EN Pin Input Current High EN Pin Input Current Low At VEN = 5V At VEN = 0V -6 VS+ 0.5
215 0.95 VS+ 1.5
ns s V V
40 -2.5
60
A A
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 PIN NAME FBP IN+ REF INFBN OUTEN VS+ VSOUT+ PIN DESCRIPTION Non-inverting feedback input; resistor RF1 must be connected from this pin to VOUT Non-inverting input Output common-mode control; the common-mode voltage of VOUT will follow the voltage on this pin Inverting input Inverting feedback input; resistor RF2 must be connected from this pin to VOUT Inverting output Enabled when this pin is floating or the applied voltage VS+ -1.5 Positive supply Negative supply Non-inverting output
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FN7343.2 August 3, 2005
EL5176 Connection Diagram
RF1 VREF 0 RS3 50 INP RS1 50 INNRS2 50 1 FBP 2 IN+ RG OPEN 3 REF 4 IN5 FBN RF2 0 OUT+ 10 VS- 9 VS+ 8 EN 7 OUT- 6 -5V +5V RLD 1k EN OUTOUT+
Typical Performance Curves
AV = 1, RLD = 1k, CLD = 2.7pF 4 NORMALIZED MAGNITUDE (dB) 3 2 MAGNITUDE (dB) 1 0 -1 -2 -3 -4 -5 -6 1M 10M 100M 1G VOP-P = 1VP-P VOP-P = 200mV 4 3 2 1 0 -1 -2 -3 -4 -5 -6 1M 10M 100M 1G AV = 10 AV = 5 AV = 2 AV = 1 RLD = 1k, CLD = 2.7pF
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS GAIN
AV = 1, CLD = 2.7pF 4 3 NORMINALIZED GAIN (dB) 2 1 0 -1 -2 -3 -4 -5 -6 1M 10M 100M 1G RLD = 200 RLD = 1k RLD = 500 MAGNITUDE (dB) 5 4 3 2 1 0 -1 -2 -3 -4
AV = 1, RLD = 1k CLD = 56pF CLD = 34pF CLD = 23pF
CLD = 9pF CLD = 2.7pF
-5 1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. FREQUENCY RESPONSE vs RLD
FIGURE 4. FREQUENCY RESPONSE vs CLD
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FN7343.2 August 3, 2005
EL5176 Typical Performance Curves
AV = 2, RLD = 1k, CLD = 2.7pF 10 9 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 8 7 6 5 4 3 2 1 0 1M 10M FREQUENCY (Hz) 100M 400M RF = 200 RF = 500 RF = 1k 10 9 8 7 6 5 4 3 2 1 0 1M 10M FREQUENCY (Hz) 100M 400M RLD = 200 RLD = 500 RLD = 1k
(Continued)
AV = 2, RF = 1k, CLD = 2.7pF
FIGURE 5. FREQUENCY RESPONSE
FIGURE 6. FREQUENCY RESPONSE vs RLD
5 4 3 MAGNITUDE (dB) 2 1 0 -1 -2 -3 -4 -5 100K 1M 10M FREQUENCY (Hz) 100M IMPEDENCE ()
100
10
1
0.1 10K
100K
1M FREQUENCY (Hz)
10M
100M
FIGURE 7. FREQUENCY RESPONSE - VREF
FIGURE 8. OUTPUT IMPEDANCE vs FREQUENCY
0 -10 -20 CMRR (dB) PSRR+ PSRR (dB) -30 -40 -50 -60 -70 -80 -90 1K 10K 100K 1M 10M 100M PSRR-
100 90 80 70 60 50 40 30 20 10 0 100K 1M 10M FREQUENCY (Hz) 100M 1G
FREQUENCY (Hz)
FIGURE 9. PSRR vs FREQUENCY
FIGURE 10. CMRR vs FREQUENCY
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FN7343.2 August 3, 2005
EL5176 Typical Performance Curves
1K VOLTAGE NOISE (nV/Hz), CURRENT NOISE (pA/Hz)
(Continued)
VS = 5V, AV = 1, RLD = 1k -50 -55 -60 DISTORTION (dB)
100 EN 10 IN 1 10 100 1K 10K 100K 1M 10M
-65 -70 -75 -80 -85 -90 -95 -100 1 1.5 2 2.5 3
HD3 (f = 5MHz)
HD3 (f = 20MHz)
HD2 (f
= 20M
Hz )
(f HD2
= 5M
Hz)
3.5
4
4.5
5
FREQUENCY (Hz)
VOP-P, DM (V)
FIGURE 11. VOLTAGE AND CURRENT NOISE vs FREQUENCY
FIGURE 12. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE
VS = 5V, AV = 1, RLD = 1k -50 -50 -55 -60 DISTORTION (dB) -65 -70 -75 -80 -85 -90 -95 1 2
Hz) HD2 (f = 5M
HD2 (f = 20MHz)
HD3 (f = 20MH z)
VS = 5V, AV = 1, VOP-P, DM = 1V -55
HD3 (f = 5MHz) DISTORTION (dB)
-60 -65 -70 -75 -80 -85 -90 -95
HD
3
(f =
HD 3
20 M Hz )
(f
=
5M Hz )
HD
2 (f
HD2 (f
Hz ) = 5M Hz)
=2
0M
3
4
5
6
7
8
9
10
-100 100
200
300
400
500
600
700
800
900 1000
VOP-P, DM (V)
RLD ()
FIGURE 13. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE
FIGURE 14. HARMONIC DISTORTION vs RLD
VS = 5V, AV = 2, VOP-P, DM = 2V -40 -50 DISTORTION (dB) -60 -70 -80 -90
HD2 (f = 20M H z)
-40 HD3 (f = 20MHz) HD3 (f = 5MHz) DISTORTION (dB) -50 -60 -70 -80 -90 -100 300 400 500 600 RLD () 700 800 900 1000
VS = 5V, RLD = 1k, VOP-P, DM = 1V for AV = 1, VOP-P, DM = 2V for AV = 2 HD3 (AV = 1)
3 HD
(AV
) =2
HD2 (AV =
2)
HD2 (AV
= 1)
HD2 (f = 5MHz)
-100 200
0
10
20
30
40
50
60
FREQUENCY (MHz)
FIGURE 15. HARMONIC DISTORTION vs RLD
FIGURE 16. HARMONIC DISTORTION vs FREQUENCY
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FN7343.2 August 3, 2005
EL5176 Typical Performance Curves
(Continued)
50mV/DIV
0.5V/DIV
10ns/DIV
10ns/DIV
FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE
M = 100ns, CH1 = 500mV/DIV, CH2 = 5V/DIV
M = 200ns, CH1 = 500mV/DIV, CH2 = 5V/DIV
CH1 CH2
CH1
CH2
100ns/DIV
200ns/DIV
FIGURE 19. ENABLED RESPONSE
FIGURE 20. DISABLED RESPONSE
0.6 POWER DISSIPATION (W) 0.5
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
1 0.9 POWER DISSIPATION (W) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
870mW MSOP8/10 JA=115C/W
486mW 0.4 0.3 0.2 0.1 0 0 25 50
MSOP8/10 JA=206C/W
75 85
100
125
0
25
50
75 85
100
125
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN7343.2 August 3, 2005
EL5176 Simplified Schematic
VS+ R3 R7 R4 R8
R1
R2
IN+
IN-
FBP
FBN
VB1
OUT+ RCD RCD REF R9 R10
CC
VB2 CC R5 VSR6
OUT-
Description of Operation and Application Information
Product Description
The EL5176 is a wide bandwidth, low power and single/differential ended to differential output amplifier. It can be used as single/differential ended to differential converter. The EL5176 is internally compensated for closed loop gain of +1 of greater. Connected in gain of 1 and driving a 1k differential load, the EL5176 has a -3dB bandwidth of 250MHz. Driving a 200 differential load at gain of 2, the bandwidth is about 30MHz. The EL5176 is available with a power down feature to reduce the power while the amplifier is disabled.
The gain setting for EL5176 is:
R F1 + R F2 V ODM = V IN + x 1 + --------------------------- RG 2R F V ODM = ( V IN + - V IN - ) x 1 + ---------- RG V OCM = V REF
Where: * RF1 = RF2 = RF
RF1
Input, Output, and Supply Voltage Range
The EL5176 has been designed to operate with a single supply voltage of 5V to 10V or a split supplies with its total voltage from 5V to 10V. The amplifier has an input common mode voltage range from -4.5V to 3.4V for 5V supply. The differential mode input range (DMIR) between the two inputs is from -2.3V to +2.3V. The input voltage range at the REF pin is from -3.3V to 3.8V. If the input common mode or differential mode signal is outside the above-specified ranges, it will cause the output signal distorted. The output of the EL5176 can swing from -3.8V to +3.9V at 1k differential load at 5V supply. As the load resistance becomes lower, the output swing is reduced.
VIN+ VINVREF RG
FBP IN+ INREF FBN RF2 VOVO+
FIGURE 23.
Choice of Feedback Resistor and Gain Bandwidth Product
For applications that require a gain of +1, no feedback resistor is required. Just short the OUT+ pin to FBP pin and OUT- pin to FBN pin. For gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier's phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, RF has some maximum value that should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few Pico farad range
Differential and Common Mode Gain Settings
The voltage applied at REF pin can set the output common mode voltage and the gain is one. The differential gain is set by the RF and RG network.
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FN7343.2 August 3, 2005
EL5176
in parallel with RF can help to reduce the ringing and peaking at the expense of reducing the bandwidth. The bandwidth of the EL5176 depends on the load and the feedback network. RF and RG appear in parallel with the load for gains other than +1. As this combination gets smaller, the bandwidth falls off. Consequently, RF also has a minimum value that should not be exceeded for optimum bandwidth performance. For gain of +1, RF = 0 is optimum. For the gains other than +1, optimum response is obtained with RF between 500 to 1k. The EL5176 has a gain bandwidth product of 100MHz for RLD = 1k. For gains 5, its bandwidth can be predicted by the following equation:
Gain x BW = 100MHz
40mA. This limit is set by the design of the internal metal interconnect.
Power Dissipation
With the high output drive capability of the EL5176. It is possible to exceed the 135C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX PD MAX = ------------------------------------------- JA
Driving Capacitive Loads and Cables
The EL5176 can drive 50pF differential capacitor in parallel with 1k differential load with less than 5dB of peaking at gain of +1. If less peaking is desired in applications, a small series resistor (usually between 5 to 50) can be placed in series with each output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than 1, the gain resistor RG can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking.
Where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or:
V O PD = V S x I SMAX + V S x ----------R
LD
Where: * VS = Total supply voltage * ISMAX = Maximum quiescent supply current per channel * VO = Maximum differential output voltage of the application * RLD = Differential load resistance * ILOAD = Load current By setting the two PDMAX equations equal to each other, we can solve the output current and RLD to avoid the device overheat.
Disable/Power-Down
The EL5176 can be disabled and placed its outputs in a high impedance state. The turn off time is about 0.95s and the turn on time is about 215ns. When disabled, the amplifier's supply current is reduced to 1.7A for IS+ and 120A for IStypically, thereby effectively eliminating the power consumption. The amplifier's power down can be controlled by standard CMOS signal levels at the ENABLE pin. The applied logic signal is relative to VS+ pin. Letting the EN pin float or applying a signal that is less than 1.5V below VS+ will enable the amplifier. The amplifier will be disabled when the signal at EN pin is above VS+ - 0.5V.
Power Supply Bypassing and Printed Circuit Board Layout
As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as sort as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7F tantalum capacitor in parallel with a 0.1F ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail.
Output Drive Capability
The EL5176 has internal short circuit protection. Its typical short circuit current is 40mA for EL5176. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds
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FN7343.2 August 3, 2005
EL5176
For good AC performance, parasitic capacitance should be kept to minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces.
Typical Applications
RF
FBP IN+ RT RG INREF FBN RF EL5176
50
TWISTED PAIR
IN+ EL5172
50 ZO = 100 INREF
VO
RFR RGR
FIGURE 24. TWISTED PAIR CABLE RECEIVER
As the signal is transmitted through a cable, the high frequency signal will be attenuated. One way to compensate this loss is to boost the high frequency gain at the receiver side.
RF Gain (dB)
FBP RT 75 RGC CL RG IN+ INREF FBN RF fL fH frequency VOVO+
2R F DC Gain = 1 + ---------RG 2R F ( HF )Gain = 1 + -------------------------R G || R GC
1 f L -----------------------2R G C C 1 f H ---------------------------2R GC C C FIGURE 25. TRANSMIT EQUALIZER
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FN7343.2 August 3, 2005
EL5176 MSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN7343.2 August 3, 2005

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