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CM1208-07/08 7 & 8-Channel High-Speed ESD Protection Arrays
Features
* * * * * * * Seven or eight channels of high-speed ESD protection Meets IEC-61000-4-2 Level 4 ESD protection requirements (+8kV contact discharge) Meets IEC-61000-4-2 +15kV air discharge requirements Low loading capacitance at 3pF typical Low supply and leakage currents - ideal for battery-powered devices Small MSOP-10 package Lead-free versions available
Product Description
The CM1208-07/CM1208-08 is a diode array designed to provide either 7 or 8 channels of ESD protection for electronic components or sub-systems. Each channel consists of a pair of diodes, which steers the ESD current pulse to either the positive (VP) or negative (VN) supply. The CM1208-07/08 devices will protect against ESD pulses up to 15kV contact discharge per the International Standard IEC61000-4-2. These devices are particularly well-suited for portable electronics (e.g.handheld and notebook computers) because of its small package footprint, high ESD protection level, and low loading capacitance. They are also suitable for protecting video output lines and I/O ports in computers, set top boxes, digital TVs and peripheral equipment. The CM1208-07/CM1208-08 is housed in a 10 pin MSOP package and is available with optional lead-free finishing.
Applications
* * * * * High speed data line ESD protection DVI ports High resolution video (e.g. VGA ports) Expansion ports for Notebook/Handheld Computers 5V pseudo RS-232 ports
Electrical Schematics
VN
CH7
VP
CH6
CH5
CH8
CH7
VP
CH6
CH5
CH1
CH2
CH3 CM1208-07
CH4
VN
CH1
CH2
CH3 CM1208-08
CH4
VN
(c) 2004 California Micro Devices Corp. All rights reserved. 02/02/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214
L Fax: 408.263.7846
L
www.calmicro.com
1
CM1208-07/08
PACKAGE / PINOUT DIAGRAMS
Top View
CH1 CH2 CH3 CH4 VN 1 2 3 4 5 10 9 8 7 6 VN CH7 VP CH6 CH5 CH1 CH2 CH3 CH4 VN
Top View
1 2 3 4 5 10 9 8 7 6 CH8 CH7 VP CH6 CH5
10-pin MSOP CM1208-07MS CM1208-07MR
Note: These drawings are not to scale.
10-pin MSOP CM1208-08MS CM1208-08MR
PIN DESCRIPTIONS
DEVICE -07,-08 -07,-08 -07,-08 -07,-08 -07,-08 -07,-08 -07,-08 -07,-08 -07,-08 -07 -08 PIN 1 2 3 4 5 6 7 8 9 10 10 NAME CH 1 CH 2 CH 3 CH 4 VN CH 5 CH 6 VP CH 7 VN CH 8 TYPE I/O I/O I/O I/O GND I/O I/O Supply I/O GND I/O DESCRIPTION ESD Channel ESD Channel ESD Channel ESD Channel Negative voltage supply rail or ground reference rail ESD Channel ESD Channel Positive voltage supply rail ESD Channel Negative voltage supply rail or ground reference rail ESD Channel
Ordering Information
PART NUMBERING INFORMATION
Standard Finish Pins 10 10 Package MSOP MSOP Ordering Part Number1 CM1208-07MS CM1208-08MS Part Marking 0807 0808 Lead-free Finish Ordering Part Number1 CM1208-07MR CM1208-08MR Part Marking 807R 808R
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
(c) 2004 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214
L Fax: 408.263.7846
L
www.calmicro.com
02/02/04
CM1208-07/08
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (VP - VN) Diode Forward DC Current (Note 1) Operating Temperature Range Storage Temperature Range DC Voltage at any channel input Package Power Rating MSOP Package
Note 1: Only one diode conducting at a time.
RATING 6.0 20 -40 to +85 -65 to +150 (VN - 0.5) to (VP + 0.5) 300
UNITS V mA C C V mW
STANDARD OPERATING CONDITIONS
PARAMETER Operating Temperature Range Operating Supply Voltage (VP - VN) RATING -40 to +85 0 to 5.5 UNITS C V
(c) 2004 California Micro Devices Corp. All rights reserved. 02/02/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L Tel: 408.263.3214
L
Fax: 408.263.7846
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CM1208-07/08
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
SYMBOL IP VF PARAMETER Supply Current Diode Forward Voltage Top Diode Bottom Diode Channel Leakage Current Channel Input Capacitance CONDITIONS (VP-VN)=5.0V IF = 20mA; TA=25C 0.60 0.65 TA=25C At 1 MHz, OSC Level = 30mV, VP=5V, VN=0V, VCH=2.5V; Note 2 applies 0.7 0.8 0.1 3 0.95 0.95 1.0 5 V V A pF MIN TYP MAX 10 UNITS A
ILEAK CIN
VESD
ESD Protection Peak Discharge Voltage at any channel input a) Contact discharge per IEC 61000-4-2 standard b) Human Body Model, MILSTD-883, Method 3015 Channel Clamp Voltage Positive Transients Negative Transients
Notes 2, 3 & 5 Notes 2, 3 & 4 At 8kV ESD HBM; TA=25C; Note 2, 3 & 4
8 15
kV kV
VCL
VP + 5.0 VN - 5.0
V V
Note 1: All parameters specified at TA=-40 to +85C unless otherwise noted. Note 2: These parameters guaranteed by design and characterization. Note 3: From I/O pins to VP or VN only. A bypass capacitor between VP and VN is required. It is recommended that VP be bypassed to VN with a 0.2F ceramic capacitor. Note 4: Human Body Model per MIL-STD-883, Method 3015, CDischarge = 100pF, RDischarge = 1.5K, VP = 5.0V, VN grounded. Note 5: Standard IEC 61000-4-2 with CDischarge = 150pF, RDischarge = 330, VP = 5.0V, VN grounded.
Performance Information
Typical Channel Input Capacitance vs. Channel Input Voltage at TA=25C
5
Input Capacitance (pF)
4
3
T y p ic a l V a r ia t io n o f C IN vs. VIN
2 1
(VP = 5V, VN = 0V, 0.2 F chip capacitor between VP and VN)
0 0 1 2 3 4 5
Input Voltage
(c) 2004 California Micro Devices Corp. All rights reserved.
4
430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214
L Fax: 408.263.7846
L
www.calmicro.com
02/02/04
CM1208-07/08
Application Information
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances on the Supply/ Ground rails as well as the signal trace segment between the signal input (typically a connector) and the ESD protection device. Refer to Figure 1, which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on the line being protected is:
VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt + L2 x d(IESD ) / dt
ance of the power supply respectively. As an example, a ROUT of 1 ohm would result in a 10V increment in VCL for a peak IESD of 10A. To mitigate these effects, a high frequency bypass capacitor should be connected between the VP pin of the ESD Protection Array and the ground plane. The value of this bypass capacitor should be chosen such that it will absorb the charge transferred by the ESD pulse with minimal change in VP. Typically a value in the 0.1F to 0.2F range is adequate for IEC-61000-42 level 4 contact discharge protection (8kV). For higher ESD voltages, the bypass capacitor should be increased accordingly. Ceramic chip capacitors mounted with short printed circuit board traces are good choices for this application. Electrolytic capacitors should be avoided as they have poor high frequency characteristics. For extra protection, connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series inductance inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher than the maximum supply voltage. As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ESD device to minimize stray series inductance.
where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1ns. Here d(IESD)/dt can be approximated by IESD/t, or 30/(1x10-9). So just 10nH of series inductance (L1 and L2 combined) will lead to a 300V increment in VCL! Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically increased negative voltage on the line being protected. Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies exhibit a much higher output impedance to fast transient current spikes. In the VCL equation above, the VSUPPLY term, in reality, is given by (VDC + IESD x ROUT), where VDC and ROUT are the nominal supply DC output voltage and effective output impedL2
VP
Additional Information
See also California Micro Devices Application Note AP209, "Design Considerations for ESD Protection."
POSITIVE SUPPLY RAIL
PATH OF ESD CURRENT PULSE IESD
D1
ONE CHANNEL OF CM1208
L1
CHANNEL INPUT
20A
LINE BEING PROTECTED
D2
SYSTEM OR CIRCUITRY BEING PROTECTED
VCL
GROUND RAIL
0A
VN
CHASSIS GROUND
Figure 1. Application of Positive ESD Pulse between Input Channel and Ground
(c) 2004 California Micro Devices Corp. All rights reserved. 02/02/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L Tel: 408.263.3214
L
Fax: 408.263.7846
L
www.calmicro.com
5
CM1208-07/08
Mechanical Details
MSOP Mechanical Specifications: CM1208-07/08 devices are packaged in 10-pin MSOP packages. Dimensions are presented below. For complete information on the MSOP-10 package, see the California Micro Devices MSOP Package Information document. Mechanical Package Diagrams
TOP VIEW
D
10 9 8 7 6
PACKAGE DIMENSIONS
Package Pins Dimensions A A1 B C D E e H L # per tube # per tape and reel 2.90 2.90 4.76 0.40 Millimeters Min 0.75 0.05 0.18 0.18 3.10 3.10 5.00 0.70 0.114 0.114 0.187 0.0137 4000 Controlling dimension: inches
* This is an approximate number which may vary.
MSOP 10 Inches Min 0.028 0.002 0.006 Max 0.038 0.006 0.016 0.007 0.122 0.122 0.197 0.029 Max 0.95 0.15 0.40
H
Pin 1 Marking
E
1
2
3
4
5
SIDE VIEW
A
SEATING PLANE
A1 B e
END VIEW
0.50 BSC
0.0196 BSC
80 pieces*
C
L
Package Dimensions for MSOP-10
(c) 2004 California Micro Devices Corp. All rights reserved.
6
430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214
L Fax: 408.263.7846
L
www.calmicro.com
02/02/04

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