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CDB4391A Evaluation Board for CS4391A
Features
Demonstrates recommended layout and grounding arrangements CS8414 receives AES/EBU, S/PDIF, & EIAJ-340 compatible digital audio Digital and analog patch areas Requires only a digital signal source and power supplies for a complete Digital-toAnalog (D/A) converter system
Description
The CDB4391A evaluation board is an excellent means for quickly evaluating the CS4391A 24-bit, stereo D/A converter. Evaluation requires an analog signal analyzer, a digital signal source, a PC for controlling the CS4391A (for control port mode only) and a power supply. Analog line level outputs are provided via RCA phono jacks. The CS8414 digital audio receiver IC provides the system timing necessary to operate the D/A converter and will accept AES/EBU, S/PDIF, and EIAJ-340 compatible audio data. The evaluation board may also be configured to accept external timing and data signals for operation in a user application during system development. ORDERING INFORMATION CDB4391A Evaluation Board
I/O for Clocks and Data
Control Port Channel A Output and Mute
CS8414 Digital Audio Interface
CS4391A Channel B Output and Mute
www.cirrus.com
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
MAY `03 DS600DB1 1
CDB4391A
TABLE OF CONTENTS
1. CDB4391A SYSTEM OVERVIEW ............................................................................................ 4 2. CS4391A DIGITAL TO ANALOG CONVERTER ..................................................................... 4 3. CS8414 DIGITAL AUDIO RECEIVER ...................................................................................... 4 4. CS8414 DATA FORMAT .......................................................................................................... 4 5. INPUT/OUTPUT FOR CLOCKS AND DATA ........................................................................... 5 6. POWER SUPPLY CIRCUITRY ................................................................................................. 5 7. GROUNDING AND POWER SUPPLY DECOUPLING ............................................................ 5 8. CONTROL PORT SOFTWARE ................................................................................................ 5 9. DSD OPERATION .................................................................................................................... 6 10. PACKING LIST FOR CDB4391A ......................................................................................... 22
LIST OF FIGURES
Figure 1. System Block Diagram and Signal Flow .......................................................................... 9 Figure 2. CS4391A and Level Shift ............................................................................................... 10 Figure 3. Channel B Audio Output and Mute Circuit ..................................................................... 11 Figure 4. Channel A Audio Output and Mute Circuit ..................................................................... 12 Figure 5. CS8414 Digital Audio Receiver...................................................................................... 13 Figure 6. Digital Audio Inputs ........................................................................................................ 14 Figure 7. Reset Circuit................................................................................................................... 15 Figure 8. Control Port Interface ..................................................................................................... 16 Figure 9. I/O for Clocks and Data.................................................................................................. 17 Figure 10. Power Supply ............................................................................................................... 18 Figure 11. Silkscreen Top ............................................................................................................. 19 Figure 12. Top Side....................................................................................................................... 20 Figure 13. Bottom Side.................................................................................................................. 21
LIST OF TABLES
Table 1. CS8414 Supported Formats.............................................................................................. 5 Table 2. System Connections ......................................................................................................... 6 Table 3. CDB4391A Jumper and Switch settings - STAND-ALONE MODE................................... 7 Table 4. CDB4391A Jumper and Switch settings - CONTOL PORT MODE .................................. 8
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DS600DB1
CDB4391A
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I2C is a registered trademark of Philips Semiconductor. Purchase of I2C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use those components in a standard I2C system.
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CDB4391A
1. CDB4391A SYSTEM OVERVIEW
The CDB4391A evaluation board is an excellent means of quickly evaluating the CS4391A. The CS8414 digital audio interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to supply clocks and data through a 10-pin header for system development. The CDB4391A schematic has been partitioned into 9 schematics shown in Figures 2 through 10. Each partitioned schematic is represented in the system diagram shown in Figure 1. Notice that the system diagram also includes the interconnections between the partitioned schematics.
2. CS4391A DIGITAL TO ANALOG CONVERTER
A description of the CS4391A is included in the CS4391A data sheet.
3. CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8414 Digital Audio Receiver, Figure 5. The outputs of the CS8414 include a serial bit clock, serial data, left-right clock (FSYNC), deemphasis control and a 256 Fs master clock. The operation of the CS8414 and a discussion of the digital audio interface are included in the CS8414 data sheet. During normal operation, the CS8414 operates in the Channel Status mode where the LED's display channel status information for the channel selected by the CSLR/FCK jumper. This allows the CS8414 to decode the de-emphasis bit from the digital audio interface for control of the CS4391A de-emphasis filter, when the CS4391A is in stand-alone mode. When the Error Information Switch is activated, the CS8414 operates in the Error and Frequency information mode. The information displayed by the LED's can be decoded by consulting the CS8414 data sheet. It is likely that the de-emphasis control for the CS4391A will be erroneous and produce an incorrect audio output if the Error Information Switch is activated and the CS4391A is in the stand-alone mode with internal serial clock mode selected. Encoded sample frequency information can be displayed provided a proper clock is being applied to the FCK pin of the CS8414. When an LED is lit, this indicates a "1" on the corresponding pin located on the CS8414. When an LED is off, this indicates a "0" on the corresponding pin. Neither the L nor R option of CSLR/FCK should be selected if the FCK pin is being driven by a clock signal. The evaluation board has been designed such that the input can be either optical or coax, see Figure 6. However, both inputs cannot be driven simultaneously.
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4. CS8414 DATA FORMAT
The CS8414 data format can be set with switches M0, M1, M2, and M3, as described in the CS8414 data sheet. The format selected must be compatible with the data format of the CS4391A, as shown in the CS4391A data sheet. Please note that the CS8414 does not support all the possible modes of the CS4391A and the Left-Justified Format for the CS8414 and the CS4391A have incompatible serial clocks, see Table 1. The default settings for M0-M3 on the evaluation board are given in Tables 3-4.
CS4391A CP Mode Format 0 1 2 3 4 5 CS4391A SA Mode Format 0 1 2 3 CS8414 Format Unsupported 2 5 Unsupported Unsupported 6
Table 1. CS8414 Supported Formats
5. INPUT/OUTPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to external systems via the 10-pin header, J9. This header allows the evaluation board to accept externally generated clocks and data. The schematic for the clock/data I/O is shown in Figure 9. The 74HC243 transceiver functions as an I/O buffer where HRD1 through HRD6 determine if the transceiver operates as a transmitter or receiver. A transmit function is implemented with all jumpers, HRD1 through HDR6 in the 8414 position. LRCK, SDATA, and SCLK from the CS8414 will be outputs on J9. The transceiver operates as a receiver with HRD1 through HDR6 in the EXT_CLK position. MCLK, LRCK, SDATA and SCLK on J9 become inputs.
6. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by six binding posts (GND, +5V(J6), +5V(J1), VL, VCC and VEE), see Figure 10. The +5V(J6) input supplies power to the +5 volt digital circuitry (V+5, VD+5, VDPC+5), while the VL input supplies power to the Voltage Level Converters and the CS4391A VL pin. +5V(J1) supplies power to the CS4391A. VCC and VEE supply power to the op-amp and can be +/-9 to +/-12 volts. WARNING: Refer to the CS4391A data sheet for maximum allowable voltages levels. Operation outside of this range can cause permanent damage to the device.
7. GROUNDING AND POWER SUPPLY DECOUPLING
The CS4391A requires careful attention to power supply and grounding arrangements to optimize performance. Figure 10 details the power distribution used on this board. The decoupling capacitors are located as close to the CS4391A as possible. Extensive use of ground plane fill in the evaluation board yields large reductions in radiated noise.
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CDB4391A
8. CONTROL PORT SOFTWARE
The CDB4391A is shipped with Windows based software for interfacing with the CS4391A control port via the DB25 connector, P1. The software can be used to communicate with the CS4391A in either SPI or I2C mode; however, in SPI mode the CS4391A registers are write-only. Note: The CDB4391A must be configured for control port mode as shown in Table 4. Further documentation for the software is available on the distribution diskette. The documentation is available in the plain text format file, README.TXT.
9. DSD OPERATION
The CDB4391A supports Direct Stream Digital (DSD) operation through the header for external clocks and data, J9. The CS4391A must be placed into the DSD mode and the jumpers HDR1 through HDR6 must be placed into the external clock positions.
CONNECTOR +5V (J6) +5V (J1) VL VEE VCC GND Coax Input Optical Input J9 Parallel Port HDR9 AOUTA AOUTB INPUT/OUTPUT Input Input Input Input Input Input Input Input Input/Output Input/Output Input/Output Output Output + 5 Volt power + 4.75 to + 5.25 Volt power for the CS4391A + 1.8 to +5.5 digital interface voltage (Note that VL should not exceed the voltage applied to the +5V J1 terminal) -12 to -9V negative supply for the op-amp +9 to +12V positive supply for the op-amp Ground connection from power supply Digital audio interface input via coax Digital audio interface input via optical I/O for master, serial, left/right clocks and serial data Parallel connection to PC for SPI / I2C control port signals I/O for SPI / I2C control port signals Channel A line level analog output Channel B line level analog output Table 2. System Connections SIGNAL PRESENT
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JUMPER / SWITCH SW1 - M0 SW1 - M1 SW1 - M2 SW1 - M3 SW1 CSLR/FCK HDR8 HDR7 ENCTRL M0/AD0/CS M1/SDA/CDIN M2/SCL/CCLK
PURPOSE CS8414 mode selection CS8414 mode selection CS8414 mode selection CS8414 mode selection Selects channel for CS8414 channel status information External mute for AOUTA External mute for AOUTB Enables / Disables parallel port CS4391A Mode Selection CS4391A Mode Selection CS4391A Mode Selection
POSITION *LO *HI *LO *LO *LO *ON OFF *ON OFF ENABLE *DISABLE *HI LO HI *LO GND HI *DEM HI *LO *8414 EXT
FUNCTION SELECTED See CS8414 datasheet for details See CS8414 datasheet for details See CS8414 datasheet for details See CS8414 datasheet for details See CS8414 datasheet for details Mute Enabled Mute Disabled Mute Enabled Mute Disabled Invalid for Stand-Alone Mode Disables parallel port See CS4391A data sheet for details See CS4391A data sheet for details See CS4391A data sheet for details Allows the CS8414 to control de-emphasis See CS4391A data sheet for details Selects CS8414 as source Digital I/O header becomes source
M3 HDR1 to HDR6
CS4391A Mode Selection Selects source of clocks and audio data
Table 3. CDB4391A Jumper and Switch settings - STAND-ALONE MODE *Settings for Stand-Alone mode Notes: The CDB4391A evaluation board is shipped from the factory configured for Control Port mode.
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CDB4391A
JUMPER SW1 - M0 SW1 - M1 SW1 - M2 SW1 - M3 SW1 CSLR/FCK HDR8 HDR7 ENCTRL M0/AD0/CS M1/SDA/CDIN M2/SCL/CCLK
PURPOSE CS8414 mode selection CS8414 mode selection CS8414 mode selection CS8414 mode selection Selects channel for CS8414 channel status information External mute for AOUTA External mute for AOUTB Enables / Disables parallel port AD0/CS SDA/CDIN Pull-Up SCL/CCLK Pull-Up
POSITION *LO *HI *LO *LO *LO *ON OFF *ON OFF *ENABLE DISABLE *HI LO *HI LO GND *HI DEM HI *LO *8414 EXT
FUNCTION SELECTED See CS8414 datasheet for details See CS8414 datasheet for details See CS8414 datasheet for details See CS8414 datasheet for details See CS8414 datasheet for details Mute Enabled Mute Disabled Mute Enabled Mute Disabled Enables parallel port Invalid for Control Port mode "Don't Care" for Control Port mode SDA/CDIN pulled high Invalid for Control Port mode Invalid for Control Port mode SCL/CCLK pulled high Invalid for Control Port mode Must be low for Control Port mode Selects CS8414 as source Digital I/O header becomes source
M3 HDR1 to HDR6
Not Functional Selects source of clocks and audio data
Table 4. CDB4391A Jumper and Switch settings - CONTOL PORT MODE *Settings for Control Port mode Notes: The CDB4391A evaluation board is shipped from the factory configured for Control Port mode.
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I/O for Clocks and Data Fig 9
Reset Circuit Fig 7
Control Port Interface Fig 8 Channel A Outputs and Mute Circuit Fig 4 CS4391A Fig 2
Digital Audio Inputs RXN
MCLK LRCK SCLK SDATA
Fig 6 Fig 5
CS8414 Digital Audio RXP Receiver Connections
Channel B Outputs and Mute Circuit Fig 3
CDB4391A
Figure 1. System Block Diagram and Signal Flow
9
10
C54 .1UF X7R
VL GND
U9 U7 SDATA SCLK LRCK MCLK M3 M2
M2/SCL/CCLK AOUTB+ AOUTBBMUTEC
VL
VCC
14
FERRITE_BEAD L1
VA+5
C59
SDATA AMUTEC AOUTAAOUTA+
O0
3
C17 .1UF X7R
C40 1UF
SCLK
O1
6
.1UF R41 49.9
GND
LRCK
GND
M3
1 2 4 5 13 12 10 9
O2
11
R10 499 R13 499 R14 499
1 2 3 4 5 6 7 8 9 10 \RST VL SDATA/DSD_A SCLK/DSD_B LRCK/DSDMODE MCLK (DSD_CLK)M3 (SCL/CCLK)M2 (SDA/CDIN)M1 (AD0/\CS\)M0 AMUTEC AOUTAAOUTA+ VA AGND AOUTB+ AOUTBBMUTEC CMOUT FILT+ 20 19 18 17 16 15 14 13 12 11
/A0 B0 /A1 B1 /A2 B2 /A3 B3
O3
8
GND CS4391 C20 1UF
7
GND
74VHC125M M1
M1/SDA/CS
GND
C34 .1UF X7R
C21 1UF
M0
M0/AD0/CS
GND
U6
VCC
14
MCLK
O0
3
VL DEM
RST
O1
6
8414_DEM
C61
1 2 4 5 13 12 10 9
O2
11
/A0 B0 /A1 B1 /A2 B2 /A3 B3
O3
8
.1UF
GND
GND
7
74VHC125M
GND
GND
CDB4391A
DS600DB1
Figure 2. CS4391A and Level Shift
VA+5
2
1
MMUN2111LT1 Q6
3
Q5 2SC2878 R36 2K
3
HDR1X2 HDR7 1 2
DS600DB1
R35 5.62K C4 2700PF COG 10UF R34 5.62K R29 1.18K 560PF COG U11
7
AOUTBGND
C18
AOUTB-
C41
6
AOUTB+ 10UF R33 5.62K + MC33078D C22 560PF COG
GND
R32 1.18K
5
R19
560
J4 CON_RCA_RA
1 2 3 4 NC
AOUTB+
AOUTB
C39 C28 R31 5.62K 2700PF COG
GND need cog GND
R4 47K
GND
GND
2
3
BMUTEC
1
BMUTEC
Q2 MMUN2211LT1
2
1
GND
GND
CDB4391A
Figure 3. Channel B Audio Output and Mute Circuit
11
2700PF COG C48
VEE GND GND VA+5
2
560PF COG
GND
HDR1X2 HDR8 1 2
12
R28 5.62K C7 2700PF COG
VCC GND
C6 560PF COG
C49 .1UF V+ U11 GND
1 8
AOUTA10UF 3
C42 R24 5.62K 5.62K + MC33078D
4
R17 1.18K 1.18K C5 V2
AOUTA-
J3 CON_RCA_RA R20 560 R5 47K
1 2 3 4 NC
C43 10UF C14 R15 5.62K R26 R18
AOUTA+
AOUTA
AOUTA+
GND
.1UF
GND
GND
1
MMUN2111LT1 Q3
3
Q1 2SC2878 R25 2K
3
2
3
AMUTEC AMUTEC
1
Q4 MMUN2211LT1
2
1
GND GND
CDB4391A
DS600DB1
Figure 4. Channel A Audio Output and Mute Circuit
D1 LED_RECT 2 1
SN74HC04N
4 3
VA
CS8414_M2
5 4 3 2 1
D3
RXP RXN
R9 470
C33
.068UF X7R GND
SW_DIP_5
OPEN
DS600DB1
HDR1X3 HDR5 1 2 3
MCLK
HDR1X3 HDR4
1 2 3
V+5
C1 10UF
VA
HDR1X3 HDR3
GND
1 2 3
GND
HDR1X3 HDR2 1 2 3
SCLK
RN4 47K
LRCK
VD1
R11
VD1
1 2 3
10
SDATA
HDR1X3 HDR1
C26 .1UF X7R U2 1UF 1UF C32 .1UF X7R C16
VD+5
C27
CS8414_M0
.1UF C31
SW1
VD+5
14
RN3 560
CS8414_M1
VCC
GND
U8
GND
LED_RECT
1 2 3 4 5 6 7 8 9 10 11 12 13 14
VERF C CE/F2 CD/F1 SDATA CC/F0 ERF CB/E2 M1 CA/E1 M0 /C0/E0 VA+ VD+ AGND DGND FILT RXP RXN MCK FSYNC M2 SCK M3 CS12/FCK SEL U CBL CS8414
28 27 26 25 24 23 22 21 20 19 18 17 16 15
6
5
D5 LED_RECT
CSLR/FCK
8414_DEM
8 9
D6
LED_RECT
SW_B3W_1100 S4
11
D4 10 LED_RECT
R7 47.5K
ERROR & FREQ
13
D2 12 LED_RECT
VD1
7
GND
GND
CDB4391A
Figure 5. CS8414 Digital Audio Receiver
13
14
DIGITAL INPUT
OPT1
6
OPTICAL INPUT
J5 C11 .01UF
CON_RCA_RA
3 NC 4 2 3 4 5
1
RXN
1
C10 C9 .01UF L4
.01UF
RXP
2
R30 75
47UH
VD+5
GND
TORX173
GND
CDB4391A
DS600DB1
Figure 6. Digital Audio Inputs
GND
S1 SW_B3W_1100
DS600DB1
U3 DS1233-10
1 3 Vcc GND
VD+5
RST
GND
2
1
RST
C23 100PF
GND
CDB4391A
Figure 7. Reset Circuit
15
16
VDPC+5 VD+5
C63 .1UF
VDPC+5 PC PORT
C46 .1UF
RN2 4.7K
11 2 3
GND VL GND ENCTRL GND
VCC U15 SN74HCT125D GND C45 .1UF
VDPC+5 DISABLE ENABLE GND
HDR10 HDR1X3 1 2 3 71
14
HDR4X2 HDR9 1 2 3 4 5 6 7 8
6
U5 VCC O0 O1 O2 O3 GND 74VHC125M R6 2K R8 2K
7 8 11 6 3 14
GND
RN2 4.7K
16 5 6 1
U15
GND
SN74HCT125D
4
M1/SDA/CDIN M0/AD0/CS M2/SCL/CCLK
VDPC+5
RN1 1K
U1
GND
EN_SCL/CCLK
1 2 4 5 13 12 10 9
/A0 B0 /A1 B1 /A2 B2 /A3 B3
RN2 4.7K
15 2
1 11
/OE CLK
RN2 4.7K
14 3
R12 2K
DB25M_RA P1
2 3 4 5 6 7 8 9
1D 2D 3D 4D 5D 6D 7D 8D
GND
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q VCC GND
VDPC+5
20 10 HDR1X3 HDR11 1 2 3
19 18 17 16 15 14 13 12
VL
HDR1X3 HDR12 1 2 3
RN2 4.7K
13 9 8 4
U15
EN_SCL/CCLK
SN74HCT125D
10
SN74HC574DW .1UF
C47
M0/AD0/CS
M2/SCL/CCLK
M1/SDA/CDIN
RN2 4.7K
GND GND
12 5
GND GND
HDR23 1 2
VL
HDR22 1 2 HDR21 1 2
U15
11 12
M1/SDA/CDIN
13
1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13
SN74HCT125D
DEM
GND
GND VDPC+5 VDPC+5
GND
VCC C62
2 3
14
U16 SN74HCT125D
.1UF GND
GND GND
71
U16
5 6
SN74HCT125D
4
GND
U16 R38 4.7K
9 8 D7 BAT85
SN74HCT125D
10
GND RST
U16
11 12
SN74HCT125D
13
GND
CDB4391A
DS600DB1
Figure 8. Control Port Interface
GND
VCC GND SN74HC243N
14 7
VD+5
C35 .1UF R1
GND
CDB4391A
Figure 9. I/O for Clocks and Data
0
DS600DB1
U4
1 13
G1 G2 A1 A2 A3 A4
SDATA LRCK SCLK MCLK VD+5
SDATA LRCK SCLK MCLK
(DSD_CLK)M3
HDR5X2 J9 2 1 4 3 6 5 8 7 10 9 3 4 5 6
B1 B2 B3 B4 VCC GND C24 .1UF U10
RN5 47K 14 7
11 10 9 8
GND
SN74HC243N
DIGITAL I/O
1 13
VD+5
8414 EXTERNAL CLK SOURCE
G1 G2
GND
11 10 9 8
HDR1X3 HDR6 3 4 5 6
1 2 3
HDR1X3 HDR14 1 2 3
VD+5
A1 A2 A3 A4
B1 B2 B3 B4
M3 M3
GND
17
18
GND
VL
CON_BANANA CON_BANANA
+5V
VCC
CON_BANANA CON_BANANA
+5V
VEE
CON_BANANA
CON_BANANA
J6 Z1 P6KE6V8P Z3 P6KE6V8P
J7
J1 J11 J8
J10 P6KE13 Z4 P6KE13
P6KE6V8P Z2 Z5
C12 47UF
GND VL
C2 47UF
C29 47UF
C30 47UF
C36 47UF
C25 .1UF
VA+5
C3 .1UF C57 .1UF
V+5
C37 L3 FB
GND
.1UF
C38
.1UF
C8
L2
.1UF
GND
FB
C13 47UF
VCC GND
VEE
GND
10UF C19
VDPC+5
VD+5
CDB4391A
DS600DB1
Figure 10. Power Supply
CDB4391A
Figure 11. Silkscreen Top
DS600DB1
19
CDB4391A
Figure 12. Top Side
20
DS600DB1
CDB4391A
Figure 13. Bottom Side
DS600DB1
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CDB4391A
10. PACKING LIST FOR CDB4391A
Inspect the Contents of the package and confirm that the following contents are included: 1) CDB4391A 2) CDB4391A data sheet 3) CS4391A data sheet 4) 3.5 inch floppy disk with the Windows based CDB4391A Graphical User Interface 5) 25-pin RS-232 cable
Item CDB4391A CS4391A-KZ CDB4391A data sheet CS4391A Data sheet 3.5 inch floppy disk with windows based graphical user interface 25-pin RS-232 cable
Revision B B DS600DB1 DS600PP2 1.0
22
DS600DB1
* Notes *

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