View ADV7183BKSTZ_1207947.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Multiformat SDTV Video Decoder ADV7183B
FEATURES
Multiformat video decoder supports NTSC-(J, M, 4.43), PAL-(B/D/G/H/I/M/N), SECAM Integrates three 54 MHz, 10-bit ADCs Clocked from a single 27 MHz crystal Line-locked clock-compatible (LLC) Adaptive Digital Line Length Tracking (ADLLTTM), signal processing, and enhanced FIFO management give miniTBC functionality 5-line adaptive comb filters Proprietary architecture for locking to weak, noisy, and unstable video sources such as VCRs and tuners Subcarrier frequency lock and status information output Integrated AGC with adaptive peak white mode Macrovision(R) copy protection detection Chroma transient improvement (CTI) Digital noise reduction (DNR) Multiple programmable analog input formats Composite video (CVBS) S-Video (Y/C) YPrPb component (VESA, MII, SMPTE, and BetaCam) 12 analog video input channels Automatic NTSC/PAL/SECAM identification Digital output formats (8-bit or 16-bit) ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD 0.5 V to 1.6 V analog signal input range Differential gain: 0.5% typ Differential phase: 0.5 typ Programmable video controls Peak white/hue/brightness/saturation/contrast Integrated on-chip video timing generator Free-run mode (generates stable video output with no I/P) VBI decode support for close captioning, WSS, CGMS, EDTV, Gemstar(R) 1x/2x Power-down mode 2-wire serial MPU interface (I2C(R)-compatible) 3.3 V analog, 1.8 V digital core; 3.3 V IO supply 2 temperature grades: 0C to +70C and -40C to +85C 80-lead LQFP Pb-free package
APPLICATIONS
DVD recorders Video projectors HDD-based PVRs/DVDRs LCD TVs Set-top boxes Security systems Digital televisions AVR receivers
GENERAL DESCRIPTION
The ADV7183B integrated video decoder automatically detects and converts a standard analog baseband television signalcompatible with worldwide standards NTSC, PAL, and SECAM into 4:2:2 component video data-compatible with 16-/8-bit CCIR601/CCIR656. The advanced and highly flexible digital output interface enables performance video decoding and conversion in linelocked clock-based systems. This makes the device ideally suited for a broad range of applications with diverse analog video characteristics, including tape-based sources, broadcast sources, security/surveillance cameras, and professional systems. The 10-bit accurate A/D conversion provides professional quality video performance and is unmatched. This allows true 8-bit resolution in the 8-bit output mode. The 12 analog input channels accept standard composite, S-Video, YPrPb video signals in an extensive number of
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
combinations. AGC and clamp restore circuitry allow an input video signal peak-to-peak range of 0.5 V up to 1.6 V. Alternatively, these can be bypassed for manual settings. The fixed 54 MHz clocking of the ADCs and datapath for all modes allows very precise, accurate sampling and digital filtering. The line-locked clock output allows the output data rate, timing signals, and output clock signals to be synchronous, asynchronous, or line locked even with 5% line length variation. The output control signals allow glueless interface connections in almost any application. The ADV7183B modes are set up over a 2-wire, serial, bidirectional port (I2C-compatible). The ADV7183B is fabricated in a 3.3 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7183B is packaged in a small 80-lead LQFP Pb-free package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
ADV7183B TABLE OF CONTENTS
Introduction ...................................................................................... 4 Analog Front End ......................................................................... 4 Standard Definition Processor (SDP)........................................ 4 Functional Block Diagram .......................................................... 5 specifications ..................................................................................... 6 Electrical Characteristics............................................................. 6 Video Specifications..................................................................... 7 Timing Specifications .................................................................. 8 Analog Specifications................................................................... 8 Thermal Specifications ................................................................ 9 Timing Diagrams.......................................................................... 9 Absolute Maximum Ratings.......................................................... 10 ESD Caution................................................................................ 10 Pin Configuration and Function Descriptions........................... 11 Analog Front End ........................................................................... 13 Analog Input Muxing ................................................................ 13 Manual Input Muxing................................................................ 15 Global Control Registers ............................................................... 16 Power-Save Modes...................................................................... 16 Reset Control .............................................................................. 16 Global Pin Control ..................................................................... 17 Global Status Registers................................................................... 19
52H
VBI Data Recovery..................................................................... 21 General Setup.............................................................................. 21 Color Controls ............................................................................ 23 Clamp Operation........................................................................ 25 Luma Filter .................................................................................. 26 Chroma Filter.............................................................................. 29 Gain Operation........................................................................... 30 Chroma Transient Improvement (CTI) .................................. 33 Digital Noise Reduction (DNR) ............................................... 34 Comb Filters................................................................................ 35 AV Code Insertion and Controls ............................................. 37 Synchronization Output Signals............................................... 39 Sync Processing .......................................................................... 46 VBI Data Decode ....................................................................... 47 Pixel Port Configuration ............................................................... 59 MPU Port Description................................................................... 60 Register Accesses ........................................................................ 61 Register Programming............................................................... 61 I2C Sequencer.............................................................................. 61 IP2PC Register Maps ..................................................................... 62 I2PC Register Map Details ........................................................... 66
18H
I2C Programming Examples.......................................................... 88
19H
Identification............................................................................... 19
53H
Examples in this Section use a 28 MHz Clock. ...................... 88
120H
Status 1 ......................................................................................... 19
54H
Examples Using 27 MHz Clock................................................ 92
12H
Autodetection Result.................................................................. 19
5H
PCB Layout Recommendations.................................................... 94
12H
Status 2 ......................................................................................... 19
56H
Analog Interface Inputs ............................................................. 94
123H
Status 3 ......................................................................................... 19
57H
Power Supply Decoupling ......................................................... 94
124H
Standard Definition Processor (SDP).......................................... 20
58H
PLL ............................................................................................... 94
125H
SD Luma Path ............................................................................. 20
59H
Digital Outputs (Both Data and Clocks) ................................ 94
126H
SD Chroma Path......................................................................... 20
60H
Digital Inputs .............................................................................. 94
127H
Sync Processing........................................................................... 21
61H
Antialiasing Filters ..................................................................... 95
128H
Rev. B | Page 2 of 100
ADV7183B
Crystal Load Capacitor Value Selection...................................195
62H 29H 64H
Outline Dimensions........................................................................198
31H
Typical Circuit Connection ...........................................................196
63H 30H 65H
Ordering Guide ...........................................................................198
32H
REVISION HISTORY
9/05--Rev. A to Rev. B Changes to Table 1 ............................................................................6 Changes to Table 2 ............................................................................7 Changes to Table 3 and Table 4 .......................................................8 Changes to Table 5 ............................................................................9 Change to Figure 6 ..........................................................................13 Change Formatting of Table 15 to Table 17 .................................19 Change to Figure 8 ..........................................................................21 Changes to Lock Related Controls Section..................................24 Changes to Table 34 ........................................................................32 Changes to Table Reference in BETACAM Section ...................33 Change to PAL Comb Filter Settings Section..............................37 Change to NFTOG Section............................................................44 Changes to Table 85 ........................................................................68 Changes to Table 86 ........................................................................72 6/05--Rev. 0 to Rev. A Changed Crystal References to 28 MHz Crystal............ Universal Changes to Features Section ............................................................1 9/04--Revision 0: Initial Version Changes to Table 3 and Table 4 .......................................................8 Changes to Analog Specifications Section.....................................8 Changes to Table 7 ..........................................................................11 Changes to Clamp Operation Section..........................................26 Renamed Figure 14 and Figure 15 ................................................30 Changes to Table 31 ........................................................................31 Changed LAGC Register Address in Luma Gain Section .........32 Changed VSBHE VS Default .........................................................41 Changes to Table 55 ........................................................................43 Changes to Table 56 ........................................................................45 Changed Comments for CTAPSP[1:0] in Table 85 ....................81 Changes to Table 86 ........................................................................89 Changes to Table 87 ........................................................................90 Changes to Table 88 ........................................................................91 Changes to Table 89 ........................................................................92 Added Examples Using 27 MHz Clock Section..........................93 Added XTAL Load Capacitor Value Selection Section..............96 Changes to Ordering Guide...........................................................99
Rev. B | Page 3 of 100
ADV7183B INTRODUCTION
The ADV7183B is a high quality, single chip, multiformat video decoder that automatically detects and converts PAL, NTSC, and SECAM standards in the form of composite, S-Video, and component video into a digital ITU-R BT.656 format. The advanced and highly flexible digital output interface enables performance video decoding and conversion in line-locked, clock-based systems. This makes the device ideally suited for a broad range of applications with diverse analog video characteristics, including tape based sources, broadcast sources, security/surveillance cameras, and professional systems.
STANDARD DEFINITION PROCESSOR (SDP)
The ADV7183B is capable of decoding a large selection of baseband video signals in composite, S-Video, and component formats. The video standards supported include PAL B/D/I/G/H, PAL60, PAL M, PAL N, PAL Nc, NTSC M/J, NTSC 4.43, and SECAM B/D/G/K/L. The ADV7183B can automatically detect the video standard and process it accordingly. The ADV7183B has a 5-line, superadaptive, 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to video standard and signal quality with no user intervention required. Video user controls such as brightness, contrast, saturation, and hue are also available within the ADV7183B. The ADV7183B implements a patented adaptive digital linelength tracking (ADLLT) algorithm to track varying video line lengths from sources. ADLLT enables the ADV7183B to track and decode poor quality video sources such as VCRs, noisy sources from tuner outputs, VCD players, and camcorders. The ADV7183B contains a chroma transient improvement (CTI) processor that sharpens the edge rate of chroma transitions, resulting in sharper vertical transitions. The ADV7183B can process a variety of VBI data services, such as closed captioning (CC), wide screen signaling (WSS), copy generation management system (CGMS), EDTV, Gemstar 1x/2x, and extended data service (XDS). The ADV7183B is fully Macrovision(R) certified; detection circuitry enables Type I, II, and III protection levels to be identified and reported to the user. The decoder is also fully robust to all Macrovision signal inputs.
ANALOG FRONT END
The ADV7183B analog front end comprises three 10-bit ADCs that digitize the analog video signal before applying it to the standard definition processor. The analog front end uses differential channels to each ADC to ensure high performance in mixed-signal applications. The front end also includes a 12-channel input mux that enables multiple video signals to be applied to the ADV7183B. Current and voltage clamps are positioned in front of each ADC to ensure the video signal remains within the range of the converter. Fine clamping of the video signals is performed downstream by digital fine clamping within the ADV7183B. The ADCs are configured to run in 4x oversampling mode.
Rev. B | Page 4 of 100
12 CLAMP 10 10 10 CLAMP A/D DECIMATION AND DOWNSAMPLING FILTERS LUMA FILTER GAIN CONTROL LUMA RESAMPLE 10 CLAMP A/D A/D DATA PREPROCESSOR
10 STANDARD DEFINITION PROCESSOR
FUNCTIONAL BLOCK DIAGRAM
AIN1- AIN12
INPUT MUX
CVBS S-VIDEO YPrPb
LUMA DIGITAL FINE CLAMP
LUMA 2D COMB (4H MAX)
8 8 L-DNR PIXEL DATA
SYNC AND CLK CONTROL SYNC PROCESSING AND CLOCK GENERATION SYNC EXTRACT
LINE LENGTH PREDICTOR
RESAMPLE CONTROL
AV CODE INSERTION
16
HS VS CTI C-DNR FIELD
OUTPUT FORMATTER
Figure 1.
FSC RECOVERY
Rev. B | Page 5 of 100
ADV7183B
CHROMA DIGITAL FINE CLAMP CHROMA DEMOD CONTROL AND DATA VBI DATA RECOVERY GLOBAL CONTROL SYNTHESIZED LLC CONTROL CHROMA FILTER GAIN CONTROL CHROMA RESAMPLE CHROMA 2D COMB (4H MAX)
LLC1 LLC2 SFL
INTRQ
SCLK SDA ALSB SERIAL INTERFACE CONTROL AND VBI DATA
MACROVISION DETECTION
STANDARD AUTODETECTION
FREE RUN OUTPUT CONTROL
04997-001
ADV7183B
ADV7183B SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, operating temperature range, unless otherwise specified. Table 1.
Parameter0 1, 2 STATIC PERFORMANCE Resolution (each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current
F 1F
Symbol N INL DNL VIH VIL IIN CIN VOH VOL ILEAK COUT DVDD DVDDIO PVDD AVDD IDVDD IDVDDIO IPVDD IAVDD IPWRDN tPWRUP
Test Conditions
Min
Typ
Max 10 3 -0.7/+2
Unit Bits LSB LSB V V A A pF V V A A pF V V V V mA mA mA mA mA mA ms
BSL at 54 MHz BSL at 54 MHz 2 Pins listed in Note 3 All other pins
2F
-0.475/+0.6 -0.25/+0.5
-50 -10
Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage High Impedance Leakage Current Output Capacitance POWER REQUIREMENTS4 5 Digital Core Power Supply Digital I/O Power Supply PLL Power Supply Analog Power Supply Digital Core Supply Current Digital I/O Supply Current PLL Supply Current Analog Supply Current
F
0.8 +50 +10 10
ISOURCE = 0.4 mA ISINK = 3.2 mA Pins listed in Note 4 All other pins
3F
2.4 0.4 50 10 20 1.65 3.0 1.65 3.15 1.8 3.3 1.8 3.3 82 2 10.5 85 180 1.5 20 2 3.6 2.0 3.45
CVBS input5 6 YPrPb input6 7
F F
Power-Down Current Power-Up Time
1 2
Temperature range: TMIN to TMAX, -40C to +85C (0C to 70C for ADV7183BKSTZ). The min/max specifications are guaranteed over this range. 3 Pins 36 and 79. 4 Pins 1, 2, 5, 6, 8, 12, 17, 18 to 24, 32 to 35, 74 to 76, 80. 5 Guaranteed by characterization. 6 ADC1 powered on. 7 All three ADCs powered on.
Rev. B | Page 6 of 100
ADV7183B
VIDEO SPECIFICATIONS
At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, operating temperature range, unless otherwise specified. Table 2.
Parameter7 1, 2 NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted
F 8F
Symbol DP DG LNL
Test Conditions CVBS I/P, modulate 5-step CVBS I/P, modulate 5-step CVBS I/P, 5-step Luma ramp Luma flat field
Min
Typ 0.5 0.5 0.5
Max 0.7 0.7 0.7
Unit Degrees % % dB dB dB
54 58
Analog Front End Crosstalk LOCK TIME SPECIFICATIONS Horizontal Lock Range Vertical Lock Range FSC Subcarrier Lock Range Color Lock In Time Sync Depth Range Color Burst Range Vertical Lock Time Autodetection Switch Speed CHROMA SPECIFICATIONS Hue Accuracy Color Saturation Accuracy Color AGC Range Chroma Amplitude Error Chroma Phase Error Chroma Luma Intermodulation LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy
1 2
56 60 60 +5 70 1.3 60
-5 40
20 5 2 100 HUE CL_AC 5 0.5 0.4 0.2 CVBS, 1 V I/P CVBS, 1 V I/P 1 1 1 1
200 200
% Hz Hz Lines % % Fields Lines Degrees % % % Degrees % % %
400
Temperature range: TMIN to TMAX, -40C to +85C (0C to 70C for ADV7183BKSTZ). The min/max specifications are guaranteed over this range.
Rev. B | Page 7 of 100
ADV7183B
TIMING SPECIFICATIONS
Guaranteed by characterization. At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, operating temperature range, unless otherwise specified. Table 3.
Parameter9 1, 2 SYSTEM CLOCK AND CRYSTAL Nominal Frequency Frequency Stability I2C PORT SCLK Frequency SCLK Min Pulse Width High SCLK Min Pulse Width Low Hold Time (Start Condition) Setup Time (Start Condition) SDA Setup Time SCLK and SDA Rise Time SCLK and SDA Fall Time Setup Time for Stop Condition RESET FEATURE Reset Pulse Width CLOCK OUTPUTS LLC1 Mark Space Ratio LLC1 Rising to LLC2 Rising LLC1 Rising to LLC2 Falling DATA AND CONTROL OUTPUTS Data Output Transitional Time
F 10F
Symbol
Test Conditions
Min
Typ 28.6363
Max
Unit MHz ppm kHz s s s s ns ns ns s ms
50 400 t1 t2 t3 t4 t5 t6 t7 t8 0.6 1.3 0.6 0.6 100 300 300 0.6 5 t9:t10 t11 t12 t13 t14 t15 t16 t17 Negative clock edge to start of valid data; (tACCESS = t10 - t13) End of valid data to negative clock edge; (tHOLD = t9 + t14) 6 7 4 45:55 0.5 0.5 3.4 2.4 55:45
% duty cycle ns ns ns ns ns ns ns
Data Output Transitional Time Propagation Delay to Hi-Z Max Output Enable Access Time Min Output Enable Access Time
1 2
Temperature range: TMIN to TMAX, -40C to +85C (0C to 70C for ADV7183BKSTZ). The min/max specifications are guaranteed over this range.
ANALOG SPECIFICATIONS
Guaranteed by characterization. AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V (operating temperature range, unless otherwise noted). Recommended analog input video signal range: 0.5 V to 1.6 V, typically 1 V p-p. Table 4.
Parameter1 1, 2 CLAMP CIRCUITRY External Clamp Capacitor Input Impedance Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current
1F 12F
Symbol
Test Conditions
Min
Typ 0.1 10 0.75 0.75 60 60
Max
Unit F M mA mA A A
Clamps switched off
1 2
Temperature range: TMIN to TMAX, -40C to +85C (0C to 70C for ADV7183BKSTZ). The min/max specifications are guaranteed over this range.
Rev. B | Page 8 of 100
ADV7183B
THERMAL SPECIFICATIONS
Table 5.
Parameter1 1, 2 Junction-to-Case Thermal Resistance Junction-to-Ambient Thermal Resistance (Still Air)
3F 14F
Symbol JC JA
Test Conditions 4-layer PCB with solid ground plane 4-layer PCB with solid ground plane
Min
Typ 7.6 38.1
Max
Unit C/W C/W
1 2
Temperature range: TMIN to TMAX, -40C to +85C (0C to 70C for ADV7183BKSTZ). The min/max specifications are guaranteed over this range.
TIMING DIAGRAMS
t3
SDA
t5
t3
t6
SCLK
t1
04997-002
t2
t7
t4
t8
Figure 2. I C Timing
2
t9
OUTPUT LLC 1
t10
t11
OUTPUT LLC 2
t12
t13 t14
04997-003
OUTPUTS P0-P15, VS, HS, FIELD, SFL
Figure 3. Pixel Port and Control Output Timing
OE
t15
P0-P15, HS, VS, FIELD, SFL
t17
04997-004
t16
Figure 4. OE Timing
Rev. B | Page 9 of 100
ADV7183B ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter AVDD to GND AVDD to AGND DVDD to DGND PVDD to AGND DVDDIO to DGND DVDDIO to AVDD PVDD to DVDD DVDDIO - PVDD DVDDIO - DVDD AVDD - PVDD AVDD - DVDD Digital Inputs Voltage to DGND Digital Output Voltage to DGND Analog Input to AGND Maximum Junction Temperature (TJ max) Storage Temperature Range Infrared Reflow Soldering (20 sec) Rating 4V 4V 2.2 V 2.2 V 4V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to +2 V -0.3 V to +2 V -0.3 V to +2 V -0.3 V to +2 V -0.3 V to DVDDIO + 0.3 V -0.3 V to DVDDIO + 0.3 V AGND - 0.3 V to AVDD + 0.3 V 150C -65C to +150C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 10 of 100
ADV7183B PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RESET DGND FIELD
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
VS 1 HS 2 DGND 3 DVDDIO 4 P11 5 P10 6 P9 7 P8 8 DGND 9 DVDD 10 INTRQ 11 SFL 12 NC 13 DGND 14 DVDDIO 15 NC 16 NC 17 NC 18 P7 19 P6 20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PIN 1
AIN12
60 59 58 57 56 55 54
DVDD
SCLK
ALSB
AIN6
SDA
P12
P13
P14
P15
OE
NC
NC
NC
NC
NC
NC
AIN5 AIN11 AIN4 AIN10 AGND CAPC2 CAPC1 AGND CML REFOUT AVDD CAPY2 CAPY1 AGND AIN3 AIN9 AIN2 AIN8 AIN1 AIN7
ADV7183B
TOP VIEW (Not to Scale)
53 52 51 50 49 48 47 46 45 44 43 42 41
ELPF
XTAL1
DVDD
PWRDN
DGND
PVDD
XTAL
LLC2
LLC1
P5
P4
P3
P2
P1
NC
P0
NC
NC
AGND
AGND
Figure 5. 80-Lead LQFP Pin Configuration
Rev. B | Page 11 of 100
04997-005
NC = NO CONNECT
ADV7183B
Table 7. Pin Function Descriptions
Pin No. 3, 9, 14, 31, 71 39, 40, 47, 53, 56 4, 15 10, 30, 72 50 38 42, 44, 46, 58, 60, 62, 41, 43, 45, 57, 59, 61 11 13, 16 to 18, 25, 34, 35, 63, 65, 69, 70, 77, 78 33, 32, 24, 23, 22, 21, 20, 19, 8, 7, 6, 5, 76, 75, 74, 73 2 1 80 67 68 66 64 27 26 29 28 Mnemonic DGND AGND DVDDIO DVDD AVDD PVDD AIN1 to AIN12 Type G G P P P P I Description Digital Ground. Analog Ground. Digital I/O Supply Voltage (3.3 V). Digital Core Supply Voltage (1.8 V). Analog Supply Voltage (3.3 V). PLL Supply Voltage (1.8 V). Analog Video Input Channels.
INTRQ NC
O
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video. See the interrupt register map in Table 83. No Connect Pins.
13H
P0 to P15
O
Video Pixel Output Port.
HS VS FIELD SDA SCLK ALSB RESET LLC1 LLC2 XTAL XTAL1
O O O I/O I I I O O I O
36 79 37 12
PWRDN OE ELPF SFL
I I I O
51 52 48, 49 54, 55
REFOUT CML CAPY1, CAPY2 CAPC1, CAPC2
O O I I
Horizontal Synchronization Output Signal. Vertical Synchronization Output Signal. Field Synchronization Output Signal. I2C Port Serial Data Input/Output Pin. I2C Port Serial Clock Input. Maximum clock rate of 400 kHz. This pin selects the I2C address for the ADV7183B. ALSB set to Logic 0 sets the address for a write as 0x40; for ALSB set to logic high, the address selected is 0x42. System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset the ADV7183B circuitry. This is a line-locked output clock for the pixel data output by the ADV7183B. Nominally 27 MHz, but varies up or down according to video line length. This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the ADV7183B. Nominally 13.5 MHz, but varies up or down according to video line length. This is the input pin for the 28.6363 MHz crystal, or can be overdriven by an external 3.3 V, 27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal. This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external 3.3 V, 27 MHz clock oscillator source is used to clock the ADV7183B. In crystal mode, the crystal must be a fundamental crystal. A logic low on this pin places the ADV7183B in a power-down mode. Refer to the IP2PC Register Maps section for more options on power-down modes for the ADV7183B. When set to a logic low, OE enables the pixel output bus, P15 to P0 of the ADV7183B. A logic high on the OE pin places Pins P15 to P0, HS, VS, SFL into a high impedance state. The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 46. Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices, Inc. digital video encoder. Internal Voltage Reference Output. Refer to Figure 46 for a recommended capacitor network for this pin. The CML pin is a common-mode level for the internal ADCs. Refer to Figure 46 for a recommended capacitor network for this pin. ADC's Capacitor Network. Refer to Figure 46 for a recommended capacitor network for this pin. ADC's Capacitor Network. Refer to Figure 46 for a recommended capacitor network for this pin.
134H 135H 136H 137H 138H 139H
Rev. B | Page 12 of 100
ADV7183B ANALOG FRONT END
AIN1 AIN7 AIN2 AIN8 AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12
ADC_SW_MAN_EN INSEL[3:0] INTERNAL MAPPING FUNCTIONS 1 0 ADC0_SW[3:0]
AIN1 AIN7 AIN2 AIN8 AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12 AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12 AIN2 AIN8 AIN5 AIN11 AIN6 AIN12
ADC0
1 0
ADC1_SW[3:0]
ADC1
1 0
ADC2_SW[3:0]
ADC2
Figure 6. Internal Pin Connections
ANALOG INPUT MUXING
The ADV7183B has an integrated analog muxing section that allows more than one source of video signal to be connected to the decoder. Figure 6 outlines the overall structure of the input muxing provided in the ADV7183B.
140H
Refer to Figure 7 for an overview of the two methods of controlling the ADV7183B's input muxing.
142H
ADI Recommended Input Muxing
A maximum of 12 CVBS inputs can be connected and decoded by the ADV7183B. As seen in Figure 5, this means the sources will have to be connected to adjacent pins on the IC. This calls for a careful design of the PCB layout, such as ground shielding between all signals routed through tracks that are physically close together.
143H
As seen in Figure 6, the analog input muxes can be controlled by functional registers (INSEL) or manually. Using INSEL[3:0] simplifies the setup of the muxes and minimizes crosstalk between channels by pre-assigning the input channels. This is referred to as ADI recommended input muxing.
14H
Control via an I2C manual override (ADC_sw_man_en, ADC0_sw, and ADC1_sw, ADC2_sw) is provided for applications with special requirements (for example, number/ combinations of signals) that would not be served by the preassigned input connections. This is referred to as manual input muxing.
INSEL[3:0] Input Selection, Address 0x00[3:0]
The INSEL bits allow the user to select an input channel as well as the input format. Depending on the PCB connections, only a subset of the INSEL modes is valid. The INSEL[3:0] not only switches the analog input muxing, it also configures the standard definition processor core to process CVBS (Comp), S-Video (Y/C), or component (YPbPr) format.
Rev. B | Page 13 of 100
04997-006
ADV7183B
CONNECTING ANALOG SIGNALS TO ADV7183B
YES SET INSEL[3:0] FOR REQUIRED MUXING CONFIGURATION
ADI RECOMMENDED INPUT MUXING; SEE TABLE 9
NO SET INSEL[3:0] TO CONFIGURE ADV7183B TO DECODE VIDEO FORMAT: CVBS: 0000 YC: 0110 YPrPb: 1001
Figure 7. Input Muxing Overview
Table 8. Input Channel Switching Using INSEL[3:0]
INSEL[3:0] 0000 (default) 0001 0010 0011 0100 0101 0110 0111 1000 1001 Description Analog Input Pins Video Format CVBS1 = AIN1 Composite CVBS2 = AIN2 Composite CVBS3 = AIN3 Composite CVBS4 = AIN4 Composite CVBS5 = AIN5 Composite CVBS6 = AIN6 Composite Y1 = AIN1 Y/C C1 = AIN4 Y/C Y2 = AIN2 Y/C C2 = AIN5 Y/C Y3 = AIN3 Y/C C3 = AIN6 Y/C Y1 = AIN1 YPrPb PB1 = AIN4 YPrPb PR1 = AIN5 YPrPb Y2 = AIN2 YPrPb PB2 = AIN3 YPrPb PR2 = AIN6 YPrPb CVBS7 = AIN7 Composite CVBS8 = AIN8 Composite CVBS9 = AIN9 Composite CVBS10 = AIN10 Composite CVBS11 = AIN11 Composite
Table 9. Input Channel Assignments
Input Channel AIN7 AIN1 AIN8 AIN2 AIN9 AIN3 AIN10 AIN4 AIN11 AIN5 AIN12 AIN6 Pin No. 41 42 43 44 45 46 57 58 59 60 61 62 ADI Recommended Input Muxing Control INSEL[3:0] CVBS7 CVBS1 Y/C1-Y YPrPb1-Y CVBS8 CVBS2 Y/C2-Y YPrPb2-Y CVBS9 CVBS3 Y/C3-Y YPrPb2-Pb CVBS10 CVBS4 Y/C1-C YPrPb1-Pb CVBS11 CVBS5 Y/C2-C YPrPb1-Pr Not available CVBS6 Y/C3-C YPrPb2-Pr
1010
ADI recommended input muxing is designed to minimize crosstalk between signal channels and to obtain the highest level of signal integrity. Table 9 summarizes how the PCB layout should connect analog video signals to the ADV7183B.
14H
1011 1100 1101 1110 1111
It is strongly recommended to connect any unused analog input pins to AGND to act as a shield. Inputs AIN7 to AIN11 should be connected to AGND when only six input channels are used. This improves the quality of the sampling due to better isolation between the channels. AIN12 is not under the control of INSEL[3:0]. It can be routed to ADC0/ADC1/ADC2 only by manual muxing. See Table 10 for details.
145H
Rev. B | Page 14 of 100
04997-007
USE MANUAL INPUT MUXING (ADC_SW_MAN_EN, ADC0_SW, ADC1_SW, ADC2_SW)
ADV7183B
MANUAL INPUT MUXING
By accessing a set of manual override muxing registers, the analog input muxes of the ADV7183B can be controlled directly. This is referred to as manual input muxing. Manual input muxing overrides other input muxing control bits, such as INSEL. The manual muxing is activated by setting the ADC_SW_MAN_EN bit. It affects only the analog switches in front of the ADCs. This means if the settings of INSEL and the manual input muxing registers (ADC0/ADC1/ADC2_sw) contradict each other, the ADC0/ADC1/ADC2_sw settings apply, and INSEL is ignored. Manual input muxing controls only the analog input muxes. INSEL[3:0] still has to be set so the follow-on blocks process the video data in the correct format. This means INSEL must still be used to tell the ADV7183B whether the input signal is of component, Y/C, or CVBS format. Restrictions in the channel routing are imposed by the analog signal routing inside the IC; every input pin cannot be routed to each ADC. Refer to Figure 6 for an overview on the routing capabilities inside the chip. The three mux sections can be controlled by the reserved control signal buses ADC0/ADC1/ ADC2_sw[3:0]. Table 10 explains the control words used.
146H 147H
SETADC_sw_man_en, Manual Input Muxing Enable, Address 0xC4[7]
ADC0_sw[3:0], ADC0 mux configuration, Address 0xC3[3:0] ADC1_sw[3:0], ADC1 mux configuration, Address 0xC3[7:4] ADC2_sw[3:0], ADC2 mux configuration, Address 0xC4[3:0]
Table 10. Manual Mux Settings for All ADCs (SETADC_sw_man_en = 1)
ADC0_sw[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADC0 Connected to No connection AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 No connection No connection AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 No connection ADC1_sw[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADC1 Connected to No connection No connection No connection AIN3 AIN4 AIN5 AIN6 No connection No connection No connection No connection AIN9 AIN10 AIN11 AIN12 No connection ADC2_sw[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADC2 Connected to No connection No connection AIN2 No connection No connection AIN5 AIN6 No connection No connection No connection AIN8 No connection No connection AIN11 AIN12 No connection
Rev. B | Page 15 of 100
ADV7183B GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip.
PWRDN_ADC_0, Address 0x3A[3]
When PWRDN_ADC_0 is 0 (default), the ADC is in normal operation. When PWRDN_ADC_0 is 1, ADC 0 is powered down.
POWER-SAVE MODES
Power-Down PDBP, Address 0x0F[2]
The digital core of the ADV7183B can be shut down by using the PWRDN pin and the PWRDN bit (see below). The PDBP controls which of the two pins has the higher priority. The default is to give priority to the PWRDN pin. This allows the user to have the ADV7183B powered down by default. When PDBD is 0 (default), the digital core power is controlled by the PWRDN pin (the bit is disregarded). When PDBD is 1, the bit has priority (the pin is disregarded).
PWRDN_ADC_1, Address 0x3A[2]
When PWRDN_ADC_1 is 0 (default), the ADC is in normal operation. When PWRDN_ADC_1 is 1, ADC 1 is powered down.
PWRDN_ADC_2, Address 0x3A[1]
When PWRDN_ADC_2 is 0 (default), the ADC is in normal operation. When PWRDN_ADC_2 is 1, ADC 2 is powered down.
PWRDN, Address 0x0F[5]
Setting the PWRDN bit switches the ADV7183B into a chipwide power-down mode. The power-down stops the clock from entering the digital section of the chip, thereby freezing its operation. No I2C bits are lost during power-down. The PWRDN bit also affects the analog blocks and switches them into low current modes. The I2C interface is unaffected and remains operational in power-down mode. The ADV7183B leaves the power-down state if the PWRDN bit is set to 0 (via I2C), or if the overall part is reset using the RESET pin. PDBP must be set to 1 for the PWRDN bit to power down the ADV7183B. When PWRDN is 0 (default), the chip is operational. When PWRDN is 1, the ADV7183B is in chip-wide power-down.
RESET CONTROL
Chip Reset (RES), Address 0x0F[7]
Setting this bit, equivalent to controlling the RESET pin on the ADV7183B, issues a full chip reset. All I2C registers are reset to their default values. (Some register bits do not have a reset value specified. They keep their last written value. Those bits are marked as having a reset value of x in the register table.) After the reset sequence, the part immediately starts to acquire the incoming video signal. After setting the RES bit (or initiating a reset via the pin), the part returns to the default mode of operation with respect to its primary mode of operation. All I2C bits are loaded with their default values, making this bit self-clearing. Executing a software reset takes approximately 2 ms. However, it is recommended to wait 5 ms before any further I2C writes are performed. The I2C master controller receives a no acknowledge condition on the ninth clock cycle when chip reset is implemented. See the MPU Port Description section.
148H
ADC Power-Down Control
The ADV7183B contains three 10-bit ADCs (ADC 0, ADC 1, and ADC 2). If required, each ADC can be powered down individually. The ADCs should be powered down when in: * * CVBS mode. ADC 1 and ADC 2 should be powered down to save on power consumption. S-Video mode. ADC 2 should be powered down to save on power consumption.
When RES is 0 (default), operation is normal. When RES is 1, the reset sequence starts.
Rev. B | Page 16 of 100
ADV7183B
GLOBAL PIN CONTROL
Three-State Output Drivers TOD, Address 0x03[6]
This bit allows the user to three-state the output drivers of the ADV7183B. Upon setting the TOD bit, the P15 to P0, HS, VS, FIELD, and SFL pins are three-stated. The timing pins (HS/VS/FIELD) can be forced active via the TIM_OE bit. For more information on three-state control, refer to the Three-State LLC Driver and the Timing Signals Output Enable sections.
149H 150H
Timing Signals Output Enable TIM_OE, Address 0x04[3]
The TIM_OE bit should be regarded as an addition to the TOD bit. Setting it high forces the output drivers for HS, VS, and FIELD pins into the active (driving) state even if the TOD bit is set. If set to low, the HS, VS, and FIELD pins are three-stated, dependent on the TOD bit. This functionality is useful if the decoder is used as a timing generator only. This can happen when only the timing signals are to be extracted from an incoming signal, or if the part is in free-run mode where a separate chip can output, for an example, a company logo. For more information on three-state control, refer to the ThreeState Output Drivers and the Three-State LLC Driver sections.
153H 154H
Individual drive strength controls are provided via the DR_STR_XX bits. The ADV7183B supports three-stating via a dedicated pin. When set high, the OE pin three-states the output drivers for the P15 to P0, HS, VS, FIELD, and SFL pins. The output drivers are three-stated if the TOD bit or the OE pin is set high. When TOD is 0 (default), the output drivers are enabled. When TOD is 1, the output drivers are three-stated.
Individual drive strength controls are provided via the DR_STR_XX bits. When TIM_OE is 0 (default), the HS, VS, and FIELD pins are three-stated according to the TOD bit. When TIM_OE is 1, HS, VS, and FIELD are forced active all the time.
Drive Strength Selection (Data) DR_STR[1:0] Address 0xF4[5:4]
For EMC and crosstalk reasons, it can be desirable to strengthen or weaken the drive strength of the output drivers. The DR_STR[1:0] bits affect the P[15:0] output drivers. For more information on three-state control, refer to the Drive Strength Selection (Clock) and the Drive Strength Selection (Sync) sections.
15H 156H
Three-State LLC Driver TRI_LLC, Address 0x1D[7]
This bit allows the output drivers for the LLC1 and LLC2 pins of the ADV7183B to be three-stated. For more information on three-state control, refer to the Three-State Output Drivers and the Timing Signals Output Enable sections.
15H 152H
Individual drive strength controls are provided via the DR_STR_XX bits. When TRI_LLC is 0 (default), the LLC pin drivers work according to the DR_STR_C[1:0] setting (pin enabled). When TRI_LLC is 1, the LLC pin drivers are three-stated.
Table 11. DR_STR Function
DR_STR[1:0] 00 01 (default) 10 11 Description Low drive strength (1x) Medium low drive strength (2x) Medium high drive strength (3x) High drive strength (4x)
Rev. B | Page 17 of 100
ADV7183B
Drive Strength Selection (Clock) DR_STR_C[1:0] Address 0xF4[3:2]
The DR_STR_C[1:0] bits can be used to select the strength of the clock signal output driver (LLC pin). For more information, refer to the Drive Strength Selection (Sync) and the Drive Strength Selection (Data) sections.
157H 158H
Enable Subcarrier Frequency Lock Pin EN_SFL_PIN Address 0x04[1]
The EN_SFL_PIN bit enables the output of subcarrier lock information (also known as GenLock) from the ADV7183B to an encoder in a decoder-encoder back-to-back arrangement. When EN_SFL_PIN is 0 (default), the subcarrier frequency lock output is disabled. When EN_SFL_PIN is 1, the subcarrier frequency lock information is presented on the SFL pin.
Table 12. DR_STR_C Function
DR_STR_C[1:0] 00 01 (default) 10 11 Description Low drive strength (1x) Medium low drive strength (2x) Medium high drive strength (3x) High drive strength (4x)
Polarity LLC Pin PCLK Address 0x37[0]
The polarity of the clock that leaves the ADV7183B via the LLC1 and LLC2 pins can be inverted using the PCLK bit. Changing the polarity of the LLC clock output can be necessary to meet the setup-and-hold time expectations of follow-on chips. This bit also inverts the polarity of the LLC2 clock. When PCLK is 0, the LLC output polarity is inverted. When PCLK is 1 (default), the LLC output polarity is normal (as per the timing diagrams).
Drive Strength Selection (Sync) DR_STR_S[1:0] Address 0xF4[1:0]
The DR_STR_S[1:0] bits allow the user to select the strength of the synchronization signals with which HS, VS, and F are driven. For more information, refer to the Drive Strength Selection (Clock) and the Drive Strength Selection (Data) sections.
159H 160H
Table 13. DR_STR_S Function
DR_STR_S[1:0] 00 01 (default) 10 11 Description Low drive strength (1x) Medium low drive strength (2x) Medium high drive strength (3x) High drive strength (4x)
Rev. B | Page 18 of 100
ADV7183B GLOBAL STATUS REGISTERS
Four registers provide summary information about the video decoder. The IDENT register allows the user to identify the revision code of the ADV7183B. The three other registers contain status bits regarding IC operation. Table 15. STATUS 1 Function
STATUS 1[7:0] 0 1 2 3 4 5 6 7 Bit Name IN_LOCK LOST_LOCK FSC_LOCK FOLLOW_PW AD_RESULT.0 AD_RESULT.1 AD_RESULT.2 COL_KILL Description In lock (right now) Lost lock (since last read of this register) FSC locked (right now) AGC follows peak white algorithm Result of autodetection Result of autodetection Result of autodetection Color kill active
IDENTIFICATION
IDENT[7:0] Address 0x11[7:0]
This register provides identification of the revision of the ADV7183B. An identification value of 0x11 indicates the ADV7183, released silicon. An identification value of 0x13 indicates the ADV7183B silicon.
STATUS 2
STATUS_2[7:0], Address 0x12[7:0]
Table 16. STATUS 2 Function
STATUS 2[7:0] 0 1 Bit Name MVCS DET MVCS T3 Description Detected Macrovision color striping Macrovision color striping protection. Conforms to Type 3 if high and to Type 2 if low Detected Macrovision pseudo sync pulses Detected Macrovision AGC pulses Line length is nonstandard FSC frequency is nonstandard
STATUS 1
STATUS_1[7:0] Address 0x10[7:0]
This read-only register provides information about the internal status of the ADV7183B. See VS_Coast[1:0] Address 0xF9[3:2], CIL[2:0] Count Into Lock, Address 0x51[2:0], and COL[2:0] Count Out-of-Lock, Address 0x51[5:3] for information on the timing.
16H 162H 163H
Depending on the setting of the FSCLE bit, the Status[0] and Status[1] bits are based solely on horizontal timing information on the horizontal timing and lock status of the color subcarrier. See the FSCLE FSC Lock Enable, Address 0x51[7] section.
164H
2 3 4 5 6 7
MV_PS DET MV_AGC DET LL_NSTD FSC_NSTD Reserved Reserved
AUTODETECTION RESULT
AD_RESULT[2:0] Address 0x10[6:4]
The AD_RESULT[2:0] bits report back on the findings from the autodetection block. For more information on enabling the autodetection block, see the General Setup section. For information on configuring it, see the Autodetection of SD Modes section.
165H 16H
STATUS 3
STATUS_3[7:0], Address 0x13[7:0]
Table 17. STATUS 3 Function
STATUS 3[7:0] 0 1 2 3 4 Bit Name INST_HLOCK GEMD SD_OP_50HZ Description Horizontal lock indicator (instantaneous). Gemstar detect. Flags whether 50 Hz or 60 Hz are present at output. Reserved for future use. Outputs a blue screen (see the DEF_VAL_AUTO_EN Default Value Automatic Enable, Address 0x0C[1] section). Field length is correct for currently selected video standard. Interlaced video detected (field sequence found). Reliable sequence of swinging bursts detected.
167H
Table 14. AD_RESULT Function
AD_RESULT[2:0] 000 001 010 011 100 101 110 111 Description NTSM-MJ NTSC-443 PAL-M PAL-60 PAL-BGHID SECAM PAL-Combination N SECAM 525
FREE_RUN_ACT
5
STD_FLD_LEN
6 7
INTERLACED PAL_SW_LOCK
Rev. B | Page 19 of 100
ADV7183B STANDARD DEFINITION PROCESSOR (SDP)
STANDARD DEFINITION PROCESSOR
MACROVISION DETECTION VBI DATA RECOVERY STANDARD AUTODETECTION SLLC CONTROL
DIGITIZED CVBS DIGITIZED Y (YC)
LUMA DIGITAL FINE CLAMP
LUMA FILTER
GAIN CONTROL
LUMA RESAMPLE
LUMA 2D COMB
SYNC EXTRACT
LINE LENGTH PREDICTOR
RESAMPLE CONTROL
AV CODE INSERTION
VIDEO DATA OUTPUT
DIGITIZED CVBS DIGITIZED C (YC)
CHROMA DIGITAL FINE CLAMP
CHROMA DEMOD
CHROMA FILTER
GAIN CONTROL
CHROMA RESAMPLE
CHROMA 2D COMB
MEASUREMENT BLOCK ( I2C) VIDEO DATA PROCESSING BLOCK
04997-008
FSC RECOVERY
Figure 8. Block Diagram of the Standard Definition Processor
A block diagram of the ADV7183B's standard definition processor (SDP) is shown in Figure 8.
168H
SD CHROMA PATH
The input signal is processed by the following blocks: * * Digital Fine Clamp. This block uses a high precision algorithm to clamp the video signal. Chroma Demodulation. This block uses a color subcarrier (FSC) recovery unit to regenerate the color subcarrier for any modulated chroma scheme. The demodulation block then performs an AM demodulation for PAL and NTSC, and an FM demodulation for SECAM. Chroma Filter Block. This block contains a chroma decimation filter (CAA) with a fixed response and some shaping filters (CSH) that have selectable responses. Gain Control. Automatic gain control (AGC) can operate on several different modes, including gain based on the color subcarrier's amplitude, gain based on the depth of the horizontal sync pulse on the luma channel, or fixed manual gain. Chroma Resample. The chroma data is digitally resampled to keep it perfectly aligned with the luma data. The resampling is done to correct for static and dynamic linelength errors of the incoming video signal. Chroma 2D Comb. The two-dimensional, 5-line, superadaptive comb filter provides high quality Y/C separation when the input signal is CVBS. AV Code Insertion. At this point, the demodulated chroma (Cr and Cb) signal is merged with the retrieved luma values. AV codes (as per ITU-R. BT-656) can be inserted.
The SDP block can handle standard definition video in CVBS, Y/C, and YPrPb formats. It can be divided into a luminance and a chrominance path. If the input video is of a composite type (CVBS), both processing paths are fed with the CVBS input.
SD LUMA PATH
The input signal is processed by the following blocks: * * Digital Fine Clamp. This block uses a high precision algorithm to clamp the video signal. Luma Filter Block. This block contains a luma decimation filter (YAA) with a fixed response and some shaping filters (YSH) that have selectable responses. Luma Gain Control. The automatic gain control (AGC) can operate on a variety of different modes, including gain based on the depth of the horizontal sync pulse, peak white mode, and fixed manual gain. Luma Resample. To correct for line-length errors as well as dynamic line-length changes, the data is digitally resampled. Luma 2D Comb. The two-dimensional comb filter provides Y/C separation. AV Code Insertion. At this point, the decoded luma (Y) signal is merged with the retrieved chroma values. AV codes (as per ITU-R. BT-656) can be inserted. *
*
*
* * *
*
*
*
Rev. B | Page 20 of 100
ADV7183B
SYNC PROCESSING
The ADV7183B extracts syncs embedded in the video data stream. There is currently no support for external HS/VS inputs. The sync extraction has been optimized to support imperfect video sources such as VCRs with head switches. The actual algorithm used employs a coarse detection based on a threshold crossing followed by a more detailed detection using an adaptive interpolation algorithm. The raw sync information is sent to a line-length measurement and prediction block. The output of this is then used to drive the digital resampling section to ensure the ADV7183B outputs 720 active pixels per line. The sync processing on the ADV7183B also includes the following specialized postprocessing blocks that filter and condition the raw sync information retrieved from the digitized analog video. * * Vsync Processor. This block provides extra filtering of the detected Vsyncs to give improved vertical lock. Hsync Processor. The Hsync processor is designed to filter incoming Hsyncs that are corrupted by noise, providing much improved performance for video signals with stable time base but poor SNR.
GENERAL SETUP
Video Standard Selection
The VID_SEL[3:0] bits allows the user to force the digital core into a specific video standard. Under normal circumstances, this should not be necessary. The VID_SEL[3:0] bits default to an autodetection mode that supports PAL, NTSC, SECAM, and variants thereof. The following section describes the autodetection system.
Autodetection of SD Modes
To guide the autodetection system, individual enable bits are provided for each of the supported video standards. Setting the relevant bit to 0 inhibits the standard from being detected automatically. Instead, the system picks the closest of the remaining enabled standards. The results of the autodetection can be read back via the status registers. See the Global Status Registers section for more information.
169H
VID_SEL[3:0] Address 0x00[7:4]
Table 18. VID_SEL Function
VID_SEL 0000 (default) 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Autodetect (PAL BGHID) <-> NTSC J (no pedestal), SECAM Autodetect (PAL BGHID) <-> NTSC M (pedestal), SECAM Autodetect (PAL N) (pedestal) <-> NTSC J (no pedestal), SECAM Autodetect (PAL N) (pedestal) <-> NTSC M (pedestal), SECAM NTSC-J (1) NTSC-M (1) PAL60 NTSC-.43 (1) PAL-B/G/H/I/D PAL-N (= PAL BGHID (with pedestal)) PAL-M (without pedestal) PAL-M PAL-Combination N PAL COMBINATION N (with pedestal) SECAM SECAM (with pedestal)
VBI DATA RECOVERY
The ADV7183B can retrieve the following information from the input video: * * * * * * Wide-screen signaling (WSS) Copy generation management system (CGMS) Closed caption (CC) Macrovision protection presence EDTV data Gemstar-compatible data slicing
The ADV7183B is also capable of automatically detecting the incoming video standard with respect to * * * Color subcarrier frequency Field rate Line rate
AD_SEC525_EN Enable Autodetection of SECAM 525 Line Video, Address 0x07[7]
Setting AD_SEC525_EN to 0 (default) disables the autodetection of a 525-line system with a SECAM style, FM-modulated color component. Setting AD_SEC525_EN to 1 enables the detection.
The SPD can configure itself to support PAL-B/G/H/I/D, PAL-M/N, PAL-combination N, NTSC-M, NTSC-J, SECAM 50 Hz/60 Hz, NTSC4.43, and PAL60.
Rev. B | Page 21 of 100
ADV7183B
AD_SECAM_EN Enable Autodetection of SECAM, Address 0x07[6]
Setting AD_SECAM_EN to 0 disables the autodetection of SECAM. Setting AD_SECAM_EN to 1 (default) enables the detection.
SFL_INV Subcarrier Frequency Lock Inversion
This bit controls the behavior of the PAL switch bit in the SFL (GenLock Telegram) data stream. It was implemented to solve some compatibility issues with video encoders. It solves two problems. First, the PAL switch bit is only meaningful in PAL. Some encoders (including ADI encoders) also look at the state of this bit in NTSC. Second, there was a design change in ADI encoders from ADV717x to ADV719x. The older versions used the SFL (Genlock Telegram) bit directly, while the later ones invert the bit prior to using it. The reason for this is that the inversion compensated for the 1-line delay of an SFL (GenLock Telegram) transmission. As a result, ADV717x encoders need the PAL switch bit in the SFL (Genlock Telegram) to be 1 for NTSC to work, and ADV7190/ADV7191/ADV7194 encoders need the PAL switch bit in the SFL to be 0 to work in NTSC. If the state of the PAL switch bit is wrong, a 180 phase shift occurs. In a decoder/encoder back-to-back system in which SFL is used, this bit must be set up properly for the specific encoder used.
AD_N443_EN Enable Autodetection of NTSC 443, Address 0x07[5]
Setting AD_N443_EN to 0 disables the autodetection of NTSC style systems with a 4.43 MHz color subcarrier. Setting AD_N443_EN to 1 (default) enables the detection.
AD_P60_EN Enable Autodetection of PAL60, Address 0x07[4]
Setting AD_P60_EN to 0 disables the autodetection of PAL systems with a 60 Hz field rate. Setting AD_P60_EN to 1 (default) enables the detection.
AD_PALN_EN Enable Autodetection of PAL N, Address 0x07[3]
Setting AD_PALN_EN to 0 disables the detection of the PAL N standard. Setting AD_PALN_EN to 1 (default) enables the detection.
SFL_INV Address 0x41[6]
Setting SFL_INV to 0 makes the part SFL-compatible with ADV7190/ADV7191/ADV7194 encoders. Setting SFL_INV to 1 (default), makes the part SFL-compatible with ADV717x/ADV7173x encoders.
AD_PALM_EN Enable Autodetection of PAL M, Address 0x07[2]
Setting AD_PALM_EN to 0 disables the autodetection of PAL M. Setting AD_PALM_EN to 1 (default) enables the detection.
Lock-Related Controls
Lock information is presented to the user through Bits[1:0] of the Status 1 register. See the STATUS_1[7:0] Address 0x10[7:0] section. Figure 9 outlines the signal flow and the controls available to influence the way the lock status information is generated.
170H 17H
AD_NTSC_EN Enable Autodetection of NTSC, Address 0x07[1]
Setting AD_NTSC_EN to 0 disables the detection of standard NTSC. Setting AD_NTSC_EN to 1 (default) enables the detection.
AD_PAL_EN Enable Autodetection of PAL, Address 0x07[0]
Setting AD_PAL_EN to 0 disables the detection of standard PAL. Setting AD_PAL_EN to 1 (default) enables the detection.
SELECT THE RAW LOCK SIGNAL SRLS TIME_WIN FREE_RUN FSC LOCK TAKE FSC LOCK INTO ACCOUNT FSCLE 1 0 1 FILTER THE RAW LOCK SIGNAL CIL[2:0], COL[2:0]
0 COUNTER INTO LOCK COUNTER OUT OF LOCK MEMORY STATUS 1 [0] STATUS 1 [1]
04997-009
Figure 9. Lock-Related Signal Path
Rev. B | Page 22 of 100
ADV7183B
SRLS Select Raw Lock Signal, Address 0x51[6]
Using the SRLS bit, the user can choose between two sources for determining the lock status (per Bits[1:0] in the Status 1 register). * The time_win signal is based on a line-to-line evaluation of the horizontal synchronization pulse of the incoming video. It reacts quite quickly. The free_run signal evaluates the properties of the incoming video over several fields and takes vertical synchronization information into account.
COL[2:0] Count Out-of-Lock, Address 0x51[5:3]
COL[2:0] determines the number of consecutive lines for which the out-of-lock condition must be true before the system switches into unlocked state, and reports this via Status 0[1:0]. It counts the value in lines of video. Table 21. COL Function
COL[2:0] 000 001 010 011 100 (default) 101 110 111 Description 1 2 5 10 100 500 1000 100000
*
Setting SRLS to 0 (default) selects the free_run signal. Setting SRLS to 1 selects the time_win signal.
FSCLE FSC Lock Enable, Address 0x51[7]
The FSCLE bit allows the user to choose whether the status of the color subcarrier loop is taken into account when the overall lock status is determined and presented via Bits[1:0] in Status Register 1. This bit must be set to 0 when operating in YPrPb component mode to generate a reliable HLOCK status bit. Setting FSCLE to 0 (default) makes the overall lock status dependent on only horizontal sync lock. Setting FSCLE to 1 makes the overall lock status dependent on horizontal sync lock and FSC lock.
COLOR CONTROLS
These registers allow the user to control the picture appearance, including control of the active data in the event of video being lost. These controls are independent of any other controls. For instance, brightness control is independent from picture clamping, although both controls affect the signal's dc level.
CON[7:0] Contrast Adjust, Address 0x08[7:0]
This allows the user to adjust the contrast of the picture. Table 22. CON Function
CON[7:0] 0x80 (default) 0x00 0xFF Description Gain on luma channel = 1 Gain on luma channel = 0 Gain on luma channel = 2
VS_Coast[1:0] Address 0xF9[3:2]
These bits are used to set VS free-run (coast) frequency. Table 19. VS_COAST[1:0] Function
VS_COAST[1:0] 00 (default) 01 10 11 Description Auto coast mode--follows VS frequency from last video input Forces 50 Hz coast mode Forces 60 Hz coast mode Reserved
SD_SAT_Cb[7:0] SD Saturation Cb Channel, Address 0xE3[7:0]
This register allows the user to control the gain of the Cb channel only. The user can adjust the saturation of the picture. Table 23. SD_SAT_Cb Function
SD_SAT_Cb[7:0] 0x80 (default) 0x00 0xFF Description Gain on Cb channel = 0 dB Gain on Cb channel = -42 dB Gain on Cb channel = +6 dB
CIL[2:0] Count Into Lock, Address 0x51[2:0]
CIL[2:0] determines the number of consecutive lines for which the lock condition must be true before the system switches into the locked state, and reports this via Status 0[1:0]. It counts the value in lines of video. Table 20. CIL Function
CIL[2:0] 000 001 010 011 100 (default) 101 110 111 Description 1 2 5 10 100 500 1000 100000
Rev. B | Page 23 of 100
ADV7183B
SD_SAT_Cr[7:0] SD Saturation Cr Channel, Address 0xE4[7:0]
This register allows the user to control the gain of the Cr channel only. The user can adjust the saturation of the picture. Table 24. SD_SAT_Cr Function
SD_SAT_Cr[7:0] 0x80 (default) 0x00 0xFF Description Gain on Cr channel = 0 dB Gain on Cb channel = -42 dB Gain on Cb channel = +6 dB
HUE[7:0] Hue Adjust, Address 0x0B[7:0]
This register contains the value for the color hue adjustment. It allows the user to adjust the hue of the picture. HUE[7:0] has a range of 90, with 0x00 equivalent to an adjustment of 0. The resolution of HUE[7:0] is 1 bit = 0.7. The hue adjustment value is fed into the AM color demodulation block. Therefore, it applies only to video signals that contain chroma information in the form of an AM modulated carrier (CVBS or Y/C in PAL or NTSC). It does not affect SECAM and does not work on component video inputs (YPrPb). Table 28. HUE Function
HUE[7:0] 0x00 (default) 0x7F 0x80 Description Phase of the chroma signal = 0 Phase of the chroma signal = -90 Phase of the chroma signal = +90
SD_OFF_Cb[7:0] SD Offset Cb Channel, Address 0xE1[7:0]
This register allows the user to select an offset for data on the Cb channel only and adjust the hue of the picture. There is a functional overlap with the Hue[7:0] register. Table 25.SD_OFF_Cb Function
SD_OFF_Cb[7:0] 0x80 (default) 0x00 0xFF Description 0 offset applied to the Cb channel -312 mV offset applied to the Cb channel +312 mV offset applied to the Cb channel
DEF_Y[5:0] Default Value Y, Address 0x0C[7:2]
If the ADV7183B loses lock on the incoming video signal or if there is no input signal, the DEF_Y[5:0] bits allow the user to specify a default luma value to be output. This value is used if * The DEF_VAL_AUTO_EN bit is set to high and the ADV7183B lost lock to the input video signal. This is the intended mode of operation (automatic mode). The DEF_VAL_EN bit is set, regardless of the lock status of the video decoder. This is a forced mode that may be useful during configuration.
SD_OFF_Cr[7:0] SD Offset Cr Channel, Address 0xE2[7:0]
This register allows the user to select an offset for data on the Cr channel only and adjust the hue of the picture. There is a functional overlap with the Hue[7:0] register. Table 26. SD_OFF_Cr Function
SD_OFF_Cr[7:0] 0x80 (default) 0x00 0xFF Description 0 offset applied to the Cr channel -312 mV offset applied to the Cr channel +312 mV offset applied to the Cr channel
*
The DEF_Y[5:0] values define the 6 MSBs of the output video. The remaining LSBs are padded with 0s. For example, in 8-bit mode, the output is Y[7:0] = {DEF_Y[5:0], 0, 0}. DEF_Y[5:0] is 0x0D (blue) is the default value for Y.
BRI[7:0] Brightness Adjust, Address 0x0A[7:0]
This register controls the brightness of the video signal. It allows the user to adjust the brightness of the picture. Table 27. BRI Function
BRI[7:0] 0x00 (default) 0x7F 0xFF Description Offset of the luma channel = 0IRE Offset of the luma channel = +100IRE Offset of the luma channel = -100IRE
Register 0x0C has a default value of 0x36.
DEF_C[7:0] Default Value C, Address 0x0D[7:0]
The DEF_C[7:0] register complements the DEF_Y[5:0] value. It defines the 4 MSBs of Cr and Cb values to be output if * The DEF_VAL_AUTO_EN bit is set to high and the ADV7183B cannot lock to the input video (automatic mode). The DEF_VAL_EN bit is set to high (forced output).
*
The data that is finally output from the ADV7183B for the chroma side is Cr[7:0] = {DEF_C[7:4], 0, 0, 0, 0}, Cb[7:0] = {DEF_C[3:0], 0, 0, 0, 0}. DEF_C[7:0] is 0x7C (blue) is the default value for Cr and Cb.
Rev. B | Page 24 of 100
ADV7183B
DEF_VAL_EN Default Value Enable, Address 0x0C[0]
This bit forces the use of the default values for Y, Cr, and Cb. Refer to the descriptions for DEF_Y and DEF_C for additional information. In this mode, the decoder also outputs a stable 27 MHz clock, HS, and VS. Setting DEF_VAL_EN to 0 (default) outputs a colored screen determined by user-programmable Y, Cr, and Cb values when the decoder free-runs. Free-run mode is turned on and off by the DEF_VAL_AUTO_EN bit. Setting DEF_VAL_EN to 1 forces a colored screen output determined by user-programmable Y, Cr, and Cb values. This overrides picture data even if the decoder is locked. The clamping can be divided into two sections: * * Clamping before the ADC (analog domain): current sources Clamping after the ADC (digital domain): digital processing block
The ADCs can digitize an input signal only if it resides within the ADC's 1.6 V input voltage range. An input signal with a dc level that is too large or too small is clipped at the top or bottom of the ADC range. The primary task of the analog clamping circuits is to ensure the video signal stays within the valid ADC input window so that the analog-to-digital conversion can take place. It is not necessary to clamp the input signal with a very high accuracy in the analog domain as long as the video signal fits the ADC range. After digitization, the digital fine clamp block corrects for any remaining variations in dc level. Since the dc level of an input video signal refers directly to the brightness of the picture transmitted, it is important to perform a fine clamp with high accuracy; otherwise, brightness variations can occur. Furthermore, dynamic changes in the dc level almost certainly lead to visually objectionable artifacts and must therefore be prohibited. The clamping scheme has to be able to acquire a newly connected video signal with a completely unknown dc level, and it must maintain the dc level during normal operation. For quickly acquiring an unknown video signal, the large current clamps can be activated. (It is assumed that the amplitude of the video signal at this point is of a nominal value.) Control of the coarse and fine current clamp parameters is performed automatically by the decoder. Standard definition video signals can have excessive noise on them. In particular, CVBS signals transmitted by terrestrial broadcast and demodulated using a tuner usually show very large levels of noise (>100 mV). A voltage clamp is unsuitable for this type of video signal. Instead, the ADV7183B uses a set of four current sources that can cause coarse (>0.5 mA) and fine (<0.1 mA) currents to flow into and away from the high impedance node that carries the video signal (see Figure 10).
173H
DEF_VAL_AUTO_EN Default Value Automatic Enable, Address 0x0C[1]
This bit enables the automatic usage of the default values for Y, Cr, and Cb when the ADV7183B cannot lock to the video signal. Setting DEF_VAL_AUTO_EN to 0 disables free-run mode. If the decoder is unlocked, it outputs noise. Setting DEF_VAL_EN to 1 (default) enables free-run mode. A colored screen set by the user-programmable Y, Cr, and Cb values is displayed when the decoder loses lock.
CLAMP OPERATION
The input video is ac-coupled into the ADV7183B through a 0.1 F capacitor. The recommended range of the input video signal is 0.5 V to 1.6 V (typically 1 V p-p). If the signal exceeds this range, it cannot be processed correctly in the decoder. Since the input signal is ac-coupled into the decoder, its dc value needs to be restored. This process is referred to as clamping the video. This section explains the general process of clamping on the ADV7183B and shows the different ways in which a user can configure its behavior. The ADV7183B uses a combination of current sources and a digital processing block for clamping, as shown in Figure 10. The analog processing channel shown is replicated three times inside the IC. While only one single channel (and only one ADC) is needed for a CVBS signal, two independent channels are needed for Y/C (S-VHS) type signals, and three independent channels are needed to allow component signals (YPrPb) to be processed.
172H
FINE CURRENT SOURCES
COARSE CURRENT SOURCES
ANALOG VIDEO INPUT
ADC
DATA PREPROCESSOR (DPP) CLAMP CONTROL
SDP WITH DIGITAL FINE CLAMP
04997-010
Figure 10. Clamping Overview
Rev. B | Page 25 of 100
ADV7183B
The following sections describe the I2C signals that can be used to influence the behavior of the clamps on the ADV7183B. Previous revisions of the ADV7183B had controls (FACL/FICL, fast and fine clamp length) to allow configuration of the length for which the coarse (fast) and fine current sources are switched on. These controls were removed on the ADV7183B-FT and replaced by an adaptive scheme.
LUMA FILTER
Data from the digital fine clamp block is processed by three sets of filters. The data format at this point is CVBS for CVBS input or luma only for Y/C and YPrPb input formats. * Luma Antialias Filter (YAA). The ADV7183B receives video at a rate of 27 MHz. (For 4x oversampled video, the ADCs sample at 54 MHz, and the first decimation is performed inside the DPP filters. Therefore, the data rate into the SDP core is always 27 MHz.) The ITU-R BT.601 recommends a sampling frequency of 13.5 MHz. The luma antialias filter decimates the oversampled video using a high quality, linear phase, low-pass filter that preserves the luma signal while at the same time attenuating out-of-band components. The luma antialias filter has a fixed response. Luma Shaping Filters (YSH). The shaping filter block is a programmable low-pass filter with a wide variety of responses. It can be used to selectively reduce the luma video signal bandwidth (needed prior to scaling, for example). For some video sources that contain high frequency noise, reducing the bandwidth of the luma signal improves visual picture quality. A follow-on video compression stage can work more efficiently if the video is low-pass filtered. The ADV7183B has two responses for the shaping filter: one that is used for good quality CVBS, component, and S-VHS type sources, and a second for nonstandard CVBS signals. The YSH filter responses also include a set of notches for PAL and NTSC. However, using the comb filters for Y/C separation is recommended. * Digital Resampling Filter. This block is used to allow dynamic resampling of the video signal to alter parameters such as the time base of a line of video. Fundamentally, the resampler is a set of low-pass filters. The actual response is selected by the system, and user intervention is not required.
175H
CCLEN Current Clamp Enable, Address 0x14[4]
The current clamp enable bit allows the user to switch off the current sources in the analog front end altogether. This can be useful if the incoming analog video signal is clamped externally. When CCLEN is 0, the current sources are switched off. When CCLEN is 1 (default), the current sources are enabled. *
DCT[1:0] Digital Clamp Timing, Address 0x15[6:5]
The clamp timing register determines the time constant of the digital fine clamp circuitry. It is important to realize that the digital fine clamp reacts very quickly because it is supposed to immediately correct any residual dc level error for the active line. The time constant of the digital fine clamp must be much faster than the one from the analog blocks. By default, the time constant of the digital fine clamp is adjusted dynamically to suit the currently connected input signal. Table 29. DCT Function
DCT[1:0] 00 01 10 (default) 11 Description Slow (TC = 1 sec) Medium (TC = 0.5 sec) Fast (TC = 0.1 sec) Determined by the ADV7183B, depending on the I/P video parameters
DCFE Digital Clamp Freeze Enable, Address 0x15[4]
This register bit allows the user to freeze the digital clamp loop at any time. It is intended for users who would like to do their own clamping. Users should disable the current sources for analog clamping via the appropriate register bits, wait until the digital clamp loop settles, and then freeze it via the DCFE bit. When DCFE is 0 (default), the digital clamp is operational. When DCFE is 1, the digital clamp loop is frozen.
Figure 12 through Figure 15 show the overall response of all filters together. Unless otherwise noted, the filters are set into a typical wideband mode.
174H
Rev. B | Page 26 of 100
ADV7183B
Y-Shaping Filter
For input signals in CVBS format, the luma shaping filters play an essential role in removing the chroma component from a composite signal. Y/C separation must aim for best possible crosstalk reduction while still retaining as much bandwidth (especially on the luma component) as possible. High quality Y/C separation can be achieved by using the internal comb filters of the ADV7183B. Comb filtering, however, relies on the frequency relationship of the luma component (multiples of the video line rate) and the color subcarrier (FSC). For good quality CVBS signals, this relationship is known; the comb filter algorithms can be used to separate out luma and chroma with high accuracy. For nonstandard video signals, the frequency relationship may be disturbed, and the comb filters may not be able to optimally remove all crosstalk artifacts without the assistance of the shaping filter block. An automatic mode is provided. The ADV7183B evaluates the quality of the incoming video signal and selects the filter responses in accordance with the signal quality and video standard. YFSM, WYSFMOVR, and WYSFM allow the user to manually override the automatic decisions in part or in full. The luma shaping filter has three control registers: * YSFM[4:0] allows the user to manually select a shaping filter mode (applied to all video signals) or to enable an automatic selection (dependent on video quality and video standard). WYSFMOVR allows the user to manually override the WYSFM decision. WYSFM[4:0] allows the user to select a different shaping filter mode for good quality CVBS, component (YPrPb), and S-VHS (Y/C) input signals. In automatic mode, the system preserves the maximum possible bandwidth for good CVBS sources, since they can successfully be combed, as well as for luma components of YPrPb and Y/C sources, since they need not be combed. For poor quality signals, the system selects from a set of proprietary shaping filter responses that complements comb filter operation to reduce visual artifacts. The decisions of the control logic are shown in Figure 11.
176H
YSFM[4:0] Y-Shaping Filter Mode, Address 0x17[4:0]
The Y shaping filter mode bits allow the user to select from a wide range of low-pass and notch filters. When switched in automatic mode, the filter is selected based on other register selections (for example, detected video standard) as well as properties extracted from the incoming video itself (for example, quality, time-base stability). The automatic selection always selects the widest possible bandwidth for the video input encountered. If the YSFM settings specify a filter (where YSFM is set to values other than 00000 or 00001), the chosen filter is applied to all video, regardless of its quality. In automatic selection mode, the notch filters are used only for bad quality video signals. For all other video signals, wideband filters are used.
WYSFMOVR Wideband Y-Shaping Filter Override, Address 0x18[7]
Setting the WYSFMOVR bit enables the use of the WYSFM[4:0] settings for good quality video signals. For more information, refer to the general discussion of the luma shaping filters in the Y-Shaping Filter section and the flowchart shown in Figure 11.
17H 178H
* *
When WYSFMOVR is 0, the shaping filter for good quality video signals is selected automatically. Setting WYSFMOVR to 1 enables manual override via WYSFM[4:0] (default).
Rev. B | Page 27 of 100
ADV7183B
SET YSFM
YES
YSFM IN AUTO MODE? 00000 OR 00001
NO
VIDEO QUALITY BAD GOOD USE YSFM SELECTED FILTER REGARDLESS FOR GOOD AND BAD VIDEO
AUTO SELECT LUMA SHAPING FILTER TO COMPLEMENT COMB 1
WYSFMOVR 0
SELECT AUTOMATIC WIDEBAND FILTER
Figure 11. YSFM and WYSFM Control Flowchart
Table 30. YSFM Function
YSFM[4:0] 0'0000 0'0001 (default) 0'0010 0'0011 0'0100 0'0101 0'0110 0'0111 0'1000 0'1001 0'1010 0'1011 0'1100 0'1101 0'1110 0'1111 1'0000 1'0001 1'0010 1'0011 1'0100 1'0101 1'0110 1'0111 1'1000 1'1001 1'1010 1'1011 1'1100 1'1101 1'1110 1'1111 Description Automatic selection including a wide notch response (PAL/NTSC/SECAM) Automatic selection including a narrow notch response (PAL/NTSC/SECAM) SVHS 1 SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 SVHS 7 SVHS 8 SVHS 9 SVHS 10 SVHS 11 SVHS 12 SVHS 13 SVHS 14 SVHS 15 SVHS 16 SVHS 17 SVHS 18 (CCIR 601) PAL NN 1 PAL NN 2 PAL NN 3 PAL WN 1 PAL WN 2 NTSC NN 1 NTSC NN 2 NTSC NN 3 NTSC WN 1 NTSC WN 2 NTSC WN 3 Reserved
WYSFM[4:0] Wideband Y-Shaping Filter Mode, Address 0x18[4:0]
The WYSFM[4:0] bits allow the user to manually select a shaping filter for good quality video signals, for example, CVBS with time-base stability, luma component of YPrPb and luma component of Y/C. The WYSFM bits are active only if the WYSFMOVR bit is set to 1. See the general discussion of the shaping filter settings in the Y-Shaping Filter section.
179H
Table 31. WYSFM Function
WYSFM[4:0] 0'0000 0'0001 0'0010 0'0011 0'0100 0'0101 0'0110 0'0111 0'1000 0'1001 0'1010 0'1011 0'1100 0'1101 0'1110 0'1111 1'0000 1'0001 1'0010 1'0011 (default) 1'0100 to 1'1111 Description Do not use Do not use SVHS 1 SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 SVHS 7 SVHS 8 SVHS 9 SVHS 10 SVHS 11 SVHS 12 SVHS 13 SVHS 14 SVHS 15 SVHS 16 SVHS 17 SVHS 18 (CCIR 601) Do not use
Rev. B | Page 28 of 100
04997-011
SELECT WIDEBAND FILTER AS PER WYSFM[4:0]
ADV7183B
The filter plots in Figure 12 show the S-VHS 1 (narrowest) to S-VHS 18 (widest) shaping filter settings. Figure 14 shows the PAL notch filter responses. The NTSC-compatible notches are shown in Figure 15.
180H 18H 182H
COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS, Y RESAMPLE
0 -10 -20 -30 -40 -50 -60 -70 0 2 4 6 8 FREQUENCY (MHz) 10 12
0 -10 -20 -30 -40 -50 -60 -70 0 2 4 6 8 FREQUENCY (MHz) 10 12
AMPLITUDE (dB)
AMPLITUDE (dB)
COMBINED Y ANTIALIAS, S-VHS LOW-PASS FILTERS, Y RESAMPLE
Figure 15. NTSC Notch Filter Response
04997-012
CHROMA FILTER
Data from the digital fine clamp block is processed by three sets of filters. The data format at this point is CVBS for CVBS inputs, chroma only for Y/C, or U/V interleaved for YPrPb input formats. * Chroma Antialias Filter (CAA). The ADV7183B oversamples the CVBS by a factor of 2 and the Chroma/PrPb by a factor of 4. A decimating filter (CAA) is used to preserve the active video band and to remove any out-ofband components. The CAA filter has a fixed response. Chroma Shaping Filters (CSH). The shaping filter block (CSH) can be programmed to perform a variety of lowpass responses. It can be used to selectively reduce the bandwidth of the chroma signal for scaling or compression. Digital Resampling Filter. This block is used to allow dynamic resampling of the video signal to alter parameters such as the time base of a line of video. Fundamentally, the resampler is a set of low-pass filters. The actual response is chosen by the system without user intervention.
183H
Figure 12. Y S-VHS Combined Responses
COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER, Y RESAMPLE
0
-20
AMPLITUDE (dB)
-40
-60
*
-80
-100
0
2
4
6 8 FREQUENCY (MHz)
10
12
04997-013
-120
*
Figure 13. Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant)
COMBINED Y ANTIALIAS, PAL NOTCH FILTERS, Y RESAMPLE
0 -10 -20 -30 -40 -50 -60 -70 0 2 4 6 8 FREQUENCY (MHz) 10 12
AMPLITUDE (dB)
The plots in Figure 16 show the overall response of all filters together.
Figure 14. PAL Notch Filter Response
04997-014
Rev. B | Page 29 of 100
04997-015
ADV7183B
CSFM[2:0] C- Shaping Filter Mode, Address 0x17[7]
The C-shaping filter mode bits allow the user to select from a range of low-pass filters, SH1 to SH5 and wideband mode for the chrominance signal. The autoselection options automatically select from the filter options to give the specified response. (See settings 000 and 001 in Table 32).
184H
GAIN OPERATION
The gain control within the ADV7183B is performed strictly on a digital basis. The input ADCs support a 10-bit range, mapped into a 1.6 V analog voltage range. Gain correction occurs after the digitization in the form of a digital multiplier. One advantage of this architecture over the commonly used programmable gain amplifier (PGA) before the ADCs is that the gain is now completely independent of supply, temperature, and process variations. As shown in Figure 17, the ADV7183B can decode a video signal providing it fits into the ADC window. Two components to this are the amplitude of the input signal and the dc level on which it resides. The dc level is set by the clamping circuitry (see the Clamp Operation section).
186H 187H
Table 32. CSFM Function
CSFM[2:0] 000 (default) 001 010 011 100 101 110 111 Description Autoselect 1.5 MHz bandwidth Autoselect 2.17 MHz bandwidth SH1 SH2 SH3 SH4 SH5 Wideband mode
COMBINED C ANTIALIAS, C SHAPING FILTER, C RESAMPLER
0
If the amplitude of the analog video signal is too high, clipping can occur, resulting in visual artifacts. The analog input range of the ADC, together with the clamp level, determines the maximum supported amplitude of the video signal. The minimum supported amplitude of the input video is determined by the ADV7183B's ability to retrieve horizontal and vertical timing and to lock to the color burst, if present. There are two gain control units, one each for luma and chroma data. Both can operate independently of each other. The chroma unit, however, can also take its gain value from the luma path. The possible AGC modes are summarized in Table 33.
18H
-10
ATTENUATION (dB)
-20
-30
-40
-50
0
1
2
3 4 FREQUENCY (MHz)
5
6
Figure 16. Chroma Shaping Filter Responses
Figure 16 shows the responses of SH1 (narrowest) to SH5 (widest) and the wide band mode (in red).
185H
04997-016
-60
It is possible to freeze the automatic gain control loops. This causes the loops to stop updating and the AGC determined gain, at the time of the freeze, to stay active. The ACG determined gain stays active until the automatic gain control loop is either unfrozen, or the gain mode of the operation is changed. The currently active gain from any of the modes can be read back. Refer to the description of the dual function manual gain registers, LG[11:0] Luma Gain and CG[11:0] Chroma Gain, in the Luma Gain and Chroma Gain sections.
189H 190H
ANALOG VOLTAGE RANGE SUPPORTED BY ADC (1.6V RANGE FOR ADV7189B) MAXIMUM VOLTAGE
ADC
DATA PREPROCESSOR (DPP)
SDP (GAIN SELECTION ONLY)
MINIMUM VOLTAGE
CLAMP LEVEL
Figure 17. Gain Control Overview
Rev. B | Page 30 of 100
04983-017
GAIN CONTROL
ADV7183B
Table 33. AGC Modes
Input Video Type Any CVBS Luma Gain Manual gain luma Dependent on horizontal sync depth Peak white Y/C Dependent on horizontal sync depth Peak white YPrPb Dependent on horizontal sync depth Chroma Gain Manual gain chroma Dependent on color burst amplitude Taken from luma path Dependent on color burst amplitude Taken from luma path Dependent on color burst amplitude Taken from luma path Dependent on color burst amplitude Taken from luma path Taken from luma path
Luma Gain LAGC[2:0] Luma Automatic Gain Control, Address 0x2C[7:0]
The luma automatic gain control mode bits select the mode of operation for the gain control in the luma path. ADI internal parameters are available to customize the peak white gain control. Contact ADI sales for more information. Table 34. LAGC Function
LAGC[2:0] 000 001 010 (default) 011 100 101 110 111 Description Manual fixed gain (use LMG[11:0]) AGC (blank level to sync tip); peak white algorithm off AGC (blank level to sync tip); peak white algorithm on Reserved Reserved Reserved Reserved Freeze gain
Table 35. LAGT Function
LAGT[1:0] 00 01 10 11 (default) Description Slow (TC = 2 sec) Medium (TC = 1 sec) Fast (TC = 0.2 sec) Adaptive
LG[11:0] Luma Gain, Address 0x2F[3:0]; Address 0x30[7:0]; LMG[11:0] Luma Manual Gain, Address 0x2F[3:0]; Address 0x30[7:0]
Luma gain[11:0] is a dual-function register. If written to, a desired manual luma gain can be programmed. This gain becomes active if the LAGC[2:0] mode is switched to manual fixed gain. Equation 1 shows how to calculate a desired gain. If read back, this register returns the current gain value. Depending on the setting in the LAGC[2:0] bits, one of these gain values is returned * * Luma manual gain value (LAGC[2:0] set to luma manual gain mode) Luma automatic gain value (LAGC[2:0] set to any of the automatic modes)
Read/Write Write Read Description Manual gain for luma path Actually used gain
LAGT[1:0] Luma Automatic Gain Timing, Address 0x2F[7:6]
The luma automatic gain timing register allows the user to influence the tracking speed of the luminance automatic gain control. Note that this register has an effect only if the LAGC[2:0] register is set to 001, 010, 011, or 100 (automatic gain control modes). If peak white AGC is enabled and active (see the STATUS_1[7:0] Address 0x10[7:0] section), the actual gain update speed is dictated by the peak white AGC loop and, as a result, the LAGT settings have no effect. As soon as the part leaves peak white AGC, LAGT becomes relevant again.
19H
Table 36. LG/LMG Function
LG[11:0]/LMG[11:0] LMG[11:0] = X LG[11:0]
Luma _ Gain =
(0 < LG 4095)
2048
= 0...2
(1)
The update speed for the peak white algorithm can be customized by the use of internal parameters. Contact ADI sales for more information.
Rev. B | Page 31 of 100
ADV7183B
For example, program the ADV7183B into manual fixed gain mode with a desired gain of 0.89. 1. 2. 3. 4. Use Equation 1 to convert the gain: 0.89 x 2048 = 1822.72 Truncate to integer value: 1822.72 = 1822 Convert to hexadecimal: 1822d = 0x71E Split into two registers and program: Luma Gain Control 1[3:0] = 0x7 Luma Gain Control 2[7:0] = 0x1E Enable manual fixed gain mode: Set LAGC[2:0] to 000
PW_UPD Peak White Update, Address 0x2B[0]
The peak white and average video algorithms determine the gain based on measurements taken from the active video. The PW_UPD bit determines the rate of gain change. The LAGC[2:0] must be set to the appropriate mode to enable the peak white or average video mode in the first place. For more information, refer to the LAGC[2:0] Luma Automatic Gain Control, Address 0x2C[7:0] section.
196H
Setting PW_UPD to 0 updates the gain once per video line. Setting PW_UPD to 1 (default) updates the gain once per field.
5.
BETACAM Enable Betacam Levels, Address 0x01[5]
If YPrPb data is routed through the ADV7183B, the automatic gain control modes can target different video input levels, as outlined in Figure 40. The BETACAM bit is valid only if the input mode is YPrPb (component). The BETACAM bit sets the target value for AGC operation.
192H
Chroma Gain CAGC[1:0] Chroma Automatic Gain Control, Address 0x2C[1:0]
The two bits of the Color Automatic Gain Control mode select the basic mode of operation for automatic gain control in the chroma path.
Table 38. CAGC Function
CAGC[1:0] 00 01 10 (default) 11 Description Manual fixed gain (use CMG[11:0]) Use luma gain for chroma Automatic gain (based on color burst) Freeze chroma gain
A review of the following sections is useful: *
193H
INSEL[3:0] Input Selection, Address 0x00[3:0] to find how component video (YPrPb) can be routed through the ADV7183B. Video Standard Selection to select the various standards, such as those with and without pedestal.
194H
*
The automatic gain control (AGC) algorithms adjust the levels based on the setting of the BETACAM bit (see Table 37). Table 37. BETACAM Function
195H
CAGT[1:0] Chroma Automatic Gain Timing, Address 0x2D[7:6]
The chroma automatic gain timing register allows the user to influence the tracking speed of the chroma automatic gain control. This register has an effect only if the CAGC[1:0] register is set to 10 (automatic gain).
Table 39. CAGT Function
CAGT[1:0] 00 01 10 11 (default) Description Slow (TC = 2 sec) Medium (TC = 1 sec) Fast (TC = 0.2 sec) Adaptive
BETACAM 0 (default)
1
Description Assuming YPrPb is selected as input format Selecting PAL with pedestal selects MII Selecting PAL without pedestal selects SMPTE Selecting NTSC with pedestal selects MII Selecting NTSC without pedestal selects SMPTE Assuming YPrPb is selected as input format Selecting PAL with pedestal selects BETACAM Selecting PAL without pedestal selects BETACAM variant Selecting NTSC with pedestal selects BETACAM Selecting NTSC without pedestal selects BETACAM variant
Table 40. Betacam Levels
Name Y Range Pb and Pr Range Sync Depth Betacam (mV) 0 to 714 (includes 7.5% pedestal) -467 to +467 286 Betacam Variant (mV) 0 to 714 -505 to +505 286 SMPTE (mV) 0 to 700 -350 to +350 300 MII (mV) 0 to 700 (includes 7.5% pedestal) -324 to +324 300
Rev. B | Page 32 of 100
ADV7183B
CG[11:0] Chroma Gain, Address 0x2D[3:0]; Address 0x2E[7:0] CMG[11:0] Chroma Manual Gain, Address 0x2D[3:0]; Address 0x2E[7:0]
Chroma Gain[11:0] is a dual-function register. If written to, a desired manual chroma gain can be programmed. This gain becomes active if the CAGC[1:0] mode is switched to manual fixed gain. Refer to Equation 2 for calculating a desired gain. If read back, this register returns the current gain value. Depending on the setting in the CAGC[1:0] bits, one of these gain values is returned * * Chroma manual gain value (CAGC[1:0] set to chroma manual gain mode) Chroma automatic gain value (CAGC[1:0] set to any of the automatic modes)
Read/Write Write Read Description Manual gain for chroma path Currently active gain
CKILLTHR[2:0] Color Kill Threshold, Address 0x3D[6:4]
The CKILLTHR[2:0] bits allow the user to select a threshold for the color kill function. The threshold applies only to QAM based (NTSC and PAL) or FM-modulated (SECAM) video standards. To enable the color kill function, the CKE bit must be set. For settings 000, 001, 010, and 011, chroma demodulation inside the ADV7183B may not work satisfactorily for poor input video signals.
Table 42. CKILLTHR Function
CKILLTHR[2:0] 000 001 010 011 100 (default) 101 110 111 Description SECAM NTSC, PAL No color kill Kill at < 0.5% Kill at < 5% Kill at < 1.5% Kill at < 7% Kill at < 2.5% Kill at < 8% Kill at < 4.0% Kill at < 9.5% Kill at < 8.5% Kill at < 15% Kill at < 16.0% Kill at < 32% Kill at < 32.0% Reserved for ADI internal use only; do not select
Table 41. CG/CMG Function
CG[11:0]/CMG[11:0] CMG[11:0] CG[11:0]
Chroma _ Gain =
(0 < CG 4095 )
1024
= 0...4
(2)
For example, freezing the automatic gain loop and reading back the CG[11:0] register results in a value of 0x47A. 1. 2. Convert the readback value to decimal: 0x47A = 1146d Apply Equation 2 to convert the readback value: 1146/1024 = 1.12
CHROMA TRANSIENT IMPROVEMENT (CTI)
The signal bandwidth allocated for chroma is typically much smaller than that of luminance. In the past, this was a valid way to fit a color video signal into a given overall bandwidth because the human eye is less sensitive to chrominance than to luminance. The uneven bandwidth, however, can lead to visual artifacts in sharp color transitions. At the border of two bars of color, both components (luma and chroma) change at the same time (see Figure 18). Due to the higher bandwidth, the signal transition of the luma component is usually much sharper than that of the chroma component. The color edge is not sharp but blurred, in the worst case, over several pixels.
197H
CKE Color Kill Enable, Address 0x2B[6]
The color kill enable bit allows the optional color kill function to be switched on or off. For QAM-based video standards (PAL and NTSC) and FMbased systems (SECAM), the threshold for the color kill decision is selectable via the CKILLTHR[2:0] bits. If color kill is enabled, and if the color carrier of the incoming video signal is less than the threshold for 128 consecutive video lines, color processing is switched off (black and white output). To switch the color processing back on, another 128 consecutive lines with a color burst greater than the threshold are required. The color kill option works only for input signals with a modulated chroma part. For component input (YPrPb), there is no color kill. Setting CKE to 0 disables color kill. Setting CKE to 1 (default) enables color kill.
LUMA SIGNAL
LUMA SIGNAL WITH A TRANSITION, ACCOMPANIED BY A CHROMA TRANSITION
Figure 18. CTI Luma/Chroma Transition
Rev. B | Page 33 of 100
04997-018
DEMODULATED CHROMA SIGNAL
ORIGINAL, SLOW CHROMA TRANSITION PRIOR TO CTI SHARPENED CHROMA TRANSITION AT THE OUTPUT OF CTI
ADV7183B
The chroma transient improvement block examines the input video data. It detects transitions of chroma and can be programmed to steepen the chroma edges in an attempt to artificially restore lost color bandwidth. The CTI block, however, operates only on edges above a certain threshold to ensure that noise is not emphasized. Care has also been taken to ensure that edge ringing and undesirable saturation or hue distortion are avoided. Chroma transient improvements are needed primarily for signals that experienced severe chroma bandwidth limitations. For those types of signals, it is strongly recommended to enable the CTI block via CTI_EN.
Table 43. CTI_AB Function
CTI_AB[1:0] 00 01 10 11 (default) Description Sharpest mixing between sharpened and original chroma signal Sharp mixing Smooth mixing Smoothest alpha blend function
CTI_C_TH[7:0] CTI Chroma Threshold, Address 0x4E[7:0]
The CTI_C_TH[7:0] value is an unsigned, 8-bit number specifying how big the amplitude step in a chroma transition must be steepened by the CTI block. Programming a small value into this register causes even smaller edges to be steepened by the CTI block. Making CTI_C_TH[7:0] a large value causes the block to improve large transitions only. The default value for CTI_C_TH[7:0] is 0x08, indicating the threshold for the chroma edges prior to CTI.
CTI_EN Chroma Transient Improvement Enable, Address 0x4D[0]
The CTI_EN bit enables the CTI function. If set to 0, the CTI block is inactive and the chroma transients are left untouched. Setting CTI_EN to 0 disables the CTI block. Setting CTI_EN to 1 (default) enables the CTI block.
DIGITAL NOISE REDUCTION (DNR)
Digital noise reduction is based on the assumption that high frequency signals with low amplitude are probably noise and that their removal, therefore, improves picture quality.
CTI_AB_EN Chroma Transient Improvement Alpha Blend Enable, Address 0x4D[1]
The CTI_AB_EN bit enables an alpha-blend function within the CTI block. If set to 1, the alpha blender mixes the transient improved chroma with the original signal. The sharpness of the alpha blending can be configured via the CTI_AB[1:0] bits. For the alpha blender to be active, the CTI block must be enabled via the CTI_EN bit. Setting CTI_AB_EN to 0 disables the CTI alpha blender. Setting CTI_AB_EN to 1 (default) enables the CTI alpha-blend mixing function.
DNR_EN Digital Noise Reduction Enable, Address 0x4D[5]
The DNR_EN bit enables or bypasses the DNR block. Setting DNR_EN to 0 bypasses DNR (disables it). Setting DNR_EN to 1 (default) enables digital noise reduction on the luma data.
DNR_TH[7:0] DNR Noise Threshold, Address 0x50[7:0]
The DNR_TH[7:0] value is an unsigned 8-bit number used to determine the maximum edge to be interpreted as noise and, therefore, blanked from the luma data. Programming a large value into DNR_TH[7:0] causes the DNR block to interpret even large transients as noise and remove them. The effect on the video data is, therefore, more visible. Programming a small value causes only small transients to be seen as noise and to be removed. The recommended DNR_TH[7:0] setting for A/V inputs is 0x04, and the recommended DNR_TH[7:0] setting for tuner inputs is 0x0A. The default value for DNR_TH[7:0] is 0x08, indicating the threshold for maximum luma edges to be interpreted as noise.
CTI_AB[1:0] Chroma Transient Improvement Alpha Blend, Address 0x4D[3:2]
The CTI_AB[1:0] controls the behavior of alpha-blend circuitry that mixes the sharpened chroma signal with the original one. It thereby controls the visual impact of CTI on the output data. For CTI_AB[1:0] to become active, the CTI block must be enabled via the CTI_EN bit, and the alpha blender must be switched on via CTI_AB_EN. Sharp blending maximizes the effect of CTI on the picture, but can also increase the visual impact of small amplitude, high frequency chroma noise.
Rev. B | Page 34 of 100
ADV7183B
COMB FILTERS
The comb filters of the ADV7183B have been greatly improved to automatically handle video of all types, standards, and levels of quality. The NTSC and PAL configuration registers allow the user to customize comb filter operation, depending on which video standard is detected (by autodetection) or selected (by manual programming). In addition to the bits listed in this section, there are some other ADI internal controls; contact ADI for more information.
Table 44. NSFSEL Function
NSFSEL[1:0] 00 (default) 01 10 11 Description Narrow Medium Medium Wide
CTAPSN[1:0] Chroma Comb Taps NTSC, Address x38[7:6]
Table 45. CTAPSN Function
CTAPSN[1:0] 00 01 10 (default) 11 Description Do not use NTSC chroma comb adapts 3 lines (3 taps) to 2 lines (2 taps) NTSC chroma comb adapts 5 lines (5 taps) to 3 lines (3 taps) NTSC chroma comb adapts 5 lines (5 taps) to 4 lines (4 taps)
NTSC Comb Filter Settings
Used for NTSC-M/J CVBS inputs.
NSFSEL[1:0] Split Filter Selection NTSC, Address 0x19[3:2]
The NSFSEL[1:0] control selects how much of the overall signal bandwidth is fed to the combs. A narrow split filter selection gives better performance on diagonal lines, but leaves more dot crawl in the final output image; the opposite is true for selecting a wide bandwidth split filter.
CCMN[2:0] Chroma Comb Mode NTSC, Address 0x38[5:3]
Table 46. CCMN Function
CCMN[2:0] 0xx (default) Description Adaptive comb mode Adaptive 3-line chroma comb for CTAPSN = 01 Adaptive 4-line chroma comb for CTAPSN = 10 Adaptive 5-line chroma comb for CTAPSN = 11 Fixed 2-line chroma comb for CTAPSN = 01 Fixed 3-line chroma comb for CTAPSN = 10 Fixed 4-line chroma comb for CTAPSN = 11 Fixed 3-line chroma comb for CTAPSN = 01 Fixed 4-line chroma comb for CTAPSN = 10 Fixed 5-line chroma comb for CTAPSN = 11 Fixed 2-line chroma comb for CTAPSN = 01 Fixed 3-line chroma comb for CTAPSN = 10 Fixed 4-line chroma comb for CTAPSN = 11
100 101
Disable chroma comb Fixed chroma comb (top lines of line memory)
110
Fixed chroma comb (all lines of line memory)
111
Fixed chroma comb (bottom lines of line memory)
YCMN[2:0] Luma Comb Mode NTSC, Address 0x38[2:0]
Table 47.YCMN Function
YCMN[2:0] 0xx (default) 100 101 110 111 Description Adaptive comb mode Disable luma comb Fixed luma comb (top lines of line memory) Fixed luma comb (all lines of line memory) Fixed luma comb (bottom lines of line memory) Adaptive 3-line (3 taps) luma comb Use low-pass/notch filter; see the Y-Shaping Filter section Fixed 2-line (2 taps) luma comb Fixed 3-line (3 taps) luma comb Fixed 2-line (2 taps) luma comb
198H
Rev. B | Page 35 of 100
ADV7183B
PAL Comb Filter Settings
Used for PAL-B/G/H/I/D, PAL-M, PAL-Combination N, PAL60 and NTSC443 CVBS inputs.
Table 48. PSFSEL Function
PSFSEL[1:0] 00 01 (default) 10 11 Description Narrow Medium Wide Widest
PSFSEL[1:0] Split Filter Selection PAL, Address 0x19[1:0]
The PSFSEL[1:0] control selects how much of the overall signal bandwidth is fed to the combs. A wide split filter selection eliminates dot crawl, but shows imperfections on diagonal lines; the opposite is true for selecting a narrow bandwidth split filter.
CTAPSP[1:0] Chroma Comb Taps PAL, Address 0x39[7:6]
Table 49. CTAPSP Function
CTAPSP[1:0] 00 01 10 11 (default) Description Do not use. PAL chroma comb adapts 5 lines (3 taps) to 3 lines (2 taps); cancels cross luma only PAL chroma comb adapts 5 lines (5 taps) to 3 lines (3 taps); cancels cross luma and hue error less well PAL chroma comb adapts 5 lines (5 taps) to 4 lines (4 taps); cancels cross luma and hue error well
CCMP[2:0] Chroma Comb Mode PAL, Address 0x39[5:3]
Table 50. CCMP Function
CCMP[2:0] 0xx (default) Description Adaptive comb mode Configuration Adaptive 3-line chroma comb for CTAPSP = 01 Adaptive 4-line chroma comb for CTAPSP = 10 Adaptive 5-line chroma comb for CTAPSP = 11 Fixed 2-line chroma comb for CTAPSP = 01 Fixed 3-line chroma comb for CTAPSP = 10 Fixed 4-line chroma comb for CTAPSP = 11 Fixed 3-line chroma comb for CTAPSP = 01 Fixed 4-line chroma comb for CTAPSP = 10 Fixed 5-line chroma comb for CTAPSP = 11 Fixed 2-line chroma comb for CTAPSP = 01 Fixed 3-line chroma comb for CTAPSP = 10 Fixed 4-line chroma comb for CTAPSP = 11
100 101
Disable chroma comb Fixed chroma comb (top lines of line memory)
110
Fixed chroma comb (all lines of line memory)
111
Fixed chroma comb (bottom lines of line memory)
YCMP[2:0] Luma Comb Mode PAL, Address 0x39[2:0]
Table 51. YCMP Function
YCMP[2:0] 0xx (default) 100 101 110 111 Description Adaptive comb mode Disable luma comb Fixed luma comb (top lines of line memory) Fixed luma comb (all lines of line memory) Fixed luma comb (bottom lines of line memory) Configuration Adaptive 5 lines (3 taps) luma comb Use low-pass/notch filter; see the Y-Shaping Filter section Fixed 3 lines (2 taps) luma comb Fixed 5 lines (3 taps) luma comb Fixed 3 lines (2 taps) luma comb
19H
Rev. B | Page 36 of 100
ADV7183B
AV CODE INSERTION AND CONTROLS
This section describes the I C based controls that affect: * * * * Insertion of AV codes into the data stream Data blanking during the vertical blank interval (VBI) The range of data values permitted in the output data stream The relative delay of luma vs. chroma signals
2
SD_DUP_AV Duplicate AV Codes, Address 0x03[0]
Depending on the output interface width, it can be necessary to duplicate the AV codes from the luma path into the chroma path. In an 8-bit-wide output interface (Cb/Y/Cr/Y interleaved data), the AV codes are defined as FF/00/00/AV, with AV as the transmitted word that contains information about H/V/F. In this output interface mode, the following assignment takes place: Cb = FF, Y = 00, Cr = 00, and Y = AV. In a 16-bit output interface where Y and Cr/Cb are delivered via separate data buses, the AV code is over the whole 16 bits. The SD_DUP_AV bit allows the user to replicate the AV codes on both busses, so the full AV sequence can be found on the Y bus and on the Cr/Cb bus. See Figure 19.
201H
Some of the decoded VBI data is inserted during the horizontal blanking interval. See the Gemstar Data Recovery section for more information.
20H
BT656-4 ITU Standard BT-R.656-4 Enable, Address 0x04[7]
The ITU has changed the position for toggling of the V bit within the SAV EAV codes for NTSC between revisions 3 and 4. The BT656-4 standard bit allows the user to select an output mode that is compliant with either the previous or the new standard. For more information, review the standard at www.itu.int. Note that the standard change affects NTSC only and has no bearing on PAL. When BT656-4 is 0 (default), the BT656-3 specification is used. The V bit goes low at EAV of Line 10 and Line 273. When BT656-4 is 1, the BT656-4 specification is used. The V bit goes low at EAV of Line 20 and Line 283.
When SD_DUP_AV is 0 (default), the AV codes are in single fashion (for 8-bit interleaved data output). When SD_DUP_AV is 1, the AV codes are duplicated (for 16-bit interfaces).
VBI_EN Vertical Blanking Interval Data Enable, Address 0x03[7]
The VBI enable bit allows data such as intercast and closed caption data to be passed through the luma channel of the decoder with a minimal amount of filtering. All data for Line 1 to Line 21 is passed through and available at the output port. The ADV7183B does not blank the luma data, and automatically switches all filters along the luma data path into their widest bandwidth. For active video, the filter settings for YSH and YPK are restored. Refer to the BL_C_VBI Blank Chroma During VBI, Address 0x04[2] section for information on the chroma path.
20H
When VBI_EN is 0 (default), all video lines are filtered/scaled. When VBI_EN is 1, only the active video region is filtered/scaled.
SD_DUP_AV = 1 16-BIT INTERFACE Y DATA BUS FF 00 00 AV Y 16-BIT INTERFACE 00 AV Y Cb/Y/Cr/Y INTERLEAVED Cr/Cb DATA BUS FF 00 00 AV Cb FF 00 Cb
04997-019
SD_DUP_AV = 0 8-BIT INTERFACE
FF
00
00
AV
Cb
AV CODE SECTION AV CODE SECTION AV CODE SECTION
Figure 19. AV Code Duplication Control
Rev. B | Page 37 of 100
ADV7183B
BL_C_VBI Blank Chroma During VBI, Address 0x04[2]
Setting BL_C_VBI high, the Cr and Cb values of all VBI lines are blanked. This is done so any data that arrives during VBI is not decoded as color and output through Cr and Cb. As a result, it should be possible to send VBI lines into the decoder, then output them through an encoder again, undistorted. Without this blanking, any wrongly decoded color is encoded by the video encoder; therefore, the VBI lines are distorted. Setting BL_C_VBI to 0 decodes and outputs color during VBI. Setting BL_C_VBI to 1 (default) blanks Cr and Cb values during VBI.
LTA[1:0] Luma Timing Adjust, Address 0x27[1:0]
The Luma Timing Adjust register allows the user to specify a timing difference between chroma and luma samples. There is a certain functionality overlap with the CTA[2:0] register. For manual programming, use the following defaults: * * * CVBS input LTA[1:0] = 00 Y/C input LTA[1:0] = 01 YPrPb input LTA[1:0] = 01
Description No delay Luma 1 clk (37 ns) delayed Luma 2 clk (74 ns) early Luma 1 clk (37 ns) early
Table 53. LTA Function
LTA[1:0] 00 (default) 01 10 11
RANGE Range Selection, Address 0x04[0]
AV codes (as per ITU-R BT-656, formerly known as CCIR-656) consist of a fixed header made up of 0xFF and 0x00 values. These two values are reserved and therefore cannot be used for active video. Additionally, the ITU specifies that the nominal range for video should be restricted to values between 16 and 235 for luma and 16 to 240 for chroma. The RANGE bit allows the user to limit the range of values output by the ADV7183B to the recommended value range. In any case, it ensures that the reserved values of 255d (0xFF) and 00d (0x00) are not presented on the output pins unless they are part of an AV code header.
Table 52. RANGE Function
RANGE 0 1 (default) Description 16 Y 235 1 Y 254 16 C/P 240 1 C/P 254
CTA[2:0] Chroma Timing Adjust, Address 0x27[5:3]
The Chroma Timing Adjust register allows the user to specify a timing difference between chroma and luma samples. This can be used to compensate for external filter group delay differences in the luma vs. chroma path, and to allow a different number of pipeline delays while processing the video downstream. Review this functionality together with the LTA[1:0] register. The chroma can only be delayed/advanced in chroma pixel steps. One chroma pixel step is equal to two luma pixels. The programmable delay occurs after demodulation, where one can no longer delay by luma pixel steps. For manual programming, use the following defaults: * * * CVBS input CTA[2:0] = 011 Y/C input CTA[2:0] = 101 YPrPb input CTA[2:0] =110
Description Not used Chroma + 2 chroma pixel (early) Chroma + 1 chroma pixel (early) No delay Chroma - 1 chroma pixel (late) Chroma - 2 chroma pixel (late) Chroma - 3 chroma pixel (late) Not used
AUTO_PDC_EN Automatic Programmed Delay Control, Address 0x27[6]
Enabling the AUTO_PDC_EN function activates a function within the ADV7183B that automatically programs the LTA[1:0] and CTA[2:0] to have the chroma and luma data match delays for all modes of operation. If set, manual registers LTA[1:0] and CTA[2:0] are not used. If the automatic mode is disabled (via setting the AUTO_PDC_EN bit to 0), the values programmed into LTA[1:0] and CTA[2:0] registers become active. When AUTO_PDC_EN is 0, the ADV7183 uses the LTA[1:0] and CTA[2:0] values for delaying luma and chroma samples. Refer to the LTA[1:0] Luma Timing Adjust, Address 0x27[1:0] and the CTA[2:0] Chroma Timing Adjust, Address 0x27[5:3] sections.
203H 204H
Table 54. CTA Function
CTA[2:0] 000 001 010 011 (default) 100 101 110 111
When AUTO_PDC_EN is 1 (default), the ADV7183B automatically determines the LTA and CTA values to have luma and chroma aligned at the output.
Rev. B | Page 38 of 100
ADV7183B
SYNCHRONIZATION OUTPUT SIGNALS
HS Configuration
The following controls allow the user to configure the behavior of the HS output pin only: * * * Beginning of HS signal via HSB[10:0] End of HS signal via HSE[10:0] Polarity of HS using PHS
HSE[10:0] HS End, Address 0x34[2:0], Address 0x36[7:0]
The position of this edge is controlled by placing a binary number into HSE[10:0]. The number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after EAV Code FF, 00, 00, XY (see Figure 20). HSE is set to 00000000000b, which is 0 LLC1 clock cycles from Count[0].
206H
The default value of HSE[9:0] is 000, indicating that the HS pulse ends zero pixels after falling edge of HS. For example: 1. To shift the HS toward active video by 20 LLC1s, add 20 LLC1s to both HSB and HSE, that is, HSB[10:0] = [00000010110], HSE[10:0] = 00000010100]. To shift the HS away from active video by 20 LLC1s, add 1696 LLC1s to both HSB and HSE (for NTSC), that is, HSB[10:0] = [11010100010], HSE[10:0] = [11010100000]. 1696 is derived from the NTSC total number of pixels = 1716.
The HS begin and HS end registers allow the user to freely position the HS output (pin) within the video line. The values in HSB[10:0] and HSE[10:0] are measured in pixel units from the falling edge of HS. Using both values, the user can program both the position and length of the HS output signal.
2.
HSB[10:0] HS Begin, Address 0x34[6:4], Address 0x35[7:0]
The position of this edge is controlled by placing a binary number into HSB[10:0]. The number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after EAV Code FF, 00, 00, XY (see Figure 20). HSB is set to 00000000010b, which is 2 LLC1 clock cycles from Count[0].
205H
To move 20 LLC1s away from active video is equal to subtracting 20 from 1716 and adding the result in binary to both HSB[10:0] and HSE[10:0].
The default value of HSB[10:0] is 0x002, indicating the HS pulse starts two pixels after the falling edge of HS.
PHS Polarity HS, Address 0x37[7]
The polarity of the HS pin can be inverted using the PHS bit. When PHS is 0 (default), HS is active high. When PHS is 1, HS is active low.
Table 55. HS Timing Parameters (see Figure 20)
207H
Standard NTSC NTSC Square Pixel PAL
HS Begin Adjust (HSB[10:0]) (Default) 00000000010b 00000000010b 00000000010b
HS End Adjust (HSE[10:0]) (Default) 00000000000b 00000000000b 00000000000b
Characteristic HS to Active Video (LLC1 Clock Cycles) (C in Figure 20) (Default) 272 276 284
208H
Active Video Samples/Line (D in Figure 20) 720Y + 720C = 1440 640Y + 640C = 1280 720Y + 720C = 1440
209H
Total LLC1 Clock Cycles (E in Figure 20) 1716 1560 1728
210H
LLC1 PIXEL BUS HS HSE[10:0] 4 LLC1 D E HSB[10:0] C E D
04997-020
Cr ACTIVE VIDEO
Y
FF
00
00
XY
80
10
80
10
80
10
FF
00
00 SAV
XY
Cb
Y
Cr
Y
Cb
Y
Cr
EAV
H BLANK
ACTIVE VIDEO
Figure 20. HS Timing
Rev. B | Page 39 of 100
ADV7183B
VS and FIELD Configuration
The following controls allow the user to configure the behavior of the VS and FIELD output pins and to generate embedded AV codes: * * * * * * ADV encoder-compatible signals via NEWAVMODE PVS, PF HVSTIM VSBHO, VSBHE VSEHO, VSEHE For NTSC control: * * * * NVBEGDELO, NVBEGDELE, NVBEGSIGN, NVBEG[4:0] NVENDDELO, NVENDDELE, NVENDSIGN, NVEND[4:0] NFTOGDELO, NFTOGDELE, NFTOGSIGN, NFTOG[4:0]
VSBHO VS Begin Horizontal Position Odd, Address 0x32[7]
The VSBHO and VSBHE bits select the position within a line at which the VS pin (not the bit in the AV code) becomes active. Some follow-on chips require the VS pin to change state only when HS is high/low. When VSBHO is 0 (default), the VS pin goes high at the middle of a line of video (odd field). When VSBHO is 1, the VS pin changes state at the start of a line (odd field).
VSBHE VS Begin Horizontal Position Even, Address 0x32[6]
The VSBHO and VSBHE bits select the position within a line at which the VS pin (not the bit in the AV code) becomes active. Some follow-on chips require the VS pin to change state when only HS is high/low. When VSBHE is 0, the VS pin goes high at the middle of a line of video (even field). When VSBHE is 1 (default), the VS pin changes state at the start of a line (even field).
For PAL control: * * * PVBEGDELO, PVBEGDELE, PVBEGSIGN, PVBEG[4:0] PVENDDELO, PVENDDELE, PVENDSIGN, PVEND[4:0] PFTOGDELO, PFTOGDELE, PFTOGSIGN, PFTOG[4:0]
VSEHO VS End Horizontal Position Odd, Address 0x33[7]
The VSEHO and VSEHE bits select the position within a line at which the VS pin (not the bit in the AV code) becomes active. Some follow-on chips require the VS pin to change state only when HS is high/low. When VSEHO is 0 (default), the VS pin goes low (inactive) at the middle of a line of video (odd field). When VSEHO is 1, the VS pin changes state at the start of a line (odd field).
NEWAVMODE New AV Mode, Address 0x31[4]
When NEWAVMODE is 0, EAV/SAV codes are generated to suit ADI encoders. No adjustments are possible. Setting NEWAVMODE to 1 (default) enables the manual posi-tion of the Vsync, Field, and AV codes using Register 0x34 to Register 0x37 and Register 0xE5 to Register 0xEA. Default register settings are CCIR656-compliant; see Figure 21 for NTSC and Figure 26 for PAL. For recommended manual user settings, see Table 56 and Figure 22 for NTSC; see Table 57 and Figure 27 for PAL.
21H 21H 213H 214H 215H 216H
VSEHE VS End Horizontal Position Even, Address 0x33[6]
The VSEHO and VSEHE bits select the position within a line at which the VS pin (not the bit in the AV code) becomes active. Some follow-on chips require the VS pin to change state only when HS is high/low. When VSEHE is 0 (default), the VS pin goes low (inactive) at the middle of a line of video (even field). When VSEHE is 1, the VS pin changes state at the start of a line (even field).
HVSTIM Horizontal VS Timing, Address 0x31[3]
The HVSTIM bit allows the user to select where the VS signal is being asserted within a line of video. Some interface circuitry can require VS to go low while HS is low. When HVSTIM is 0 (default), the start of the line is relative to HSE. When HVSTIM is 1, the start of the line is relative to HSB.
PVS Polarity VS, Address 0x37[5]
The polarity of the VS pin can be inverted using the PVS bit. When PVS is 0 (default), VS is active high.
Rev. B | Page 40 of 100
ADV7183B
When PVS is 1, VS is active low. PF Polarity FIELD, Address 0x37[3]
The polarity of the FIELD pin can be inverted using the PF bit. When PF is 0 (default), FIELD is active high. When PF is 1, FIELD is active low.
FIELD 1 525 OUTPUT VIDEO H 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 21 22
V NVBEG[4:0] = 0x5 F NFTOG[4:0] = 0x3 FIELD 2 262 OUTPUT VIDEO H V NVBEG[4:0] = 0x5 F
04997-021
NVEND[4:0] = 0x4
1BT.656-4
REG 0x04, BIT 7 = 1
263
264
265
266
267
268
269
270
271
272
273
274
275
276
283
284
285
NVEND[4:0] = 0x4
1BT.656-4
REG 0x04, BIT 7 = 1
NFTOG[4:0] = 0x3
1APPLIES
IF NEWAVMODE = 0: MUST BE MANUALLY SHIFTED IF NEWAVMODE = 1.
Figure 21. NTSC Default (BT.656). The Polarity of H, V, and F is Embedded in the Data.
FIELD 1 525 OUTPUT VIDEO HS OUTPUT VS OUTPUT FIELD OUTPUT NVBEG[4:0] =0x0 NVEND[4:0] = 0x3 NFTOG[4:0] = 0x5 FIELD 2 262 OUTPUT VIDEO HS OUTPUT VS OUTPUT NVBEG[4:0] = 0x0 FIELD OUTPUT NFTOG[4:0] = 0x5
04997-022
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
21
22
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
284
285
NVEND[4:0] = 0x3
Figure 22. NTSC Typical Vsync/Field Positions Using Register Writes in Table 56
217H
Rev. B | Page 41 of 100
ADV7183B
Table 56. Recommended User Settings for NTSC (See Figure 22)
218H
Register 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0xE5 0xE6 0xE7
Register Name Vsync Field Control 1 Vsync Field Control 2 Vsync Field Control 3 Hsync Pos. Control 1 Hsync Pos. Control 2 Hsync Pos. Control 3 Polarity NTSV_V_Bit_Beg NTSC_V_Bit_End NTSC_F_Bit_Tog
Write 0x1A 0x81 0x84 0x00 0x00 0x7D 0xA1 0x41 0x84 0x06
1
NVBEGSIGN
0
NVBEGDELO NTSC Vsync Begin Delay on Odd Field, Address 0xE5[7]
When NVBEGDELO is 0 (default), there is no delay. Setting NVBEGDELO to 1, delay Vsync going high on an odd field by a line relative to NVBEG.
ADVANCE BEGIN OF VSYNC BY NVBEG[4:0]
DELAY BEGIN OF VSYNC BY NVBEG[4:0]
NOT VALID FOR USER PROGRAMMING ODD FIELD? YES NO
NVBEGDELE NTSC Vsync Begin Delay on Even Field, Address 0xE5[6]
When NVBEGDELE is 0 (default), there is no delay.
NVBEGDELO
NVBEGDELE
Setting NVBEGDELE to 1 delays Vsync going high on an even field by a line relative to NVBEG.
1
0
0
1
NVBEGSIGN NTSC Vsync Begin Sign, Address 0xE5[5]
ADDITIONAL DELAY BY 1 LINE ADDITIONAL DELAY BY 1 LINE
Setting NVBEGSIGN to 0 delays the start of Vsync. Set for user manual programming. Setting NVBEGSIGN to 1 (default), advances the start of Vsync. Not recommended for user programming.
VSBHO
VSBHE
NVBEG[4:0] NTSC Vsync Begin, Address 0xE5[4:0]
1 0 0 1
ADVANCE BY 0.5 LINE
ADVANCE BY 0.5 LINE
The default value of NVBEG is 00101, indicating the NTSC Vsync begin position. For all NTSC/PAL Vsync timing controls, both the V bit in the AV code and the Vsync on the VS pin are modified.
VSYNC BEGIN
Figure 23. NTSC Vsync Begin
04997-023
Rev. B | Page 42 of 100
ADV7183B
NVEND NTSC[4:0] Vsync End, Address 0xE6[4:0]
1 NVENDSIGN 0
The default value of NVEND is 00100, indicating the NTSC Vsync end position. For all NTSC/PAL Vsync timing controls, both the V bit in the AV code and the Vsync on the VS pin are modified.
ADVANCE END OF VSYNC BY NVEND[4:0]
DELAY END OF VSYNC BY NVEND[4:0]
NOT VALID FOR USER PROGRAMMING ODD FIELD? YES NO
NFTOGDELO NTSC Field Toggle Delay on Odd Field, Address 0xE7[7]
When NFTOGDELO is 0 (default), there is no delay.
NVENDDELO
NVENDDELE
Setting NFTOGDELO to 1 delays the field toggle/transition on an odd field by a line relative to NFTOG.
1
0
0
1
ADDITIONAL DELAY BY 1 LINE
ADDITIONAL DELAY BY 1 LINE
NFTOGDELE NTSC Field Toggle Delay on Even Field, Address 0xE7[6]
When NFTOGDELE is 0, there is no delay. Setting NFTOGDELE to 1 (default) delays the field toggle/ transition on an even field by a line relative to NFTOG.
VSEHO
VSEHE
1
0
0
1
1
NFTOGSIGN
0
ADVANCE BY 0.5 LINE
ADVANCE BY 0.5 LINE
ADVANCE TOGGLE OF FIELD BY NFTOG[4:0]
DELAY TOGGLE OF FIELD BY NFTOG[4:0]
VSYNC END
04997-024
NOT VALID FOR USER PROGRAMMING ODD FIELD? YES NO
Figure 24. NTSC Vsync End
NVENDDELO NTSC Vsync End Delay on Odd Field, Address 0xE6[7]
When NVENDDELO is 0 (default), there is no delay.
NFTOGDELO
NFTOGDELE
1
0
0
1
Setting NVENDDELO to 1 delays Vsync from going low on an odd field by a line relative to NVEND.
NVENDDELE NTSC Vsync End Delay on Even Field, Address 0xE6[6]
When NVENDDELE is set to 0 (default), there is no delay. Setting NVENDDELE to 1 delays Vsync from going low on an even field by a line relative to NVEND.
ADDITIONAL DELAY BY 1 LINE
ADDITIONAL DELAY BY 1 LINE
FIELD TOGGLE
Figure 25. NTSC FIELD Toggle
NVENDSIGN NTSC Vsync End Sign, Address 0xE6[5]
Setting NVENDSIGN to 0 (default) delays the end of Vsync (default). Set for user manual programming. Setting NVENDSIGN to 1 advances the end of Vsync. Not recommended for user programming.
NFTOGSIGN NTSC Field Toggle Sign, Address 0xE7[5]
Setting NFTOGSIGN to 0 delays the field transition. Set for user manual programming. Setting NFTOGSIGN to 1 (default) advances the field transition. Not recommended for user programming.
Rev. B | Page 43 of 100
04997-025
ADV7183B
NFTOG[4:0] NTSC Field Toggle, Address 0xE7[4:0]
The default value of NFTOG is 00011, indicating the NTSC Field toggle position. For all NTSC/PAL Field timing controls, both the F bit in the AV code and the Field signal on the FIELD pin are modified.
Table 57. Recommended User Settings for PAL (see Figure 27)
219H
Register 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0xE8 0xE9 0xEA
4 5 6 7 8
Register Name Vsync Field Control 1 Vsync Field Control 2 Vsync Field Control 3 Hsync Pos. Control 1 Hsync Pos. Control 2 Hsync Pos. Control 3 Polarity PAL_V_Bit_Beg PAL_V_Bit_End PAL_F_Bit_Tog
9 10 22 23
Write 0x1A 0x81 0x84 0x00 0x00 0x7D 0x29 0x41 0x84 0x06
24
FIELD 1 622 OUTPUT VIDEO H 623 624 625 1 2 3
V PVBEG[4:0] = 0x5 F PFTOG[4:0] = 0x3 FIELD 2 310 OUTPUT VIDEO H 311 312 313 314 315 316 317 318 319 320 321 322 335 336 337 PVEND[4:0] = 0x4
V PVBEG[4:0] = 0x5 F PFTOG[4:0] = 0x3 PVEND[4:0] = 0x4
04997-026
Figure 26. PAL Default (BT.656). The Polarity of H, V, and F is Embedded in the Data.
FIELD 1 622 OUTPUT VIDEO HS OUTPUT VS OUTPUT FIELD OUTPUT FIELD 2 310 OUTPUT VIDEO HS OUTPUT VS OUTPUT PVBEG[4:0] = 0x1 FIELD OUTPUT PFTOG[4:0] = 0x6 PVEND[4:0] = 0x4
04997-027
623
624
625
1
2
3
4
5
6
7
8
9
10
11
23
24
PVBEG[4:0] = 0x1
PVEND[4:0] = 0x4 PFTOG[4:0] = 0x6
311
312
313
314
315
316
317
318
319
320
321
322
323
336
337
Figure 27. PAL Typical Vsync/Field Positions Using Register Writes in Table 57
20H
Rev. B | Page 44 of 100
ADV7183B
1 PVBEGSIGN 0
PVBEG[4:0] PAL Vsync Begin, Address 0xE8[4:0]
ADVANCE BEGIN OF VSYNC BY PVBEG[4:0] DELAY BEGIN OF VSYNC BY PVBEG[4:0]
The default value of PVBEG is 00101, indicating the PAL Vsync begin position. For all NTSC/PAL Vsync timing controls, both the V bit in the AV code and the Vsync on the VS pin are modified.
NOT VALID FOR USER PROGRAMMING ODD FIELD? YES NO
1
PVENDSIGN
0
PVBEGDELO
PVBEGDELE
ADVANCE END OF VSYNC BY PVEND[4:0] DELAY END OF VSYNC BY PVEND[4:0]
1
0
0
1
NOT VALID FOR USER PROGRAMMING ODD FIELD? YES NO
ADDITIONAL DELAY BY 1 LINE
ADDITIONAL DELAY BY 1 LINE
VSBHO
VSBHE
PVENDDELO
PVENDDELE
1
0
0
1
1
0
0
1
ADVANCE BY 0.5 LINE
ADVANCE BY 0.5 LINE
ADDITIONAL DELAY BY 1 LINE
ADDITIONAL DELAY BY 1 LINE
VSYNC BEGIN
04997-028
Figure 28. PAL Vsync Begin
VSEHO
VSEHE
1
0
0
1
PVBEGDELO PAL Vsync Begin Delay on Odd Field, Address 0xE8[7]
When PVBEGDELO is 0 (default), there is no delay. Setting PVBEGDELO to 1 delays Vsync going high on an odd field by a line relative to PVBEG.
ADVANCE BY 0.5 LINE
ADVANCE BY 0.5 LINE
VSYNC END
Figure 29. PAL Vsync End
PVBEGDELE PAL Vsync Begin Delay on Even Field, Address 0xE8[6]
When PVBEGDELE is 0, there is no delay. Setting PVBEGDELE to 1 (default) delays Vsync going high on an even field by a line relative to PVBEG.
PVENDDELO PAL Vsync End Delay on Odd Field, Address 0xE9[7]
When PVENDDELO is 0 (default), there is no delay. Setting PVENDDELO to 1 delays Vsync going low on an odd field by a line relative to PVEND.
PVBEGSIGN PAL Vsync Begin Sign, Address 0xE8[5]
Setting PVBEGSIGN to 0 delays the beginning of Vsync. Set for user manual programming. Setting PVBEGSIGN to 1 (default) advances the beginning of Vsync. Not recommended for user programming.
PVENDDELE PAL Vsync End Delay on Even Field, Address 0xE9[6]
When PVENDDELE is 0 (default), there is no delay. Setting PVENDDELE to 1 delays Vsync going low on an even field by a line relative to PVEND.
Rev. B | Page 45 of 100
04997-029
ADV7183B
PVENDSIGN PAL Vsync End Sign, Address 0xE9[5]
Setting PVENDSIGN to 0 (default) delays the end of Vsync. Set for user manual programming. Setting PVENDSIGN to 1 advances the end of Vsync. Not recommended for user programming.
1 PFTOGSIGN 0
ADVANCE TOGGLE OF FIELD BY PTOG[4:0]
DELAY TOGGLE OF FIELD BY PFTOG[4:0]
PVEND[4:0] PAL Vsync End, Address 0xE9[4:0]
The default value of PVEND is 10100, indicating the PAL Vsync end position. For all NTSC/PAL Vsync timing controls, both the V bit in the AV code and the Vsync on the VS pin are modified.
NOT VALID FOR USER PROGRAMMING ODD FIELD? YES NO
PFTOGDELO
PFTOGDELE
PFTOGDELO PAL Field Toggle Delay on Odd Field, Address 0xEA[7]
When PFTOGDELO is 0 (default), there is no delay. Setting PFTOGDELO to 1 delays the F toggle/transition on an odd field by a line relative to PFTOG.
1
0
0
1
ADDITIONAL DELAY BY 1 LINE
ADDITIONAL DELAY BY 1 LINE
PFTOGDELE PAL Field Toggle Delay on Even Field, Address 0xEA[6]
When PFTOGDELE is 0, there is no delay. Setting PFTOGDELE to 1 (default) delays the F toggle/ transition on an even field by a line relative to PFTOG.
FIELD TOGGLE
Figure 30. PAL F Toggle
SYNC PROCESSING
The ADV7183B has two additional sync processing blocks that postprocess the raw synchronization information extracted from the digitized input video. If desired, the blocks can be disabled via the following two I2C bits.
PFTOGSIGN PAL Field Toggle Sign, Address 0xEA[5]
Setting PFTOGSIGN to 0 delays the field transition. Set for user manual programming. Setting PFTOGSIGN to 1 (default) advances the field transition. Not recommended for user programming.
ENHSPLL Enable Hsync Processor, Address 0x01[6]
The Hsync processor is designed to filter incoming Hsyncs that have been corrupted by noise, providing improved performance for video signals with stable time bases but poor SNR. Setting ENHSPLL to 0 disables the Hsync processor. Setting ENHSPLL to 1 (default) enables the Hsync processor.
PFTOG PAL Field Toggle, Address 0xEA[4:0]
The default value of PFTOG is 00011, indicating the PAL field toggle position. For all NTSC/PAL Field timing controls, the F bit in the AV code and the field signal on the FIELD/DE pin are modified.
ENVSPROC Enable Vsync Processor, Address 0x01[3]
This block provides extra filtering of the detected Vsyncs to give improved vertical lock. Setting ENVSPROC to 0 disables the Vsync processor. Setting ENVSPROC to 1 (default) enables the Vsync processor.
Rev. B | Page 46 of 100
04997-030
ADV7183B
VBI DATA DECODE
The following low data rate VBI signals can be decoded by the ADV7183B: * * * * * Wide screen signaling (WSS) Copy generation management systems (CGMS) Closed captioning (CCAP) EDTV Gemstar 1x- and 2x-compatible data recovery
CCAPD Closed Caption Detected, Address 0x90[1]
A Logic 1 for this bit indicates that the data in the CCAP1 and CCAP2 registers is valid. The CCAPD bit goes high if the rising edge of the start bit is detected within a time window and if the polarity of the parity bit matches the data transmitted. When CCAPD is 0, no CCAP sequences are detected and confidence in the decoded data is low. When CCAPD is 1, the CCAP sequence is detected and confidence in the decoded data is high.
The presence of any of the above signals is detected and, if applicable, a parity check is performed. The result of this testing is contained in a confidence bit in the VBI Info[7:0] register. Users are encouraged to first examine the VBI Info register before reading the corresponding data registers. All VBI data decode bits are read only. All VBI data registers are double-buffered with the field signals. This means that data is extracted from the video lines and appears in the appropriate I2C registers with the next field transition. They are then static until the next field. The user should start an I2C read sequence with VS by first examining the VBI Info register. Then, depending on what data was detected, the appropriate data registers should be read. Note that the data registers are filled with decoded VBI data even if their corresponding detection bits are low; it is likely that bits within the decoded data stream are wrong. The closed captioning data (CCAP) is available in the I2C registers and is also inserted into the output video data stream during horizontal blanking. The Gemstar-compatible data is not available in the I2C registers and is inserted into the data stream only during horizontal blanking.
EDTVD EDTV Sequence Detected, Address 0x90[2]
A Logic 1 for this bit indicates the data in the EDTV1, 2, 3 registers is valid. The EDTVD bit goes high if the rising edge of the start bit is detected within a time window and if the polarity of the parity bit matches the data transmitted. When EDTVD is 0, no EDTV sequence is detected and confidence in the decoded data is low. When EDTVD is 1, an EDTV sequence is detected and confidence in the decoded data is high.
CGMSD CGMS-A Sequence Detected, Address 0x90[3]
Logic 1 for this bit indicates that the data in the CGMS1, 2, 3 registers is valid. The CGMSD bit goes high if a valid CRC checksum has been calculated from a received CGMS packet. When CGMSD is 0, no CGMS transmission is detected and confidence in the decoded data is low. When CGMSD is 1, the CGMS sequence is decoded and confidence in the decoded data is high.
CRC_ENABLE CRC, Address 0xB2[2]
For certain video sources, the CRC data bits can have an invalid format. In these circumstances, the CRC checksum validation procedure can be disabled. The CGMSD bit goes high if the rising edge of the start bit is detected within a time window. When CRC_ENABLE is 0, no CRC check is performed. The CGMSD bit goes high if the rising edge of the start bit is detected within a time window. When CRC_ENABLE is 1 (default), CRC checksum is used to validate the CGMS sequence. The CGMSD bit goes high for a valid checksum. The default is ADI's recommended setting.
WSSD Wide Screen Signaling Detected, Address 0x90[0]
Logic 1 for this bit indicates the data in the WSS1 and WSS2 registers is valid. The WSSD bit goes high if the rising edge of the start bit is detected within a time window and if the polarity of the parity bit matches the data transmitted. When WSSD is 0, no WSS is detected and confidence in the decoded data is low. When WSSD is 1, WSS is detected and confidence in the decoded data is high.
Rev. B | Page 47 of 100
ADV7183B
Wide Screen Signaling Data WSS1[7:0], Address 0x91[7:0], WSS2[7:0], Address 0x92[7:0]
Figure 31 shows the bit correspondence between the analog video waveform and the WSS1/WSS2 registers. WSS2[7:6] are undetermined and should be masked out by software.
21H 2H
EDTV Data Registers EDTV1[7:0], Address 0x93[7:0], EDTV2[7:0], Address 0x94[7:0], EDTV3[7:0], Address 0x95[7:0]
Figure 32 shows the bit correspondence between the analog video waveform and the EDTV1/EDTV2/EDTV3 registers. EDTV3[7:6] are undetermined and should be masked out by software. EDTV3[5] is reserved for future use and, for now, contains 0. The 3 LSBs of the EDTV waveform are currently not supported.
WSS1[7:0] 0
RUN-IN SEQUENCE
WSS2[5:0] 6 7 0 1 2 3 4 5 ACTIVE VIDEO
1
2
3
4
5
START CODE
11.0s 42.5s
04997-031
38.4s
Figure 31. WSS Data Extraction
Table 58. WSS Access Information
Signal Name WSS1[7:0] WSS2[5:0] Register Location WSS 1[7:0] WSS 2[5:0] 145d 146d Address 0x91 0x92 Register Default Value Readback Only Readback Only
EDTV1[7:0] 0 1 2
EDTV2[7:0]
EDTV3[5:0]
NOT SUPPORTED 3 4 5 6 7 0 1 234 5 67 0 12 3 4 5
Figure 32. EDTV Data Extraction
Table 59. EDTV Access Information
Signal Name EDTV1[7:0] EDTV2[7:0] EDTV3[7:0] Register Location EDTV 1[7:0] EDTV 2[7:0] EDTV 3[7:0] 147d 148d 149d Address 0x93 0x94 0x95 Register Default Value Readback only Readback only Readback only
Rev. B | Page 48 of 100
04997-032
ADV7183B
CGMS Data Registers CGMS1[7:0], Address 0x96[7:0], CGMS2[7:0], Address 0x97[7:0], CGMS3[7:0], Address 0x98[7:0]
24H
Closed Caption Data Registers CCAP1[7:0], Address 0x99[7:0], CCAP2[7:0], Address 0x9A[7:0]
Figure 34 shows the bit correspondence between the analog video waveform and the CCAP1/CCAP2 registers. CCAP1[7] contains the parity bit from the first word. CCAP2[7] contains the parity bit from the second word. Refer to the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C[0] section.
25H
Figure 33 shows the bit correspondence between the analog video waveform and the CGMS1/CGMS2/CGMS3 registers. CGMS3[7:4] are undetermined and should be masked out by software.
23H
+100 IRE REF +70 IRE 0 1 2 CGMS1[7:0] 3 4 5 6 7 0 1 CGMS2[7:0] 2 3 4 5 6 7 0 CGMS3[3:0] 1 2 3
0 IRE 49.1ms 0.5s CRC SEQUENCE 2.235s 20ns
04997-033
-40 IRE
11.2s
Figure 33. CGMS Data Extraction
Table 60. CGMS Access Information
Signal Name CGMS1[7:0] CGMS2[7:0] CGMS3[3:0] Register Location CGMS 1[7:0] CGMS 2[7:0] CGMS 3[3:0] 150d 151d 152d Address 0x96 0x97 0x98 Register Default Value Readback only Readback only Readback only
10.5 0.25s
12.91s
7 CYCLES OF 0.5035MHz (CLOCK RUN-IN)
CCAP1[7:0]
CCAP2[7:0]
0123456 701234567 50 IRE S T A R T BYTE 0 40 IRE REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE 10.003s 27.382s 33.764s P A R I T Y BYTE 1 P A R I T Y
Figure 34. Closed Caption Data Extraction
Table 61. CCAP Access Information
Signal Name CCAP1[7:0] CCAP2[7:0] Register Location CCAP1[7:0] CCAP2[7:0] 153d 154d Address 0x99 0x9A Register Default Value Readback only Readback only
Rev. B | Page 49 of 100
04997-034
ADV7183B
Letterbox Detection
Incoming video signals may conform to different aspect ratios (16:9 wide screen of 4:3 standard). For certain transmissions in the wide screen format, a digital sequence (WSS) is transmitted with the video signal. If a WSS sequence is provided, the aspect ratio of the video can be derived from the digitally decoded bits WSS contains. In the absence of a WSS sequence, letterbox detection may be used to find wide screen signals. The detection algorithm examines the active video content of lines at the start and end of a field. If black lines are detected, this indicates that the picture currently displayed is in wide screen format. The active video content (luminance magnitude) over a line of video is summed together. At the end of a line, this accumulated value is compared with a threshold, and a decision is made as to whether or not a particular line is black. The threshold value needed depends on the type of input signal; some control is provided via LB_TH[4:0].
LB_LCT[7:0] Letterbox Line Count Top, Address 0x9B[7:0], LB_LCM[7:0] Letterbox Line Count Mid, Address 0x9C[7:0], LB_LCB[7:0] Letterbox Line Count Bottom, Address 0x9D[7:0]
Table 62. LB_LCx Access Information
Signal Name LB_LCT[7:0] LB_LCM[7:0] LB_LCB[7:0] Address 0x9B 0x9C 0x9D Register Default Value Readback only Readback only Readback only
LB_TH[4:0] Letterbox Threshold Control, Address 0xDC[4:0]
Table 63. LB_TH Function
LB_TH[4:0] 01100 (default) 01101 to 10000 00000 to 01011 Description Default threshold for detection of black lines Increase threshold (need larger active video content before identifying nonblack lines) Decrease threshold (even small noise levels can cause the detection of nonblack lines)
Detection at the Start of a Field
The ADV7183B expects a section of at least six consecutive black lines of video at the top of a field. Once those lines are detected, Register LB_LCT[7:0] reports back the number of black lines actually found. By default, the ADV7183B starts looking for those black lines in sync with the beginning of active video, for example, straight after the last VBI video line. LB_SL[3:0] allows the user to set the start of letterbox detection from the beginning of a frame on a line-by-line basis. The detection window closes in the middle of the field.
LB_SL[3:0] Letterbox Start Line, Address 0xDD[7:4]
The LB_SL[3:0] bits are set at 0100b by default. This means the letterbox detection window starts after the EDTV VBI data line. For an NTSC signal, this window is from Line 23 to Line 286. Changing the bits to 0101, the detection window starts on Line 24 and ends on Line 287.
LB_EL[3:0] Letterbox End Line, Address 0xDD[3:0]
The LB_EL[3:0] bits are set at 1101b by default. This means the letterbox detection window ends with the last active video line. For an NTSC signal, this window is from Line 262 to Line 525. Changing the bits to 1100, the detection window starts on Line 261 and ends on Line 254.
Detection at the End of a Field
The ADV7183B expects at least six continuous lines of black video at the bottom of a field before reporting back the number of lines actually found via the LB_LCB[7:0] value. The activity window for letterbox detection (end of field) starts in the middle of an active field. Its end is programmable via LB_EL[3:0].
Gemstar Data Recovery
The Gemstar-compatible data recovery block (GSCD) supports 1x and 2x data transmissions. It can also serve as a closed caption decoder. Gemstar-compatible data transmissions can occur only in NTSC. Closed caption data can be decoded in both PAL and NTSC. The block is configured via I2C in the following ways: * * * GDECEL[15:0] allow data recovery on selected video lines on even fields to be enabled and disabled. GDECOL[15:0] enable the data recovery on selected lines for odd fields. GDECAD configures the way in which data is embedded in the video data stream.
Detection at the Midrange
Some transmissions of wide screen video include subtitles within the lower black box. If the ADV7183B finds at least two black lines followed by some more nonblack video, for example, the subtitle, and is then followed by the remainder of the bottom black block, it reports back a midcount via LB_LCM[7:0]. If no subtitles are found, LB_LCM[7:0] reports the same number as LB_LCB[7:0]. There is a 2-field delay in the reporting of any line count parameters. There is no letterbox detected bit. The user is asked to read the LB_LCT[7:0] and LB_LCB[7:0] register values and to conclude whether or not the letterbox-type video is present in software.
Rev. B | Page 50 of 100
ADV7183B
The recovered data is not available through I2C, but is inserted into the horizontal blanking period of an ITU-R BT656-compatible data stream. The data format is intended to comply with the recommendation by the International Telecommunications Union, ITU-R BT.1364. For more information, see the ITU website at www.itu.ch. See Figure 35.
6H 26H
Entries within the packet are as follows: * * Fixed preamble sequence of 0x00, 0xFF, 0xFF. Data identification word (DID). The value for the DID marking a Gemstar or CCAP data packet is 0x140 (10-bit value). Secondary data identification word (SDID) contains information about the video line from which data was retrieved, whether the Gemstar transmission was of 1x or 2x format, and whether it was retrieved from an even or odd field. Data count byte, giving the number of user data-words that follow. User data section. Optional padding to ensure the length of the user dataword section of a packet is a multiple of four bytes (requirement as set in ITU-R BT.1364). Checksum byte.
The format of the data packet depends on the following criteria: * * Transmission is 1x or 2x. Data is output in 8-bit or 4-bit format (see the description of the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C[0] bit).
27H
*
* * *
*
Data is closed caption (CCAP) or Gemstar-compatible.
Data packets are output if the corresponding enable bit is set (see the GDECEL and GDECOL descriptions) and if the decoder detects the presence of data. This means that for video lines where no data has been decoded, no data packet is output even if the corresponding line enable bit is set. Each data packet starts immediately after the EAV code of the preceding line. See Figure 35 and Table 64, which show the overall structure of the data packet.
28H 29H
*
230H
Table 64 lists the values within a generic data packet that is output by the ADV7183B in 8-bit format.
DATA IDENTIFICATION
SECONDARY DATA IDENTIFICATION DATA COUNT OPTIONAL PADDING BYTES CHECK SUM
04997-035
00
FF
FF
DID
SDID
USER DATA
PREAMBLE FOR ANCILLARY DATA
USER DATA (4 OR 8 WORDS)
Figure 35. Gemstar and CCAP Embedded Data Packet (Generic)
Table 64. Generic Data Output Packet
Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D[9] 0 1 1 0 !EP !EP !EP !EP !EP !EP !EP !EP !EP !EP !CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 0 0 0 0 CS[7] D[6] 0 1 1 1 2X 0 0 0 0 0 0 0 0 0 CS[6] D[5] 0 1 1 0 0 D[3] 0 1 1 0 Line[3:0] 0 DC[1] Word1[7:4] Word1[3:0] Word2[7:4] Word2[3:0] Word3[7:4] Word3[3:0] Word4[7:4] Word4[3:0] CS[4] CS[3] D[4] 0 1 1 0 D[2] 0 1 1 0 DC[0] D[1] 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 D[0] 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count (DC) User data-words User data-words User data-words User data-words User data-words User data-words User data-words User data-words Checksum
CS[5]
CS[2]
Rev. B | Page 51 of 100
ADV7183B
Table 65. Data Byte Allocation
2x 1 1 0 0 Raw Information Bytes Retrieved from the Video Line 4 4 2 2 GDECAD 0 1 0 1 User Data-Words (Including Padding) 8 4 4 4 Padding Bytes 0 0 0 2 DC[1:0] 10 01 01 01
Gemstar Bit Names
* DID. The data identification value is 0x140 (10-bit value). Care has been taken that in 8-bit systems, the two LSBs do not carry vital information. EP and !EP. The EP bit is set to ensure even parity on the data-word D[8:0]. Even parity means there will always be an even number of 1s within the D[8:0] bit arrangement. This includes the EP bit. !EP describes the logic inverse of EP and is output on D[9]. The !EP is output to ensure that the reserved codes of 00 and FF cannot happen. EF. Even field identifier. EF = 1 indicates that the data was recovered from a video line on an even field.
*
*
CS[8:2]. The checksum is provided to determine the integrity of the ancillary data packet. It is calculated by summing up D[8:2] of DID, SDID, the Data Count byte, and all UDWs, and ignoring any overflow during the summation. Since all data bytes that are used to calculate the checksum have their two LSBs set to 0, the CS[1:0] bits are also always 0. !CS[8] describes the logic inversion of CS[8]. The value !CS[8] is included in the checksum entry of the data packet to ensure the reserved values of 0x00 and 0xFF do not occur.
* * *
Table 66 to Table 71 outline the possible data packages.
234H 235H
2X. This bit indicates whether the data sliced was in Gemstar 1x or 2x format. A high indicates 2x format. Line[3:0]. This entry provides a code that is unique for each of the possible 16 source lines of video from which Gemstar data can be retrieved. Refer to Table 74 and Table 75.
231H 23H
Gemstar 2x Format, Half-Byte Output Mode
Half-byte output mode is selected by setting CDECAD = 0; full-byte output mode is selected by setting CDECAD = 1. See the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C[0] section.
236H
Gemstar 1x Format
Half-byte output mode is selected by setting CDECAD = 0; full-byte output mode is selected by setting CDECAD = 1. See the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C[0] section.
237H
*
DC[1:0]. Data count value. The number of user data-words in the packet divided by 4. The number of user data-words (UDW) in any packet must be an integral number of 4. Padding is required at the end, if necessary, as set in ITU-R BT.1364. See Table 65.
23H
*
The 2X bit determines whether the raw information retrieved from the video line was 2 or 4 bytes. The state of the GDECAD bit affects whether the bytes are transmitted straight (that is, two bytes transmitted as two bytes) or whether they are split into nibbles (that is, two bytes transmitted as four half bytes). Padding bytes are then added where necessary.
Rev. B | Page 52 of 100
ADV7183B
Table 66. Gemstar 2x Data, Half-Byte Mode
Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D[9] 0 1 1 0 !EP !EP !EP !EP !EP !EP !EP !EP !EP !EP !CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 0 0 0 0 CS[7] D[6] 0 1 1 1 1 0 0 0 0 0 0 0 0 0 CS[6] D[5] 0 1 1 0 0 D[3] 0 1 1 0 Line[3:0] 0 1 Gemstar Word1[7:4] Gemstar Word1[3:0] Gemstar Word2[7:4] Gemstar Word2[3:0] Gemstar Word3[7:4] Gemstar Word3[3:0] Gemstar Word4[7:4] Gemstar Word4[3:0] CS[4] CS[3] D[4] 0 1 1 0 D[2] 0 1 1 0 0 D[1] 0 1 1 0 0 0 0 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words User data-words User data-words User data-words User data-words Checksum
CS[5]
CS[2]
Table 67. Gemstar 2x Data, Full-Byte Mode
Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 !EP !EP D[8] 0 1 1 1 EP EP D[7] 0 1 1 0 EF 0 D[6] D[5] 0 0 1 1 1 1 1 0 1 0 0 Gemstar Word1[7:0] Gemstar Word2[7:0] Gemstar Word3[7:0] Gemstar Word4[7:0] CS[6] CS[5] D[4] D[3] 0 0 1 1 1 1 0 0 Line[3:0] 0 0 D[2] 0 1 1 0 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words Checksum
!CS[8]
CS[8]
CS[7]
CS[4]
CS[3]
CS[2]
Table 68. Gemstar 1x Data, Half-Byte Mode
Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 !EP !EP !EP !EP !EP !EP !CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 CS[7] D[6] 0 1 1 1 0 0 0 0 0 0 CS[6] D[5] 0 1 1 0 0 D[3] 0 1 1 0 Line[3:0] 0 0 Gemstar Word1[7:4] Gemstar Word1[3:0] Gemstar Word2[7:4] Gemstar Word2[3:0] CS[4] CS[3] D[4] 0 1 1 0 D[2] 0 1 1 0 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words Checksum
CS[5]
CS[2]
Rev. B | Page 53 of 100
ADV7183B
Table 69. Gemstar 1x Data, Full-Byte Mode
Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 !EP !EP D[8] 0 1 1 1 EP EP D[7] 0 1 1 0 EF 0 D[6] D[5] 0 0 1 1 1 1 1 0 0 0 0 Gemstar Word1[7:0] Gemstar Word2[7:0] 0 0 0 0 CS[6] CS[5] D[4] 0 1 1 0 0 D[3] 0 1 1 0 Line[3:0] 0 D[2] 0 1 1 0 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words UDW padding 0x200 UDW padding 0x200 Checksum
1 1 !CS[8]
0 0 CS[8]
0 0 CS[7]
0 0 CS[4]
0 0 CS[3]
0 0 CS[2]
Table 70. NTSC CCAP Data, Half-Byte Mode
Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 !EP !EP !EP !EP !EP !EP !CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 CS[7] D[6] 0 1 1 1 0 0 0 0 0 0 CS[6] D[5] 0 1 1 0 1 0 D[4] D[3] 0 0 1 1 1 1 0 0 0 1 0 0 CCAP Word1[7:4] CCAP Word1[3:0] CCAP Word2[7:4] CCAP Word2[3:0] CS[4] CS[3] D[2] 0 1 1 0 1 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words Checksum
CS[5]
CS[2]
Table 71. NTSC CCAP Data, Full-Byte Mode
Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 !EP !EP D[8] 0 1 1 1 EP EP D[7] 0 1 1 0 EF 0 D[6] D[5] 0 0 1 1 1 1 1 0 0 1 0 0 CCAP Word1[7:0] CCAP Word2[7:0] 0 0 0 0 CS[6] CS[5] D[4] 0 1 1 0 0 0 D[3] 0 1 1 0 1 0 D[2] 0 1 1 0 1 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words UDW padding 0x200 UDW padding 0x200 Checksum
1 1 !CS[8]
0 0 CS[8]
0 0 CS[7]
0 0 CS[4]
0 0 CS[3]
0 0 CS[2]
Rev. B | Page 54 of 100
ADV7183B
NTSC CCAP Data
Half-byte output mode is selected by setting CDECAD = 0; the full-byte mode is enabled by CDECAD = 1. See the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C[0] section. The data packet formats are shown in Table 72 and Table 73.
238H 239H 240H
PAL CCAP Data
Half-byte output mode is selected by setting CDECAD = 0; full-byte output mode is selected by setting CDECAD = 1. See the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C[0] section.
24H 243H
Table 72 and Table 73 list the bytes of the data packet.
24H
Only closed caption data can be embedded in the output data stream. NTSC closed caption data is sliced on Line 21d on even and odd fields. The corresponding enable bit has to be set high. See the and the GDECOL[15:0] Gemstar Decoding Odd Lines, Address 0x4A[7:0]; Address 0x4B[7:0] sections.
241H
Only closed caption data can be embedded in the output data stream. PAL closed caption data is sliced from Line 22 and Line 335. The corresponding enable bits have to be set. See the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C[0] and GDECOL[15:0] Gemstar Decoding Odd Lines, Address 0x4A[7:0]; Address 0x4B[7:0] sections.
245H
Table 72. PAL CCAP Data, Half-Byte Mode
Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 !EP !EP !EP !EP !EP !EP !CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 CS[7] D[6] 0 1 1 1 0 0 0 0 0 0 CS[6] D[5] 0 1 1 0 1 0 D[4] D[3] 0 0 1 1 1 1 0 0 0 1 0 0 CCAP Word1[7:4] CCAP Word1[3:0] CCAP Word2[7:4] CCAP Word2[3:0] CS[4] CS[3] D[2] 0 1 1 0 0 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words Checksum
CS[5]
CS[2]
Table 73. PAL CCAP Data, Full-Byte Mode
Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 !EP !EP D[8] 0 1 1 1 EP EP D[7] 0 1 1 0 EF 0 D[6] D[5] 0 0 1 1 1 1 1 0 0 1 0 0 CCAP Word1[7:0] CCAP Word2[7:0] 0 0 0 0 CS[6] CS[5] D[4] 0 1 1 0 0 0 D[3] 0 1 1 0 1 0 D[2] 0 1 1 0 0 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words UDW padding 0x200 UDW padding 0x200 Checksum
1 1 !CS[8]
0 0 CS[8]
0 0 CS[7]
0 0 CS[4]
0 0 CS[3]
0 0 CS[2]
Rev. B | Page 55 of 100
ADV7183B
GDECEL[15:0] Gemstar Decoding Even Lines, Address 0x48[7:0]; Address 0x49[7:0]
The 16 bits of the GDECEL[15:0] are interpreted as a collection of 16 individual line decode enable signals. Each bit refers to a line of video in an even field. Setting the bit enables the decoder block trying to find Gemstar or closed caption-compatible data on that particular line. Setting the bit to 0 prevents the decoder from trying to retrieve data. See Table 74 and Table 75.
246H 247H
Table 74. NTSC Line Enable Bits and Corresponding Line Numbering
Line[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Line Number (ITU-R BT.470) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 273 (10) 274 (11) 275 (12) 276 (13) 277 (14) 278 (15) 279 (16) 280 (17) 281 (18) 282 (19) 283 (20) 284 (21) 285 (22) 286 (23) 287 (24) 288 (25) Enable Bit GDECOL[0] GDECOL[1] GDECOL[2] GDECOL[3] GDECOL[4] GDECOL[5] GDECOL[6] GDECOL[7] GDECOL[8] GDECOL[9] GDECOL[10] GDECOL[11] GDECOL[12] GDECOL[13] GDECOL[14] GDECOL[15] GDECEL[0] GDECEL[1] GDECEL[2] GDECEL[3] GDECEL[4] GDECEL[5] GDECEL[6] GDECEL[7] GDECEL[8] GDECEL[9] GDECEL[10] GDECEL[11] GDECEL[12] GDECEL[13] GDECEL[14] GDECEL[15] Comment Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar or closed caption Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar or closed caption Gemstar Gemstar Gemstar Gemstar
To retrieve closed caption data services on NTSC (Line 284), GDECEL[11] must be set. To retrieve closed caption data services on PAL (Line 335), GDECEL[14] must be set. The default value of GDECEL[15:0] is 0x0000. This setting instructs the decoder not to attempt to decode Gemstar or CCAP data from any line in the even field.
GDECOL[15:0] Gemstar Decoding Odd Lines, Address 0x4A[7:0]; Address 0x4B[7:0]
The 16 bits of the GDECOL[15:0] form a collection of 16 individual line decode enable signals. See Table 74 and Table 75.
248H 249H
To retrieve closed caption data services on NTSC (Line 21), GDECOL[11] must be set. To retrieve closed caption data services on PAL (Line 22), GDECOL[14] must be set. The default value of GDECOL[15:0] is 0x0000. This setting instructs the decoder not to attempt to decode Gemstar or CCAP data from any line in the odd field.
GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C[0]
The decoded data from Gemstar-compatible transmissions or closed caption is inserted into the horizontal blanking period of the respective line of video. There is a potential problem if the retrieved data bytes have the value 0x00 or 0xFF. In an ITU-R BT.656-compatible data stream, those values are reserved and used only to form a fixed preamble. The GDECAD bit allows the data to be inserted into the horizontal blanking period in two ways: * Insert all data straight into the data stream, even the reserved values of 0x00 and 0xFF, if they occur. This can violate the output data format specification ITU-R BT.1364. Split all data into nibbles and insert the half-bytes over double the number of cycles in a 4-bit format.
*
When GDECAD is 0, the data is split into half-bytes and inserted (default). When GDECAD is 1, the data is output straight in 8-bit format.
Rev. B | Page 56 of 100
ADV7183B
Table 75. PAL Line Enable Bits and Corresponding Line Numbering
Line[3:0] 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 Line Number (ITU-R BT.470) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 321 (8) 322 (9) 323 (10) 324 (11) 325 (12) 326 (13) 327 (14) 328 (15) 329 (16) 330 (17) 331 (18) 332 (19) 333 (20) 334 (21) 335 (22) 336 (23) Enable Bit GDECOL[0] GDECOL[1] GDECOL[2] GDECOL[3] GDECOL[4] GDECOL[5] GDECOL[6] GDECOL[7] GDECOL[8] GDECOL[9] GDECOL[10] GDECOL[11] GDECOL[12] GDECOL[13] GDECOL[14] GDECOL[15] GDECEL[0] GDECEL[1] GDECEL[2] GDECEL[3] GDECEL[4] GDECEL[5] GDECEL[6] GDECEL[7] GDECEL[8] GDECEL[9] GDECEL[10] GDECEL[11] GDECEL[12] GDECEL[13] GDECEL[14] GDECEL[15] Comment Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Closed caption Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Closed caption Not valid
6 4 2
AMPLITUDE (dB)
0 -2 -4 -6 -8 -10
04997-036
04997-038
-12 2.0
2.5
3.0
3.5
4.0
4.5
5.0
FREQUENCY (MHz)
Figure 36. NTSC IF Compensation Filter Responses
6 4 2
AMPLITUDE (dB)
0 -2 -4 -6 -8 3.0
3.5
4.0
4.5
5.0
5.5
6.0
FREQUENCY (MHz)
Figure 37. PAL IF Compensation Filter Responses
See Table 86 for programming details.
25H
IP2 Interrupt System
PC
The ADV7183B has a comprehensive interrupt register set. This map is located in Register Access Page 2. See Table 84 for details of the interrupt register map.
253H
IF Compensation Filter IF FILTSEL[2:0] IF Filter Select Address 0xF8[2:0]
The IF FILTSEL[2:0] register allows the user to compensate for SAW filter characteristics on a composite input as observed on tuner outputs. Figure 36 and Figure 37 show IF filter compensation for NTSC and PAL.
250H 251H
How to access this map is described in Figure 38.
254H
COMMON I2C SPACE ADDRESS 0x00 0x3F
ADDRESS 0x0E BIT 6, 5 = 00b
ADDRESS 0x0E BIT 6, 5 = 01b
The options for this feature are as follows: * * * Bypass mode (default) NTSC--consists of three filter characteristics PAL--consists of three filter characteristics
I2C SPACE REGISTER ACCESS PAGE 1 ADDRESS 0x40 0xFF NORMAL REGISTER SPACE
I2C SPACE REGISTER ACCESS PAGE 2 ADDRESS 0x40 0x4C INTERRUPT REGISTER SPACE
Figure 38. Register Access --Page 1 and Page 2
Rev. B | Page 57 of 100
04997-037
ADV7183B
Interrupt Request Output Operation
When an interrupt event occurs, the interrupt pin INTRQ goes low with a programmable duration given by INTRQ_DUR_SEL[1:0]
INTRQ_OP_SEL[1:0], Interrupt Duration Select Address 0x40 (Interrupt Space)[1:0]
Table 77. INTRQ_OP_SEL
INTRQ_OP_SEL[1:0] 00 (default) 01 10 11 Description Open drain Drive low when active Drive high when active Reserved
INTRQ_DURSEL[1:0], Interrupt Duration Select Address 0x40 (Interrupt Space)[7:6]
Table 76. INTRQ_DUR_SEL
INTRQ_DURSEL[1:0] 00 (default) 01 10 11 Description 3 Xtal periods 15 Xtal periods 63 Xtal periods Active until cleared
Multiple Interrupt Events
If Interrupt Event 1 occurs and then Interrupt Event 2 occurs before the system controller has cleared or masked Interrupt Event 1, the ADV7183B will not generate a second interrupt signal. The system controller should check all unmasked interrupt status bits, as more than one can be active.
When the active until cleared interrupt duration is selected and the event that caused the interrupt is no longer in force, the interrupt persists until it is masked or cleared. For example, if the ADV7183B loses lock, an interrupt is generated and INTRQ pin goes low. If the ADV7183B returns to the locked state, INTRQ continues to drive low until the SD_LOCK bit is either masked or cleared.
Interrupt Drive Level
Macrovision Interrupt Selection Bits
The user can select between pseudo sync pulse and color stripe detection as shown in this section.
MV_INTRQ_SEL[1:0], Macrovision Interrupt Selection Bits Address 0x40 (Interrupt Space)[5:4]
Table 78. MV_INTRQ_SEL
MV_INTRQ_SEL[1:0] 00 01 (default) 10 11 Description Reserved Pseudo sync only Color stripe only Either pseudo sync or color stripe
The ADV7183B resets with open drain enabled and all interrupts masked off. Therefore, INTRQ is in a high impedance state after reset. 01 or 10 has to be written to INTRQ_OP_SEL[1:0] for a logic level to be driven out from the INTRQ pin. It is also possible to write to a register in the ADV7183B that manually asserts the INTRQ pin. This bit is MPU_STIM_INTRQ.
Additional information relating to the interrupt system is detailed in Table 84.
25H
Rev. B | Page 58 of 100
ADV7183B PIXEL PORT CONFIGURATION
The ADV7183B has a very flexible pixel port that can be configured in a variety of formats to accommodate downstream ICs. Table 79 and Table 80 summarize the various functions that the ADV7183B's pins can have in different modes of operation.
256H 257H
SWPC Swap Pixel Cr/Cb, Address 0x27[7]
This bit allows Cr and Cb samples to be swapped. When SWPC is 0 (default), no swapping is allowed. When SWPC is 1, the Cr and Cb values can be swapped.
The ordering of components (for example, Cr versus Cb, CHA/B/C) can be changed. Refer to the section. Table 79 indicates the default positions for the Cr/Cb components.
258H
PAD_SEL[2:0], Address 0x8F[6:4]
This I2C write allows the user to select between the LLC1 (nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz). The LLC2 signal is useful for LLC2-compatible wide bus (16-bit) output modes. See the OF_SEL[3:0] Output Format Selection, Address 0x03[5:2] section for additional information. The LLC2 signal and data on the data bus are synchronized. By default, the rising edge of LLC1/LLC2 is aligned with the Y data; the falling edge occurs when the data bus holds C data. The polarity of the clock, and therefore the Y/C assignments to the clock edges, can be altered by using the Polarity LLC pin.
261H
OF_SEL[3:0] Output Format Selection, Address 0x03[5:2]
The modes in which the ADV7183B pixel port can be onfigured are under the control of OF_SEL[3:0]. See Table 80 for details.
259H
The default LLC frequency output on the LLC1 pin is approximately 27 MHz. For modes that operate with a nominal data rate of 13.5 MHz (0001, 0010), the clock frequency on the LLC1 pin stays at the higher rate of 27 MHz. For information on outputting the nominal 13.5 MHz clock on the LLC1 pin, see the PAD_SEL[2:0], Address 0x8F[6:4] section.
260H
When LLC_PAD_SEL[2:0] is 000 (default), the output is nominally 27 MHz LLC on the LLC1 pin. When LLC_PAD_SEL[2:0] is 101, the output is nominally 13.5 MHz LLC on the LLC1 pin.
Table 79. P15 to P0 Output/Input Pin Mapping
Format, and Mode Video Out, 8-Bit, 4:2:2 Video Out, 16-Bit, 4:2:2 15 14 13 12 11 YCrCb[7:0] OUT Y[7:0] OUT Data Port Pins P[15:0] 10 9 8 7 6 5 4 3 2 1 0
CrCb[7:0] OUT
Table 80. Standard Definition Pixel Port Modes
P[15: 0] OF_SEL[3:0] 0010 0011 (default) 0110-1111 Format 16-bit @ LLC2 4:2:2 8-bit @ LLC1 4:2:2 (default) Reserved P[15:8] Y[7:0] YCrCb[7:0] (default) P[7: 0] CrCb[7:0] Three-state Reserved. Do not use.
Rev. B | Page 59 of 100
ADV7183B MPU PORT DESCRIPTION
The ADV7183B supports a 2-wire (I2C-compatible) serial interface. Two inputs, serial data (SDA) and serial clock (SCLK), carry information between the ADV7183B and the system I2C master controller. Each slave device is recognized by a unique address. The ADV7183B's I2C port allows the user to set up and configure the decoder and to read back captured VBI data. The ADV7183B has two possible slave addresses for both read and write operations, depending on the logic level on the ALSB pin. These four unique addresses are shown in Table 81. The ADV7183B's ALSB pin controls Bit 1 of the slave address. By altering the ALSB, it is possible to control two ADV7183Bs in an application without having a conflict with the same slave address. The LSB (Bit 0) sets either a read or write operation. Logic 1 corresponds to a read operation; Logic 0 corresponds to a write operation. Table 81. I2C Address for the ADV7183B
26H
address. The R/W bit determines the direction of the data. Logic 0 on the LSB of the first byte means the master writes information to the peripheral. Logic 1 on the LSB of the first byte means the master reads information from the peripheral. The ADV7183B acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses and the R/W bit. The ADV7183B has 249 subaddresses to enable access to the internal registers. It therefore interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses auto-increment, which allows data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without updating all the registers. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCLK high period, the user should only issue one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADV7183B does not issue an acknowledge and returns to the idle condition. If the user exceeds the highest subaddress in auto-increment mode, the following occurs: * In read mode, the highest subaddress register contents continue to be output until the master device issues a no-acknowledge. This indicates the end of a read. A no acknowledge condition is where the SDA line is not pulled low on the ninth pulse. In write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the ADV7183B, and the part returns to the idle condition.
ALSB 0 0 1 1
R/W 0 1 0 1
Slave Address 0x40 0x41 0x42 0x43
To control the device on the bus, a specific protocol must be followed. First, the master initiates a data transfer by establishing a start condition, which is defined by a high-to-low transition on SDA while SCLK remains high. This indicates that an address/data stream will follow. All peripherals respond to the start condition and shift the next eight bits (7-bit address + R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse; this is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCLK lines, waiting for the start condition and the correct transmitted
SDATA
*
START ADDR R/W ACK SUBADDRESS ACK
DATA
ACK
STOP
Figure 39. Bus Data Transfer
WRITE SEQUENCE S SLAVE ADDR A(S) LSB = 0 READ SEQUENCE SUB ADDR A(S) DATA A(S) LSB = 1 DATA A(S) P
S SLAVE ADDR A(S) S = START BIT P = STOP BIT
04997-039
SCLOCK
S
1-7
8
9
1-7
8
9
1-7
8
9
P
SUB ADDR
A(S) S
SLAVE ADDR A(S)
DATA
A(M)
DATA
A(M) P
04997-040
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO-ACKNOWLEDGE BY SLAVE A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 40. Read and Write Sequence
Rev. B | Page 60 of 100
ADV7183B
REGISTER ACCESSES
The MPU can write to or read from most of the ADV7183B's registers, except the registers that are read only or write only. The subaddress register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the subaddress register. Next, a read/write operation is performed from/to the target address, which then increments to the next address until a stop command on the bus is performed.
I2C SEQUENCER
An I2C sequencer is used when a parameter exceeds eight bits and is, therefore, distributed over two or more I2C registers, such as HSB[11:0]. When such a parameter is changed using two or more I2C write operations, the parameter can hold an invalid value for the time between the first I2C completion and the last I2C completion. This means, the top bits of the parameter can already hold the new value while the remaining bits of the parameter still hold the previous value. To avoid this problem, the I2C sequencer holds the already updated bits of the parameter in local memory; all bits of the parameter are updated together once the last register write operation has completed. The correct operation of the I2C sequencer relies on the following: * All I2C registers for the target parameter must be written to in order of ascending addresses. For example, for HSB[10:0], write to Address 0x34 first, followed by 0x35. No other I2C can take place between the two (or more) I2C writes for the sequence. For example, for HSB[10:0], write to Address 0x34 first, immediately followed by 0x35.
REGISTER PROGRAMMING
This section describes the configuration of each register. The communications register is an 8-bit, write only register. After the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The subaddress register determines to/from which register the operation takes place. Table 82 lists the various operations under the control of the subaddress register for the control port.
263H
Register Select (SR7 to SR0)
These bits are set up to point to the required starting address.
*
Rev. B | Page 61 of 100
ADV7183B IP2PC REGISTER MAPS
Table 82. Common and Normal (Page 1) Register Map Details
Register Name Input Control Video Selection Reserved Output Control Extended Output Control Reserved Reserved Autodetect Enable Contrast Reserved Brightness Hue Default Value Y Default Value C ADI Control Power Management Status 1 Ident Status 2 Status 3 Analog Clamp Control Digital Clamp Control 1 Reserved Shaping Filter Control Shaping Filter Control 2 Comb Filter Control Reserved ADI Control 2 Reserved Pixel Delay Control Reserved Misc Gain Control AGC Mode Control Chroma Gain Control 1 Chroma Gain Control 2 Luma Gain Control 1 Luma Gain Control 2 Vsync Field Control 1 Vsync Field Control 2 Vsync Field Control 3 Hsync Position Control 1 Hsync Position Control 2 Hsync Position Control 3 Polarity NTSC Comb Control PAL Comb Control ADC Control Reserved Manual Window Control Reset Value 0000 0000 1100 1000 0000 0100 0000 1100 01xx 0101 0000 0000 0000 0010 0111 1111 1000 0000 1000 0000 0000 0000 0000 0000 0011 0110 0111 1100 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0001 0010 0100 xxxx xxxx xxxx 0000 0001 1001 0011 1111 0001 xxxx xxxx 0000 0xxx xxxx xxxx 0101 1000 xxxx xxxx 1110 0001 1010 1110 1111 0100 0000 0000 1111 xxxx xxxx xxxx 0001 0010 0100 0001 1000 0100 0000 0000 0000 0010 0000 0000 0000 0001 1000 0000 1100 0000 0001 0000 xxxx xxxx 0100 0011 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw r r r r rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 to 28 29 30 to 38 39 40 to 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 to 60 61 Subaddress Hex 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A to 0x1C 0x1D 0x1E to 0x26 0x27 0x28 to 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B to 0x3C 0x3D
Rev. B | Page 62 of 100
ADV7183B
Register Name Reserved Resample Control Reserved Gemstar Ctrl 1 Gemstar Ctrl 2 Gemstar Ctrl 3 Gemstar Ctrl 4 GemStar Ctrl 5 CTI DNR Ctrl 1 CTI DNR Ctrl 2 Reserved CTI DNR Ctrl 4 Lock Count Reserved Free-Run Line Length 1 Reserved VBI Info WSS 1 WSS 2 EDTV 1 EDTV 2 EDTV 3 CGMS 1 CGMS 2 CGMS 3 CCAP1 CCAP2 Letterbox 1 Letterbox 2 Letterbox 3 Reserved CRC Enable Reserved ADC Switch 1 ADC Switch 2 Reserved Letterbox Control 1 Letterbox Control 2 Reserved Reserved Reserved SD Offset Cb SD Offset Cr SD Saturation Cb SD Saturation Cr NTSC V Bit Begin NTSC V Bit End NTSC F Bit Toggle PAL V Bit Begin PAL V Bit End PAL F Bit Toggle Reserved Reset Value xxxx xxxx 0100 0001 xxxx xxxx 00000000 0000 0000 0000 0000 0000 0000 xxxx xxx0 1110 1111 0000 1000 xxxx xxxx 0000 1000 0010 0100 xxxx xxxx 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0001 1100 xxxx xxxx xxxx xxxx 0xxx xxxx xxxx xxxx 1010 1100 0100 1100 0000 0000 0000 0000 0001 0100 1000 0000 1000 0000 1000 0000 1000 0000 0010 0101 0000 0100 0110 0011 0110 0101 0001 0100 0110 0011 xxxx xxxx rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw w w r r r r r r r r r r r r r r rw w rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Dec 62 to 64 65 66 to 71 72 73 74 75 76 77 78 79 80 81 82 to 142 143 144 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 to 177 178 179 to 194 195 196 197 to 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 to 243 Subaddress Hex 0x3E to 0x40 0x41 0x42 to 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 to 0x8E 0x8F 0x90 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E to 0xB1 0xB2 0xB2 to 0xC2 0xC3 0xC4 0xC5 to 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB to 0xF3
Rev. B | Page 63 of 100
ADV7183B
Register Name Drive Strength Reserved IF Comp Control VS Mode Control Reset Value xx01 0101 xxxx xxxx 0000 0000 0000 0000 rw rw rw rw rw Dec 244 245 to 247 248 249 Subaddress Hex 0xF4 0xF5 to 0xF7 0xF8 0xF9
Table 83. Common and Normal (Page 1) Register Map Bit Names
Register Name Input Control Video Selection Reserved Output Control Extended Output Control Reserved Reserved Autodetect Enable Contrast Reserved Brightness Hue Default Value Y Default Value C ADI Control Power Management Status 1 Ident Status 2 Status 3 Analog Clamp Control Digital Clamp Control 1 Reserved Shaping Filter Control Shaping Filter Control 2 Comb Filter Control Reserved ADI Control 2 Reserved Pixel Delay Control Reserved Misc Gain Control AGC Mode Control Chroma Gain Control 1 Chroma Gain Control 2 Luma Gain Control 1 Luma Gain Control 2 Vsync Field Control 1 Vsync Field Control 2 Vsync Field Control 3 Hsync Position Control 1 Hsync Position Control 2 Hsync Position Control 3 Polarity NTSC Comb Control PAL Comb Control ADC Control Reserved Manual Window Control Bit 7 VID_SEL.3 Bit 6 VID_SEL.2 ENHSPLL TOD Bit 5 VID_SEL.1 BETACAM OF_SEL.3 Bit 4 VID_SEL.0 Bit 3 INSEL.3 ENVSPROC OF_SEL.1 TIM_OE Bit 2 INSEL.2 Bit 1 INSEL.1 Bit 0 INSEL.0
VBI_EN BT656-4
OF_SEL.2
OF_SEL.0 BL_C_VBI
EN_SFL_PI
SD_DUP_AV RANGE
AD_SEC525_EN
AD_SECAM_EN
CON.7 BRI.7 HUE.7 DEF_Y.5 DEF_C.7 RES COL_KILL IDENT.7 PAL SW LOCK
CON.6 BRI.6 HUE.6 DEF_Y.4 DEF_C.6
AD_N443_EN CON.5 BRI.5 HUE.5 DEF_Y.3 DEF_C.5 PWRDN AD_RESULT.1 IDENT.5 FSC NSTD STD FLD LEN DCT.0 CSFM.0
AD_P60_EN CON.4 BRI.4 HUE.4 DEF_Y.2 DEF_C.4
SUB_USR_EN.0
AD_PALN_EN CON.3 BRI.3 HUE.3 DEF_Y.1 DEF_C.3
AD_PALM_EN CON.2 BRI.2 HUE.2 DEF_Y.0 DEF_C.2 PDBP FSC_LOCK IDENT.2 MV PS DET SD_OP_50HZ
AD_NTSC_EN CON.1 BRI.1 HUE.1 DEF_VAL_ AUTO_EN DEF_C.1
AD_PAL_EN CON.0 BRI.0 HUE.0 DEF_VAL_EN DEF_C.0
AD_RESULT.2 IDENT.6 INTERLACE DCT.1
AD_RESULT.0 IDENT.4 LL NSTD
FREE_RUN_ACT
FOLLOW_PW IDENT.3 MV AGC DET
LOST_LOCK IDENT.1 MVCS T3 GEMD
IN_LOCK IDENT.0 MVCS DET INST_HLOCK
CCLEN
CSFM.2 WYSFMOVR
CSFM.1
YSFM.4 WYSFM.4
YSFM.3 WYSFM.3 NSFSEL.1
YSFM.2 WYSFM.2 NSFSEL.0
YSFM.1 WYSFM.1 PSFSEL.1
YSFM.0 WYSFM.0 PSFSEL.0
TRI_LLC
EN28XTAL
VS_JIT_ COMP_EN CTA.2 CTA.1 CTA.0 LTA.1 LTA.0 PW_UPD CAGC.0 CMG.8 CMG.0 LMG.8 LMG.0
SWPC
AUTO_PDC_EN
CAGT.1 CMG.7 LAGT.1 LMG.7 VSBHO VSEHO HSB.7 HSE.7 PHS CTAPSN.1 CTAPSP.1
CKE LAGC.2 CAGT.0 CMG.6 LGAT.0 LMG.6 VSBHE VSEHE HSB.10 HSB.6 HSE.6 CTAPSN.0 CTAPSP.0
LAGC.1 CMG.5 LMG.5
LAGC.0 CMG.4 LMG.4 NEWAVMODE CMG.11 CMG.3 LMG.11 LMG.3 HVSTIM CMG.10 CMG.2 LMG.10 LMG.2
CAGC.1 CMG.9 CMG.1 LMG.9 LMG.1
HSB.9 HSB.5 HSE.5 PVS CCMN.2 CCMP.2
HSB.8 HSB.4 HSE.4 CCMN.1 CCMP.1
HSB.3 HSE.3 PF CCMN.0 CCMP.0
PWRDN_AD C_0
HSE.10 HSB.2 HSE.2 YCMN.2 YCMP.2
PWRDN_AD C_ 1
HSE.9 HSB.1 HSE.1 YCMN.1 YCMP.1
PWRDN_ADC_2
HSE.8 HSB.0 HSE.0 PCLK YCMN.0 YCMP.0
CKILLTHR.2
CKILLTHR.1
CKILLTHR.0
Rev. B | Page 64 of 100
ADV7183B
Register Name Reserved Resample Control Reserved Gemstar Ctrl 1 Gemstar Ctrl 2 Gemstar Ctrl 3 Gemstar Ctrl 4 Gemstar Ctrl 5 CTI DNR Ctrl 1 CTI DNR Ctrl 2 Reserved CTI DNR Ctrl 4 Lock Count Reserved Free-run Line Length 1 Reserved VBI Info WSS 1 WSS 2 EDTV 1 EDTV 2 EDTV 3 CGMS 1 CGMS 2 CGMS 3 CCAP1 CCAP2 Letterbox 1 Letterbox 2 Letterbox 3 Reserved CRC Enable Reserved ADC Switch 1 ADC Switch 2 Reserved Letterbox Control 1 Letterbox Control 2 Reserved Reserved Reserved SD Offset Cb SD Offset Cr SD Saturation Cb SD Saturation Cr NTSC V Bit Begin NTSC V Bit End NTSC F Bit Toggle PAL V Bit Begin PAL V Bit End PAL F Bit Toggle Reserved Drive Strength Reserved IF Comp Control VS Mode Control Bit 7 Bit 6 SFL_INV GDECEL.15 GDECEL.7 GDECOL.15 GDECOL.7 GDECEL.14 GDECEL.6 GDECOL.14 GDECOL.6 GDECEL.13 GDECEL.5 GDECOL.13 GDECOL.5 DNR_EN CTI_C_TH.5 DNR_TH.5 COL.2
LLC_PAD_SEL.1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GDECEL.12 GDECEL.4 GDECOL.12 GDECOL.4
GDECEL.11 GDECEL.3 GDECOL.11 GDECOL.3 CTI_AB.1 CTI_C_TH.3 DNR_TH.3 COL.0
GDECEL.10 GDECEL.2 GDECOL.10 GDECOL.2 CTI_AB.0 CTI_C_TH.2 DNR_TH.2 CIL.2
GDECEL.9 GDECEL.1 GDECOL.9 GDECOL.1 CTI_AB_EN CTI_C_TH.1 DNR_TH.1 CIL.1
CTI_C_TH.7 DNR_TH.7 FSCLE
CTI_C_TH.6 DNR_TH.6 SRLS
LLC_PAD_SEL.2
CTI_C_TH.4 DNR_TH.4 COL.1
LLC_PAD_SEL.0
GDECEL.8 GDECEL.0 GDECOL.8 GDECOL.0 GDECAD CTI_EN CTI_C_TH.0 DNR_TH.0 CIL.0
WSS1.7 WSS2.7 EDTV1.7 EDTV2.7 EDTV3.7 CGMS1.7 CGMS2.7 CGMS3.7 CCAP1.7 CCAP2.7 LB_LCT.7 LB_LCM.7 LB_LCB.7
WSS1.6 WSS2.6 EDTV1.6 EDTV2.6 EDTV3.6 CGMS1.6 CGMS2.6 CGMS3.6 CCAP1.6 CCAP2.6 LB_LCT.6 LB_LCM.6 LB_LCB.6
WSS1.5 WSS2.5 EDTV1.5 EDTV2.5 EDTV3.5 CGMS1.5 CGMS2.5 CGMS3.5 CCAP1.5 CCAP2.5 LB_LCT.5 LB_LCM.5 LB_LCB.5
WSS1.4 WSS2.4 EDTV1.4 EDTV2.4 EDTV3.4 CGMS1.4 CGMS2.4 CGMS3.4 CCAP1.4 CCAP2.4 LB_LCT.4 LB_LCM.4 LB_LCB.4
CGMSD WSS1.3 WSS2.3 EDTV1.3 EDTV2.3 EDTV3.3 CGMS1.3 CGMS2.3 CGMS3.3 CCAP1.3 CCAP2.3 LB_LCT.3 LB_LCM.3 LB_LCB.3
EDTVD WSS1.2 WSS2.2 EDTV1.2 EDTV2.2 EDTV3.2 CGMS1.2 CGMS2.2 CGMS3.2 CCAP1.2 CCAP2.2 LB_LCT.2 LB_LCM.2 LB_LCB.2 CRC_ENABLE
CCAPD WSS1.1 WSS2.1 EDTV1.1 EDTV2.1 EDTV3.1 CGMS1.1 CGMS2.1 CGMS3.1 CCAP1.1 CCAP2.1 LB_LCT.1 LB_LCM.1 LB_LCB.1
WSSD WSS1.0 WSS2.0 EDTV1.0 EDTV2.0 EDTV3.0 CGMS1.0 CGMS2.0 CGMS3.0 CCAP1.0 CCAP2.0 LB_LCT.0 LB_LCM.0 LB_LCB.0
ADC1_SW.3 ADC_SW_M AN
ADC1_SW.2
ADC1_SW.1
ADC1_SW.0
ADC0_SW.3 ADC2_SW.3
ADC0_SW.2 ADC2_SW.2
ADC0_SW.1 ADC2_SW.1
ADC0_SW.0 ADC2_SW.0
LB_SL.3
LB_SL.2
LB_SL.1
LB_TH.4 LB_SL.0
LB_TH.3 LB_EL.3
LB_TH.2 LB_EL.2
LB_TH.1 LB_EL.1
LB_TH.0 LB_EL.0
SD_OFF_CB.7 SD_OFF_CR.7 SD_SAT_CB.7 SD_SAT_CR.7 NVBEGDEL O NVENDDEL O NFTOGDEL O PVBEGDEL O PVENDDEL O PFTOGDEL O
SD_OFF_CB.6 SD_OFF_CR.6 SD_SAT_CB.6 SD_SAT_CR.6 NVBEGDEL E NVENDDEL E NFTOGDEL E PVBEGDEL E PVENDDEL E PFTOGDEL E
SD_OFF_CB.5 SD_OFF_CR.5 SD_SAT_CB.5 SD_SAT_CR.5 NVBEGSIGN NVENDSIGN NFTOGSIGN PVBEGSIGN PVENDSIGN PFTOGSIGN DR_STR.1
SD_OFF_CB.4 SD_OFF_CR.4 SD_SAT_CB.4 SD_SAT_CR.4 NVBEG.4 NVEND.4 NFTOG.4 PVBEG.4 PVEND.4 PFTOG.4 DR_STR.0
SD_OFF_CB.3 SD_OFF_CR.3 SD_SAT_CB.3 SD_SAT_CR.3 NVBEG.3 NVEND.3 NFTOG.3 PVBEG.3 PVEND.3 PFTOG.3 DR_STR_C.1
SD_OFF_CB.2 SD_OFF_CR.2 SD_SAT_CB.2 SD_SAT_CR.2 NVBEG.2 NVEND.2 NFTOG.2 PVBEG.2 PVEND.2 PFTOG.2 DR_STR_C.0 IFFILTSEL.2 VS_COAST_ MODE.0
SD_OFF_CB.1 SD_OFF_CR .1 SD_SAT_CB.1 SD_SAT_CR.1 NVBEG.1 NVEND.1 NFTOG.1 PVBEG.1 PVEND.1 PFTOG.1 DR_STR_S.1 IFFILTSEL.1 EXTEND_VS_ MIN_FREQ
SD_OFF_CB.0 SD_OFF_CR.0 SD_SAT_CB.0 SD_SAT_CR.0 NVBEG.0 NVEND.0 NFTOG.0 PVBEG.0 PVEND.0 PFTOG.0 DR_STR_S.0 IFFILTSEL.0 EXTEND_VS_ MAX_FREQ
VS_COAST_ MODE.1
Rev. B | Page 65 of 100
ADV7183B
IP2 REGISTER MAP DETAILS
PC
The following registers are located in the Common I2C Map and Register Access Page 2.
Table 84. Interrupt (Page 2) Register Map Bit Names 1
15F
Register Name Interrupt Config 0 Reserved Interrupt Status 1 Interrupt Clear 1 Interrupt Maskb 1 Reserved Interrupt Status 2 Interrupt Clear 2 Interrupt Maskb 2 Raw Status 3 Interrupt Status 3 Interrupt Clear 3 Interrupt Maskb 3
1
Reset Value 0001 x000
Subaddress rw rw Dec 64 65 66 67 68 69 70 71 72 Hex 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 Bit 7 INTRQ_DUR _SEL.1 Bit 6 INTRQ_DUR _SEL.0 MV_PS_CS_ Q MV_PS_CS_ CLR MV_PS_CS_ MSKB MPU_STIM_ INTRQ_Q MPU_STIM_ INTRQ_CLR MPU_STIM_ INTRQ_ MSKB SCM_LOCK PAL_SW_LK _CHNG_Q PAL_SW_LK _CHNG_CLR PAL_SW_LK _CHNG_ MSKB SCM_LOCK_ CHNG_Q SCM_LOCK_ CHNG_CLR SCM_LOCK_ CHNG_ MSKB SD_AD_ CHNG_Q SD_AD_CH NG_CLR SD_AD_ CHNG_ MSKB Bit 5 MV_INTRQ_ SEL.1 SD_FR_CHN G_Q SD_FR_CHN G_CLR SD_FR_CHN G_MSKB WSS_ CHNGD_Q WSS_ CHNGD_CLR WSS_ CHNGD_ MSKB CGMS_ CHNGD_Q CGMS_CHN GD_CLR CGMS_ CHNGD_ MSKB SD_H_LOCK SD_H_LOCK _CHNG_Q SD_H_LOCK _CHNG_CLR SD_H_LOCK _CHNG_ MSKB Bit 4 MV_INTRQ_ SEL.0 Bit 3 Bit 2 MPU_STIM_ INTRQ Bit 1 INTRQ_OP_ SEL.1 SD_UNLOCK _Q SD_UNLOCK _CLR SD_UNLOCK _MSKB GEMD_Q GEMD_CLR GEMD_ MSKB SD_V_LOCK SD_V_LOCK _CHNG_Q SD_V_LOCK _CHNG_CLR SD_V_LOCK _CHNG_ MSKB Bit 0 INTRQ_OP_ SEL.0 SD_LOCK_Q SD_LOCK_ CLR SD_LOCK_ MSKB CCAPD_Q CCAPD_CLR CCAPD_ MSKB SD_OP_ 50HZ SD_OP_ CHNG_Q SD_OP_ CHNG_CLR SD_OP_ CHNG_ MSKB
r x000 0000 x000 0000 w rw
r 0xxx 0000 0xxx 0000 w rw
r r xx00 0000 xx00 0000 w rw
73 74 75 76
0x49 0x4A 0x4B 0x4C
To access the Interrupt Register Map, the Register Access page[1:0] in Register Address 0x0E must be programmed to 01b.
Rev. B | Page 66 of 100
ADV7183B
Table 85. Interrupt Register Map Details
Bit Subaddress 0x40 Register Interrupt Config 1 Register Access Page 2 Bit Description INTRQ_OP_SEL[1:0]. Interrupt Drive Level Select 7 6 5 4 3 2 1 0 0 1 1 0 0 1 0 1 Comments Open drain. Drive low when active. Drive high when active. Reserved. Manual interrupt mode disabled. Manual interrupt mode enabled. Not used. Reserved. Pseudo sync only. Color stripe only. Pseudo sync or color stripe. 3 Xtal periods. 15 Xtal periods. 63 Xtal periods. Active until cleared. No change. SD input has caused the decoder to go from an un-locked state to a locked state. No change. SD input has caused the decoder to go from a locked state to an unlocked state. Notes
MPU_STIM_INTRQ[1:0]. Manual Interrupt Set Mode Reserved MV_INTRQ_SEL[1:0]. Macrovision Interrupt Select x 0 0 1 1 0 0 1 1 x 0 1 0 1 x 0 1 0 1
0 1
INTRQ_DUR_SEL[1:0]. Interrupt Duration Select
0x41 0x42
Reserved Interrupt Status 1 Read Only
x
x
x
x
x
SD_LOCK_Q
x 0 1
SD_UNLOCK_Q Register Access Page 2 Reserved Reserved Reserved SD_FR_CHNG_Q x x x 0 1 0 1
0 1
These bits can be cleared or masked in Registers 0x43 and 0x44, respectively.
MV_PS_CS_Q
No change. Denotes a change in the free-run status. No change. Pseudo sync/color striping detected. See
MV_INTRQ_SEL[1:0], Macrovision Interrupt Selection Bits Address 0x40 (Interrupt Space)[5:4] for selection.
264H
0x43
Interrupt Clear 1 Write Only Register Access Page 2
Reserved SD_LOCK_CLR SD_UNLOCK_CLR Reserved Reserved Reserved SD_FR_CHNG_CLR MV_PS_CS_CLR Reserved
x 0 1 0 1 0 0 0 0 1 0 1 x Do not clear. Clears SD_LOCK_Q bit. Do not clear. Clears SD_UNLOCK_Q bit. Not used. Not used. Not used. Do not clear. Clears SD_FR_CHNG_Q bit. Do not clear. Clears MV_PS_CS_Q bit. Not used.
Rev. B | Page 67 of 100
ADV7183B
Bit Subaddress 0x44 Register Interrupt Mask 1 Read/Write Register Register Access Page 2 Bit Description SD_LOCK_MSKB SD_UNLOCK_MSKB Reserved Reserved Reserved SD_FR_CHNG_MSKB MV_PS_CS_MSKB Reserved 0x45 0x46 Reserved Interrupt Status 2 Read Only Register Register Access Page 2 CCAPD_Q x x 0 1 x x x x x x x 0 1 GEMD_Q 0 1 CGMS_CHNGD_Q 0 1 WSS_CHNGD_Q 0 1 Reserved Reserved Reserved MPU_STIM_INTRQ_Q 0x47 Interrupt Clear 2 Write Only Register Access Page 2 CGMS_CHNGD_CLR WSS_CHNGD_CLR Reserved Reserved Reserved MPU_STIM_INTRQ_CLR x x x 0 1 0 1 0 1 CCAPD_CLR GEMD_CLR 0 1 x x x 0 1 0 1 0 0 0 0 1 7 6 5 4 3 2 1 0 0 1 Comments Masks SD_LOCK_Q bit. Unmasks SD_LOCK_Q bit. Masks SD_UNLOCK_Q bit. Unmasks SD_UNLOCK_Q bit Not used. Not used. Not used. Masks SD_FR_CHNG_Q bit. Unmasks SD_FR_CHNG_Q bit. Masks MV_PS_CS_Q bit. Unmasks MV_PS_CS_Q bit. Not used. Closed captioning not detected in the input video signal Closed captioning data detected in the video input signal. Gemstar data not detected in the input video signal. Gemstar data detected in the input video signal. No change detected in CGMS data in the input video signal. A change is detected in the CGMS data in the input video signal. No change detected in WSS data in the input video signal. A change is detected in the WSS data in the input video signal. Not used. Not used. Not used. Manual interrupt not set. Manual interrupt set. Do not clear. Clears CCAPD_Q bit. Do not clear. Clears GEMD_Q bit. Do not clear. Clears CGMS_CHNGD_Q bit. Do not clear. Clears WSS_CHNGD_Q bit. Not used. Not used. Not used. Do not clear. Clears MPU_STIM_INTRQ_Q bit. Notes
0 1
These bits can be cleared or masked by Registers 0x47 and 0x48, respectively.
Rev. B | Page 68 of 100
ADV7183B
Bit Subaddress 0x48 Register Interrupt Mask 2 Read/Write Register Access Page 2 CGMS_CHNGD_MSKB WSS_CHNGD_MSKB Reserved Reserved Reserved MPU_STIM_INTRQ_MSKB 0 0 0 0 1 0 1 0 1 Register Access Page 2 SD_H_LOCK 0 1 Reserved SCM_LOCK SECAM Lock Reserved Reserved Reserved SD_OP_CHNG_Q SD 60/50 Hz frame rate at input SD_V_LOCK_CHNG_Q x x x 0 1 0 1 SD_H_LOCK_CHNG_Q 0 1 SD_AD_CHNG_Q SD autodetect changed x x 0 1 0 1 0 1 Bit Description CCAPD_MSKB GEMD_MSKB 7 6 5 4 3 2 1 0 0 1 Comments Masks CCAPD_Q bit. Unmasks CCAPD_Q bit. Masks GEMD_Q bit. Unmasks GEMD_Q bit. Masks CGMS_CHNGD_Q bit. Unmasks CGMS_CHNGD_Q bit. Masks WSS_CHNGD_Q bit.. Unmasks WSS_CHNGD_Q bit. Not used. Not used. Not used. Masks MPU_STIM_INTRQ_Q bit. Unmasks MPU_STIM_INTRQ_Q bit. SD 60 Hz signal output. SD 50 Hz signal output. SD vertical sync lock not established. SD vertical sync lock established. SD horizontal sync lock not established. SD horizontal sync lock established. Not used. SECAM lock not established. SECAM lock established. Not used. Not used. Not used. No change in SD signal standard detected at the input. A change in SD signal standard is detected at the input. No change in SD vertical sync lock status. SD vertical sync lock status has changed. No change in SD horizontal sync lock status. SD horizontal sync lock status has changed. No change in AD_RESULT[2:0] bits in Status Register 1. AD_RESULT[2:0] bits in Status Register 1 have changed. No change in SECAM lock status. SECAM lock status has changed. No change in PAL swinging burst lock status. PAL swinging burst lock status has changed. Not used. Not used. Notes
0 1
0x49
Raw Status 3 Read Only Register
SD_OP_50Hz SD 60/50Hz frame rate at output SD_V_LOCK
These bits cannot be cleared or masked. Register 0x4A is used for this purpose.
0x4A
Interrupt Status 3 Read Only Register Register Access Page 2
These bits can be cleared and masked by Registers 0x4B and 0x4C, respectively.
SCM_LOCK_CHNG_Q SECAM Lock PAL_SW_LK_CHNG_Q x
0 1
Reserved Reserved
x x
Rev. B | Page 69 of 100
ADV7183B
Bit Subaddress 0x4B Register Interrupt Clear 3 Write Only Register Register Access Page 2 Bit Description SD_OP_CHNG_CLR SD_V_LOCK_CHNG_CLR SD_H_LOCK_CHNG_CLR SD_AD_CHNG_CLR SCM_LOCK_CHNG_CLR PAL_SW_LK_CHNG_CLR Reserved Reserved SD_OP_CHNG_MSKB SD_V_LOCK_CHNG_ MSKB Read/Write Register Register Access Page 2 SD_H_LOCK_CHNG_ MSKB 0 1 0 1 0 1 0 1 x x x x 0 1 0 1 0 1 0 1 0 1 0 1 7 6 5 4 3 2 1 0 0 1 Comments Do not clear. Clears SD_OP_CHNG_Q bit. Do not clear. Clears SD_V_LOCK_CHNG_Q bit. Do not clear. Clears SD_H_LOCK_CHNG_Q bit. Do not clear. Clears SD_AD_CHNG_Q bit. Do not clear. Clears SCM_LOCK_CHNG_Q bit. Do not clear. Clears PAL_SW_LK_CHNG_Q bit. Not used. Not used. Masks SD_OP_CHNG_Q bit. Unmasks SD_OP_CHNG_Q bit. Masks SD_V_LOCK_CHNG_Q bit. Unmasks SD_V_LOCK_CHNG_Q bit. Masks SD_H_LOCK_CHNG_Q bit. Unmasks SD_H_LOCK_CHNG_Q bit. Masks SD_AD_CHNG_Q bit. Unmasks SD_AD_CHNG_Q bit. Masks SCM_LOCK_CHNG_Q bit Unmasks SCM_LOCK_CHNG_Q bit. Masks PAL_SW_LK_CHNG_Q bit. Unmasks PAL_SW_LK_CHNG_Q bit. Not used. Not used. Notes
0 1
0x4C
Interrupt Mask 2
SD_AD_CHNG_ MSKB SCM_LOCK_CHNG_ MSKB
PAL_SW_LK_CHNG_ MSKB
Reserved Reserved
Rev. B | Page 70 of 100
ADV7183B
The following registers are located in the Common I2C Map and Register Access Page 1.
Table 86. Interrupt Register Map Details
Subaddress 0x00 Register Input Control Bit Description INSEL[3:0]. The INSEL bits allow the user to select an input channel as well as the input format. 76 5 Bits 43 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID_SEL[3:0]. The VID_SEL bits allow the user to select the input video standard. 00 0 0 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Comments CVBS in on AIN1. CVBS in on AIN2. CVBS in on AIN3. CVBS in on AIN4. CVBS in on AIN5. CVBS in on AIN6. Y on AIN1, C on AIN4. Y on AIN2, C on AIN5. Y on AIN3, C on AIN6. Y on AIN1, Pr on AIN4, Pb on AIN5. Y on AIN2, Pr on AIN3, Pb on AIN6. CVBS in on AIN7. CVBS in on AIN8. CVBS in on AIN9. CVBS in on AIN10. CVBS in on AIN11. Auto-detect PAL (B/G/H/I/D), NTSC (without pedestal), SECAM. Auto-detect PAL (B/G/H/I/D), NTSC-M (with pedestal), SECAM. Auto-detect PAL-N, NTSC-M (without pedestal), SECAM. Auto-detect PAL-N, NTSC-M (with pedestal), SECAM. NTSC-J. NTSC-M. PAL60. NTSC-4.43. PAL-B/G/H/I/D. PAL-N (B/G/H/I/D without pedestal). PAL-M (without pedestal). PAL-M. PAL Combination N. PAL Combination N. SECAM (with pedestal). SECAM (with pedestal). Notes Composite.
S-Video
YPbPr
Composite
00
0
1
00
1
0
00
1
1
0 0 0 0 1 1 1 1 1 1 1 1
1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1
Rev. B | Page 71 of 100
ADV7183B
Subaddress 0x01 Register Video Selection Bit Description Reserved ENVSPROC Reserved BETACAM ENHSPLL Reserved SD_DUP_AV. Duplicates the AV codes from the luma into the chroma path. Reserved OF_SEL[3:0]. Allows the user to choose from a set of output formats. 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TOD. Three-State Output Drivers. This bit allows the user to threestate the output drivers: P[19:0], HS, VS, FIELD, and SFL. VBI_EN. Allows VBI data (Lines 1 to 21) to be passed through with only a minimum amount of filtering performed. 0x04 Extended Output Control RANGE. Allows the user to select the range of output values. Can be BT656 compliant, or can fill the whole accessible number range. EN_SFL_PIN 0 1 0 1 0 1 0 1 0 1 x 1 0 1 BT656-3-compatible. BT656-4-compatible. x 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 76 5 Bits 43 0 1 2 0 1 0 0 0 Comments Set to default. Disable Vsync processor. Enable Vsync processor. Set to default. Standard video input. Betacam input enable. Disable Hsync processor. Enable Hsync processor. Set to default. AV codes to suit 8-bit interleaved data output. AV codes duplicated (for 16-bit interfaces). Set as default. Reserved. Reserved. 16-bit @ LLC1 4:2:2. 8-bit @ LLC1 4:2:2 ITU-R BT.656. Not used. Not used. Not used. Not used. Not used. Not used. Not used. Not used. Not used. Not used. Not used. Not used. Output pins enabled. Notes
0x03
Output Control
See TIM_OE, Address 0x04[3] and Introduction.
265H 26H
1
Drivers three-stated. All lines filtered and scaled. Only active video region filtered. 16 < Y < 235, 16 < C < 240. 1 < Y < 254, 1 < C < 254. SFL output is disabled. SFL information output on the SFL pin. Decode and output color. Blank Cr and Cb. HS, VS, F three-stated. HS, VS, F forced active.
ITU-R BT.656. Extended range. SFL output enables encoder and decoder to be connected directly. During VBI.
BL_C_VBI. Blank Chroma during VBI. If set, enables data in the VBI region to be passed through the decoder undistorted. TIM_OE. Timing signals output enable. Reserved Reserved BT656-4. Allows the user to select an output mode-compatible with ITU- R BT656-3/4.
Controlled by TOD.
Rev. B | Page 72 of 100
ADV7183B
Subaddress 0x07 Register
Autodetect Enable
Bit Description AD_PAL_EN. PAL B/G/I/H autodetect enable. AD_NTSC_EN. NTSC autodetect enable. AD_PALM_EN. PAL M autodetect enable. AD_PALN_EN. PAL N autodetect enable. AD_P60_EN. PAL60 autodetect enable. AD_N443_EN. NTSC443 autodetect enable. AD_SECAM_EN. SECAM autodetect enable. AD_SEC525_EN. SECAM 525 autodetect enable.
76
5
Bits 43
2
1
0 0 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 10
Comments Disable. Enable. Disable. Enable. Disable. Enable. Disable. Enable. Disable. Enable. Disable. Enable. Disable. Enable Disable. Enable. Luma gain = 1.
Notes
0x08
Contrast Register Reserved Brightness Register Hue Register Default Value Y
CON[7:0]. Contrast adjust. This is the user control for contrast adjustment. Reserved BRI[7:0]. This register controls the brightness of the video signal. HUE[7:0]. This register contains the value for the color hue adjustment. DEF_VAL_EN. Default value enable.
0
0
0
0
0
0
0x00 Gain = 0; 0x80 Gain = 1; 0xFF Gain = 2. 0x00 = 0IRE; 0x7F = +100IRE; 0x80 = -100IRE. Hue range = -90 to +90.
0x09 0x0A
10 00
0 0
0 0
0 0
0 0
0 0
0 0
0x0B 0x0C
00
0
0
0
0
0
0 0 Free-run mode dependent on DEF_VAL_AUTO_EN. Force free-run mode on and output blue screen. Disable free-run mode. Enable automatic freerun mode (blue screen). Y[7:0] = {DEF_Y[5:0], 0, 0}.
1 DEF_VAL_AUTO_EN. Default value. 0 1
DEF_Y[5:0]. Default value Y. This register holds the Y default value. 0x0D Default Value C DEF_C[7:0]. Default value C. The Cr and Cb default values are defined in this register.
00 01
1 1
1 1
0 1
1 1 0 0
When lock is lost, freerun mode can be enabled to output stable timing, clock, and a set color. Default Y value output in free-run mode. Default Cb/Cr value output in free-run mode. Default values give blue screen output.
Cr[7:0] = DEF_C[7:4], 0, 0, 0, 0}; Cb[7:0] = DEF_C[3:0], 0, 0, 0, 0}. Set as default. Access user reg map. Access interrupt reg map. Set as default.
0x0E
ADI Control
Reserved. SUB_USR_EN. Enables the user to access the interrupt map. Reserved. 00 0 1
0
0
0
0
0
See Figure 38.
267H
Rev. B | Page 73 of 100
ADV7183B
Subaddress 0x0F Register
Power
Management
Bit Description Reserved PDBP. Power-down bit priority selects between PWRDN bit or PIN.
76
5
Bits 43
2
1 0
0 0
Comments Set to default. Chip power-down controlled by pin. Bit has priority (pin disregarded). Set to default. System functional. Powered down. Set to default. Normal operation. Start reset sequence.
Notes
0 1
Reserved PWRDN. Power-down places the decoder in a full power-down mode. Reserved RES. Chip reset loads all I2C bits with default values. 0 0 1
0 0 1
0
See PDBP, 0x0F Bit 2.
0x10
Status Register 1, Read Only
IN_LOCK LOST_LOCK FSC_LOCK FOLLOW_PW AD_RESULT[2:0]. Autodetection result reports the standard of the input video. 0 0 0 0 1 1 1 1 x x x 0 0 1 1 0 0 1 1 x 0 1 0 1 0 1 0 1 x
x x x x
In lock (right now) = 1.
Lost lock (since last read) = 1.
0x11 0x12
IDENT Read Only Status Register 2, Read Only.
COL_KILL IDENT[7:0]. Provides identification on the revision of the part. MVCS DET MVCS T3 MV PS DET MV AGC DET LL NSTD FSC NSTD Reserved INST_HLOCK GEMD SD_OP_50HZ Reserved FREE_RUN_ACT STD FLD_LEN INTERLACED PAL_SW_LOCK
FSC lock (right now) = 1. Peak white AGC mode active = 1. NTSM-MJ. NTSC-443. PAL-M. PAL60. PAL-B/G/H/I/D. SECAM. PAL-combination N. SECAM 525. Color kill is active = 1. x x x x
MV color striping detected.
Executing reset takes approximately 2 ms. This bit is self-clearing. Provides information about the internal status of the decoder.
Detected standard.
x
x
Color kill. ADV7183B = 0x13. 1 = detected. 0 = Type 2, 1 = Type 3. 1 = detected. 1 = detected. 1 = detected. 1 = detected. Unfiltered.
MV color striping type. MV pseudo sync detected. MV AGC pulses detected. Nonstandard line length.
FSC frequency nonstandard.
x x x x x x x x x x x x x x 0 0 1 00 0 0 1 0
0x13
Status Register 3, Read Only.
1 = horizontal lock achieved.
1 = Gemstar data detected.
SD 60 Hz detected. SD 50 Hz detected. 1 = free-run mode active. 1 = field length standard. 1 = interlaced video detected. 1 = swinging burst detected. Set to default. Current sources switched off. Current sources enabled. Set to default.
SD Field rate detect. Blue screen output. Correct field length found. Field sequence found. Reliable swinging burst sequence.
0x14
Analog Clamp Control
Reserved CCLEN. Current clamp enable allows the user to switch off the current sources in the analog front. Reserved
Rev. B | Page 74 of 100
ADV7183B
Subaddress 0x15 Register Digital Clamp Control 1 Bit Description Reserved DCT[1:0]. Digital clamp timing determines the time constant of the digital fine clamp circuitry. 76 0 0 1 1 0 0 0 0 0 0 5 0 1 0 1 Bits 43 0x 2 x 1 x 0 x Comments Set to default. Slow (TC = 1 sec). Medium (TC = 0.5 sec). Fast (TC = 0.1 sec). TC dependent on video. Set to default. Auto wide notch for poor quality sources or wideband filter with comb for good quality input. Auto narrow notch for poor quality sources or wideband filter with comb for good quality input. SVHS 1. SVHS 2. SVHS 3. SVHS 4. SVHS 5. SVHS 6. SVHS 7. SVHS 8. SVHS 9. SVHS 10. SVHS 11. SVHS 12. SVHS 13. SVHS 14. SVHS 15. SVHS 16. SVHS 17. SVHS 18 (CCIR601). PAL NN1. PAL NN2. PAL NN3. PAL WN 1. PAL WN 2. NTSC NN1. NTSC NN2. NTSC NN3. NTSC WN1. NTSC WN2. NTSC WN3. Reserved. Auto selection 1.5 MHz. Auto selection 2.17 MHz. SH1. SH2. SH3. SH4. SH5. Wideband mode. Notes
0x17
Shaping Filter Control
Reserved YSFM[4:0]. Selects Y-Shaping Filter mode when in CVBS only mode. Allows the user to select a wide range of low-pass and notch filters. If either auto mode is selected, the decoder selects the optimum Y filter depending on the CVBS video source quality (good vs. bad).
Decoder selects optimum Y-shaping filter depending on CVBS quality.
0
0
0
0
1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 00 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1
0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
If one of these modes is selected, the decoder does not change filter modes. Depending on video quality, a fixed filter response (the one selected) is used for good and bad quality video.
CSFM[2:0]. C-Shaping Filter mode allows the selection from a range of low-pass chrominance filters, SH1 to SH5 and wideband mode.
Automatically selects a C filter for the specified bandwidth.
Rev. B | Page 75 of 100
ADV7183B
Subaddress 0x18 Register Shaping Filter Control 2 Bit Description WYSFM[4:0]. Wideband Y shaping filter mode allows the user to select which Y shaping filter is used for the Y component of Y/C, YPbPr, B/W input signals; it is also used when a good quality input CVBS signal is detected. For all other inputs, the Y shaping filter chosen is controlled by YSFM[4:0]. 76 5 Bits 43 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 ~ 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 ~ 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 ~ 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 ~ 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ~ 1 Comments Reserved. Do not use. Reserved. Do not use. SVHS 1. SVHS 2. SVHS 3. SVHS 4. SVHS 5. SVHS 6. SVHS 7. SVHS 8. SVHS 9. SVHS 10. SVHS 11. SVHS 12. SVHS 13. SVHS 14. SVHS 15. SVHS 16. SVHS 17. SVHS 18 (CCIR 601). Reserved. Do not use. Reserved. Do not use. Reserved. Do not use. Notes
Reserved WYSFMOVR. Enables the use of automatic WYSFN filter.
0 0 1
0
0x19
Comb Filter Control
PSFSEL[1:0]. Controls the signal bandwidth that is fed to the comb filters (PAL).
0 0 1 1 0 0 1 1 11 1 0 1 0 1 0 1 1 0 0 0 1 0 1 x x
0 1 0 1
NSFSEL[1:0]. Controls the signal bandwidth that is fed to the comb filters (NTSC).
0x1D
ADI Control 2
Reserved Reserved VS_JIT_COMP_EN EN28XTAL TRI_LLC
x
Set to default. Auto selection of best filter. Manual select filter using WYSFM[4:0]. Narrow. Medium. Wide. Widest. Narrow. Medium. Medium. Wide. Set as default. Set as default. Enabled. Disabled. Use 27 MHz crystal. Use 28 MHz crystal. LLC pin active. LLC pin three-stated.
Rev. B | Page 76 of 100
ADV7183B
Subaddress 0x27 Register Pixel Delay Control Bit Description LTA[1:0]. Luma timing adjust allows the user to specify a timing difference between chroma and luma samples. 76 5 Bits 43 2 1 0 1 1 1 Reserved CTA[2:0]. Chroma timing adjust allows a specified timing difference between the luma and chroma samples. 0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 Comments No delay. Luma 1 clk (37 ns) delayed. Luma 2 clk (74 ns) early. Luma 1 clk (37 ns) early. Set to zero. Not valid setting. Chroma + 2 pixels (early). Chroma + 1 pixel (early). No delay. Chroma - 1 pixel (late). Chroma - 2 pixels (late). Chroma - 3 pixels (late). Not valid setting. Use values in LTA[1:0] and CTA[2:0] for delaying luma/chroma. LTA and CTA values determined automatically. No swapping. Swap the Cr and Cb O/P samples. Update once per video line. Update once per field. Set to default. Color kill disabled. Color kill enabled. Set to default. Manual fixed gain. Use luma gain for chroma. Automatic gain. Freeze chroma gain. Set to 1. Manual fixed gain. AGC Peak white algorithm off. AGC Peak white algorithm on. Reserved Reserved. Reserved Reserved. Freeze gain. Set to 1. Notes CVBS mode LTA[1:0] = 00b; S-Video mode LTA[1:0]= 01b, YPrPb mode LTA[1:0] = 01b.
CVBS mode CTA[2:0] = 011b. S-Video mode CTA[2:0] = 101b. YPrPb mode CTA[2:0] = 110b.
AUTO_PDC_EN. Automatically programs the LTA/CTA values so that luma and chroma are aligned at the output for all modes of operation. SWPC. Allows the Cr and Cb samples to be swapped. 0 1
1
0x2B
Misc Gain Control
PW_UPD. Peak white update determines the rate of gain.
0 1
Peak white must be enabled. See LAGC[2:0] Luma Automatic Gain Control, Address 0x2C[7:0]
268H
0x2C
AGC Mode Control
Reserved CKE. Color kill enable allows the color kill function to be switched on and off. Reserved CAGC[1:0]. Chroma automatic gain control selects the basic mode of operation for the AGC in the chroma path.
1 0 1 1
0
0
0
0
For SECAM color kill, threshold is set at 8%. See CKILLTHR[2:0]. Use CMG[11:0].
0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1
0 1 0 1
Based on color burst.
Reserved LAGC[2:0]. Luma automatic gain control selects the mode of operation for the gain control in the luma path.
Use LMG[11:0]. Blank level to sync tip. Blank level to sync tip.
Reserved
1
Rev. B | Page 77 of 100
ADV7183B
Subaddress 0x2D Register Chroma Gain Control 1 Bit Description CMG[11:8]. Chroma manual gain can be used to program a desired manual chroma gain. Reading back from this register in AGC mode gives the current gain. Reserved CAGT[1:0]. Chroma automatic gain timing allows adjustment of the chroma AGC tracking speed. 76 5 Bits 43 0 2 1 1 0 0 0 Comments Notes CAGC[1:0] settings decide in which mode CMG[11:0] operates.
1 0 0 1 1 0 0 1 0 1 0
1
0x2E
Chroma Gain Control 2 Luma Gain Control 1
CMG[7:0]. Chroma manual gain lower 8 bits. See CMG[11:8] for description. LMG[11:8]. Luma manual gain can be used to program a desired manual chroma gain or to read back the actual gain value used. Reserved LAGT[1:0]. Luma automatic gain timing allows adjustment of the luma AGC tracking speed.
0
0
0
0
0
0
0x2F
x
x
x
x
Set to 1. Slow (TC = 2 sec). Medium (TC = 1 sec). Fast (TC = 0.2 sec). Adaptive. CMG[11:0] = 750d; gain is 1 in NTSC; CMG[11:0] = 741d; gain is 1 in PAL. LAGC[1:0] settings decide in which mode LMG[11:0] operates. Set to 1. Slow (TC = 2 sec). Medium (TC = 1 sec). Fast (TC = 0.2 sec). Adaptive. LMG[11:0] = 1234 dec; gain is 1 in NTSC. LMG[11:0] = 1266d; gain is 1 in PAL.
Has an effect only if CAGC[1:0] is set to auto gain (10).
Min value is 0d (G = -60 dB) Max value is 3750 (G = 5).
1 0 0 1 1 x 0 1 0 1 x
1
Has an effect only if LAGC[1:0] is set to auto gain (001, 010, 011,or 100). Min value: NTSC 1024 (G = 0.85), PAL (G = 0.81). Max value: NTSC 2468 (G = 2), PAL = 2532 (G = 2). HSE = Hsync end. HSB = Hsync begin.
0x30
Luma Gain Control 2
LMG[7:0]. Luma manual gain can be used to program a desired manual chroma gain or read back the actual used gain value.
x
x
x
x
x
x
0x31
VS and FIELD Control 1
Reserved HVSTIM. Selects where within a line of video the VS signal is asserted. NEWAVMODE. Sets the EAV/SAV mode. 0
0 0 1
1
0
Set to default.
Start of line relative to HSE. Start of line relative to HSB.
EAV/SAV codes generated to suit ADI encoders.
Manual VS/field position controlled by Registers 0x32, 0x33, and 0xE5 to 0xEA.
1
0x32
Vsync Field Control 2
Reserved Reserved VSBHE
00
0 0 0 0 0 0 1
Set to default. Set to default.
VS goes high in the middle of the line (even field). VS changes state at the start of the line (even field). VS goes high in the middle of the line (odd field). VS changes state at the start of the line (odd field). Set to default. VS goes low in the middle of the line (even field). VS changes state at the start of the line (even field). VS goes low in the middle of the line (odd field). VS changes state at the start of the line odd field.
NEWAVMODE bit must be set high.
0 1
VSBHO
0 1
0x33
Vsync Field Control 3
Reserved VSEHE
0 0 1
0
0
1
0
0
NEWAVMODE bit must be set high.
VSEHO
0 1
Rev. B | Page 78 of 100
ADV7183B
Subaddress 0x34 Register
HS Position
Bit Description HSE[10:8]. HS end allows the positioning of the HS output within the video line. Reserved HSB[10:8]. HS begin allows the positioning of the HS output within the video line. Reserved HSB[7:0] Using HSB[10:0] and HSE[10:0], the user can program the position and length of HS output signal. HSE[7:0] See above. PCLK. Sets the polarity of LLC1.
76
5
Bits 43
2 0
1 0
0 0
Control 1
0 0 0 0
0x35
HS Position Control 2
0 00
Comments HS output ends HSE[10:0] pixels after the falling edge of Hsync. Set to 0. HS output starts HSB[10:0] pixels after the falling edge of Hsync. Set to 0.
Notes Using HSB and HSE the user can program the position and length of the output Hsync.
0
0
0
0
1
0
0x36 0x37
HS Position
00
0
0
0
0
0
0 0 1 Invert polarity. Normal polarity as per the timing diagrams. Set to 0. Active high. Active low. Set to 0. Active high. Active low. Set to 0. Active high. Active low.
Adaptive 3-line, 3-tap luma .
Control 3 Polarity
Reserved. PF. Sets the FIELD polarity. Reserved. PVS. Sets the VS polarity. Reserved PHS. Sets HS polarity. 0x38 NTSC Comb Control YCMN[2:0]. Luma comb mode, NTSC. 0 0 1 0 0 1
0 0 1
0
0 1 1 1 1 0 0 0
0 0 0 1 1
0 0 1 0 1
CCMN[2:0]. Chroma comb mode, NTSC.
1 1
0 0
0 1
1
1
0
1
1
1
CTAPSN[1:0]. Chroma comb taps, NTSC.
0 0 1 1
0 1 0 1
Use low-pass notch. Fixed luma comb (2-line). Fixed luma comb (3-Line). Fixed luma comb (2-line). 3-line adaptive for CTAPSN = 01; 4-line adaptive for CTAPSN = 10; 5-line adaptive for CTAPSN = 11. Disable chroma comb. Fixed 2-line for CTAPSN = 01; Fixed 3-line for CTAPSN = 10; Fixed 4-line for CTAPSN = 11. Fixed 3-line for CTAPSN = 01; Fixed 4-line for CTAPSN = 10; Fixed 5-line for CTAPSN = 11. Fixed 2-line for CTAPSN = 01; Fixed 3-line for CTAPSN = 10; Fixed 4-line for CTAPSN = 11. Adapts 3 lines - 2 lines. Not used. Adapts 5 lines - 3 lines. Adapts 5 lines - 4 lines.
Top lines of memory. All lines of memory.
Bottom lines of memory.
Top lines of memory.
All lines of memory.
Bottom lines of memory.
Rev. B | Page 79 of 100
ADV7183B
Subaddress 0x39 Register PAL Comb Control Bit Description YCMP[2:0]. Luma Comb mode, PAL. 76 5 Bits 43 2 0 1 1 1 1 CCMP[2:0]. Chroma Comb mode, PAL. 0 0 0 1 0 0 1 1 1 0 0 0 0 0 1 Comments Adaptive 5-line, 3-tap luma comb. Use low-pass notch. Fixed luma comb. Fixed luma comb (5-line). Fixed luma comb (3-line). 3-line adaptive for CTAPSN = 01; 4-line adaptive for CTAPSN = 10; 5-line adaptive for CTAPSN = 11. Disable chroma comb Fixed 2-line for CTAPSN = 01. Fixed 3-line for CTAPSN = 10. Fixed 4-line for CTAPSN = 11. Fixed 3-line for CTAPSN = 01. Fixed 4-line for CTAPSN = 10. Fixed 5-line for CTAPSN = 11. Fixed 2-line for CTAPSN = 01. Fixed 3-line for CTAPSN = 10. Fixed 4-line for CTAPSN = 11. Not used. Adapts 5 lines - 3 lines (2 taps). Adapts 5 lines - 3 lines (3 taps). Adapts 5 lines - 4 lines (4 taps). Set as default. ADC2 normal operation. Power down ADC2. ADC1 normal operation. Power down ADC1. ADC0 normal operation. Power down ADC0. Set as default. Set to default. Kill at 0.5%. Kill at 1.5%. Kill at 2.5%. Kill at 4%. Kill at 8.5%. Kill at 16%. Kill at 32%. Reserved. Set to default. Notes
Top lines of memory. All lines of memory. Bottom lines of memory.
1 1
0 0
0 1
Top lines of memory.
1
1
0
All lines of memory.
1
1
1
Bottom lines of memory.
CTAPSP[1:0]. Chroma comb taps, PAL.
00 01 10 11
0x3A
Reserved PWRDN_ADC_2. Enables powerdown of ADC2. PWRDN_ADC_1. Enables powerdown of ADC1. PWRDN_ADC_0. Enables powerdown of ADC0. 0 1 00 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1
0 0 1
0x3D
Manual Window Control
Reserved Reserved CKILLTHR[2:0].
1
1
CKE = 1 enables the color kill function and must be enabled for CKILLTHR[2:0] to take effect.
Reserved
Rev. B | Page 80 of 100
ADV7183B
Subaddress 0x41 Register Resample Control Bit Description Reserved SFL_INV. Controls the behavior of the PAL switch bit. 76 0 5 0 Bits 43 10 2 0 1 0 0 0 Comments Set to default. SFL compatible with ADV7190/ADV7191/ ADV7194 encoders. SFL compatible with ADV717x/ADV7173x encoders. Set to default. GDECEL[15:0]. 16 individual enable bits that select the lines of video (even field Lines 10 to 25) that the decoder checks for Gemstar-compatible data. GDECOL[15:0]. 16 individual enable bits that select the lines of video (odd field lines 10 to 25) that the decoder checks for Gemstar-compatible data. Split data into half byte. Notes
1
0x48 0x49
Gemstar Control 1 Gemstar Control 2
Reserved GDECEL[15:8]. See the Comments column. GDECEL[7:0]. See Comments column.
0 00 00
0 0
0 0
0 0
0 0
0 0
0 0
0x4A
Gemstar Control 3 Gemstar Control 4 Gemstar Control 5
GDECOL[15:8]. See the Comments column. GDECOL[7:0]. See Comments column. GDECAD. Controls the manner in which decoded Gemstar data is inserted into the horizontal blanking period.
00
0
0
0
0
0
0
0x4B
00
0
0
0
0
0
0
0x4C
0
LSB = Line 10; MSB = Line 25. Default = Do not check for Gemstarcompatible data on any lines[10 to 25] in even fields. LSB = Line 10; MSB = Line 25. Default = Do not check for Gemstarcompatible data on any lines[10 to 25] in odd fields. To avoid 00/FF code.
1
Output in straight 8-bit format. Undefined. Disable CTI. Enable CTI. Disable CTI alpha blender. Enable CTI alpha blender. Sharpest mixing. Sharp mixing. Smooth. Smoothest. Set to default. Bypass the DNR block. Enable the DNR block. Set to default. Set to 0x04 for A/V input; set to 0x0A for tuner input.
0x4D
CTI DNR Control 1
Reserved CTI_EN. CTI enable. CTI_AB_EN. Enables the mixing of the transient improved chroma with the original signal. CTI_AB[1:0]. Controls the behavior of the alpha-blend circuitry.
x
x
x
x
x
x
x 0 1 0 1
0 0 1 1 0 0 1 11 00 0 0 1
0 1 0 1
Reserved DNR_EN. Enable or bypass the DNR block. 0x4E CTI DNR Control 2 CTI DNR Control 4 Reserved CTI_CTH[7:0]. Specifies how big the amplitude step must be to be steepened by the CTI block. DNR_TH[7:0]. Specifies the maximum edge that is interpreted as noise and is therefore blanked.
0
0
0
0x50
00
0
0
1
0
0
0
Rev. B | Page 81 of 100
ADV7183B
Subaddress 0x51 Register Lock Count Bit Description CIL[2:0]. Count-into-lock determines the number of lines the system must remain in lock before showing a locked status. 76 5 Bits 43 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 Comments 1 line of video. 2 lines of video. 5 lines of video. 10 lines of video. 100 lines of video. 500 lines of video. 1000 lines of video. 100000 lines of video. 1 line of video. 2 lines of video. 5 lines of video. 10 lines of video. 100 lines of video. 500 lines of video. 1000 lines of video. 100000 lines of video. Over field with vertical info. Line-to-line evaluation. Lock status set only by horizontal lock. Lock status set by horizontal lock and subcarrier lock. Set to default. LLC1 (nominal 27 MHz) selected out on LLC1 pin. LLC2 (nominally 13.5 MHz) selected out on LLC1 pin. Set to default. No WSS detected. WSS detected. No CCAP signals detected. CCAP sequence detected. No EDTV sequence detected. EDTV sequence detected. No CGMS transition detected. CGMS sequence decoded. Notes
COL[2:0]. Count-out-of-lock determines the number of lines the system must remain out-of-lock before showing a lost-locked status.
0 0 0 0 1 1 1 1 0 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
SRLS. Select raw lock signal. Selects the determination of the lock status. FSCLE. Fsc lock enable. 0 1
0x8F
Free Run Line Length 1
Reserved LLC_PAD_SEL[2:0]. Enables manual selection of clock for LLC1 pin.
0 0 1 0 0 0 1
0
0
0
For 16-bit 4:2:2 out, OF_SEL[3:0] = 0010.
0x90
VBI Info
(Read Only)
Reserved WSSD. Screen signaling detected. CCAPD. Closed caption data.
0 0 1 0 1
Read only status bits.
EDTVD. EDTV sequence.
0 1
CGMSD. CGMS sequence.
0 1
Reserved. 0x91 WSS1
(Read Only)
WSS1[7:0] Wide screen signaling data.
x x
x x
x x
x x
x
x
x
x
0x92
0x93 0x94 0x95 0x96
WSS2
(Read Only)
WSS2
(Read Only)
EDTV2
(Read Only)
EDTV3
(Read Only)
CGMS1
(Read Only)
WSS2[7:0] Wide screen signaling data. WSS2[7:0] Wide screen signaling data. EDTV2[7:0] EDTV data register. EDTV3[7:0] EDTV data register. CGMS1[7:0] CGMS data register.
xx
x x x x x x x x
x
x x x x
x
x x x x
x
x x x x
x
x x x x
x
x x x x
x
x x x x
WSS2[7:6] are undetermined.
EDTV3[7:6] are undetermined.
EDTV3[5] is reserved for future use.
Rev. B | Page 82 of 100
ADV7183B
Subaddress 0x97 0x98 0x99 0x9A 0x9B Register CGMS2
(Read Only)
Bit Description
CGMS3
(Read Only)
CCAP1
(Read Only)
CCAP2
(Read Only) Letterbox 1 (Read Only) Letterbox 2 (Read Only)
CGMS2[7:0] CGMS data register. CGMS3[7:0] CGMS data register. CCAP1[7:0] Closed caption data register. CCAP2[7:0] Closed caption data register. LB_LCT[7:0] Letterbox data register. LB_LCM[7:0] Letterbox data register.
76 xx x x x x x x x x
5 x x x x x
Bits 43 xx x x x x x x x x
2 x x x x x
1 x x x x x
0 x x x x x
Comments
Notes
CGMS3[7:4] are undetermined. CCAP1[7] contains parity bit for byte 0. CCAP2[7] contains parity bit for byte 0. Reports the number of black lines detected at the top of active video. This feature examines the active video at the start and at the end of each field. It enables format detection even if the video is not accompanied by a CGMS or WSS sequence.
0x9C
xx
x
x
x
x
x
x
0x9D
Letterbox 3 (Read Only)
LB_LCB[7:0] Letterbox data register.
xx
x
x
x
x
x
x
Reports the number of black lines detected in the bottom half of active video if subtitles are detected. Reports the number of black lines detected at the bottom of active video.
Set as default. Turn off CRC check. CGMSD goes high with valid checksum. Set as default.
0xB2
CRC Enable Write Register
Reserved. CRC_ENABLE. Enable CRC checksum decoded from CGMS packet to validate CGMSD. Reserved 00 0 1 1 0 1
0
0
Rev. B | Page 83 of 100
ADV7183B
Subaddress 0xC3 Register ADC SWITCH 1 Bit Description ADC0_SW[3:0]. Manual muxing control for ADC0. 76 5 Bits 43 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Comments No connection. AIN1. AIN2. AIN3. AIN4. AIN5. AIN6. No connection. No connection. AIN7. AIN8. AIN9. AIN10. AIN11. AIN12. No connection. No connection. No connection. No connection. AIN3. AIN4. AIN5. AIN6. No connection. No connection. No connection. No connection. AIN9. AIN10. AIN11. AIN12. No connection. Notes
SETADC_sw_man_ en = 1.
ADC1_SW[3:0]. Manual muxing control for ADC1.
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
SETADC_sw_man_ en = 1.
0xC4
ADC SWITCH 2
ADC2_SW[3:0]. Manual muxing control for ADC2.
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x 0 1 x x
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
No connection. No connection. AIN2. No connection. No connection. AIN5. AIN6. No connection. No connection. No connection. AIN8. No connection. No connection. AIN11. AIN12. No connection. Disable. Enable.
SETADC_sw_man_ en = 1.
Reserved ADC_SW_MAN_EN. Enable manual setting of the input signal muxing.
Rev. B | Page 84 of 100
ADV7183B
Subaddress Register Bit Description 76 5 Bits 43 2 1 0 Comments Notes
0xDC
Letterbox Control 1
0xDD
Letterbox Control 2
LB_TH[4:0]. Sets the threshold value that determines if a line is black. Reserved LB_EL[3:0]. Programs the end line of the activity window for LB detection (end of field). LB_SL[3:0]. Program the start line of the activity window for LB detection (start of field).
0
1
1
0
0
10
1 1 1 0 0
01
0
0
Default threshold for the detection of black lines. Set as default. LB detection ends with the last line of active video on a field, 1100b: 262/525. Letterbox detection aligned with the start of active video, 0100b: 23/286 NTSC.
0xDE 0xDF 0xE0 0xE1
SD Offset Cb SD Offset Cr SD Satura tion Cb SD Saturation Cr NTSC V Bit Begin
0xE2
0xE3
0xE4
0xE5
Reserved Reserved Reserved SD_OFF_CB[7:0]. Adjusts the hue by selecting the offset for the Cb channel. SD_OFF_CR[7:0]. Adjusts the hue by selecting the offset for the Cr channel. SD_SAT_CB[7:0]. Adjusts the saturation of the picture by affecting gain on the Cb channel. SD_SAT_CR[7:0]. Adjusts the saturation of the picture by affecting gain on the Cr channel. NVBEG[4:0]. Number of lines after lCOUNT rollover to set V high. NVBEGSIGN
0 0 0 1
0 0 0 0
0 0 0 0
0 0 1 0
0 0 0 0
0 0 1 0
0 0 0 0
0 0 0 0
10
0
0
0
0
0
0
10
0
0
0
0
0
0
Chroma gain = 0 dB.
10
0
0
0
0
0
0
Chroma gain = 0 dB.
0 0 1
0
1
0
1
NTSC default (BT.656). Set to low when manual programming. Not suitable for user programming. No delay. Additional delay by 1 line. No delay. Additional delay by 1 line. NTSC default (BT.656). Set to low when manual programming. Not suitable for user programming. No delay. Additional delay by 1 line. No delay. Additional delay by 1 line.
NVBEGDELE. Delay V bit going high by one line relative to NVBEG (even field). NVBEGDELO. Delay V bit going high by one line relative to NVBEG (odd field). 0xE6 NTSC V Bit End NVEND[4:0]. Number of lines after lCOUNT rollover to set V low. NVENDSIGN 0 1
0 1
0 0 1
0
1
0
0
NVENDDELE. Delay V bit going low by one line relative to NVEND (even field). NVENDDELO. Delay V bit going low by one line relative to NVEND (odd field). 0 1
0 1
Rev. B | Page 85 of 100
ADV7183B
Subaddress Register Bit Description 76 5 Bits 43 2 1 0 Comments Notes
0xE7
NTSC F Bit Toggle
NFTOG[4:0]. Number of lines after lCOUNT rollover to toggle F signal. NFTOGSIGN
0 0 1
0
0
1
1
NTSC default. Set to low when manual programming. Not suitable for user programming. No delay. Additional delay by 1 line. No delay. Additional delay by 1 line. PAL default (BT.656). Set to low when manual programming. Not suitable for user programming. No delay. Additional delay by 1 line. No delay. Additional delay by 1 line. PAL default (BT.656). Set to low when manual programming. Not suitable for user programming. No delay. Additional delay by 1 line. No delay. Additional delay by 1 line. PAL default (BT.656). Set to low when manual programming. Not suitable for user programming. No delay. Additional delay by 1 line. No delay. Additional delay by 1 line.
NFTOGDELE. Delay F transition by one line relative to NFTOG (even field). NFTOGDELO. Delay F transition by one line relative to NFTOG (odd field). 0xE8 PAL V Bit Begin PVBEG[4:0]. Number of lines after lCOUNT rollover to set V high. PVBEGSIGN 0 1
0 1
0 0 1
0
1
0
1
PVBEGDELE. Delay V bit going high by one line relative to PVBEG (even field). PVBEGDELO. Delay V bit going high by one line relative to PVBEG (odd field). 0xE9 PAL V Bit End PVEND[4:0]. Number of lines after lCOUNT rollover to set V low. PVENDSIGN 0 1
0 1
1 0 1
0
1
0
0
PVENDDELE. Delay V bit going low by one line relative to PVEND (even field). PVENDDELO. Delay V bit going low by one line relative to PVEND (odd field). 0xEA PAL F Bit Toggle PFTOG[4:0]. Number of lines after lCOUNT rollover to toggle F signal. PFTOGSIGN 0 1
0 1
0 0 1
0
0
1
1
PFTOGDELE. Delay F transition by one line relative to PFTOG (even field). PFTOGDELO. Delay F transition by one line relative to PFTOG (odd field). 0 1
0 1
Rev. B | Page 86 of 100
ADV7183B
Subaddress Register Bit Description 76 5 Bits 43 2 1 0 Comments Notes
0xF4
Drive Strength
DR_STR_S[1:0]. Select the drive strength for the sync output signals.
0 0 1 1
0 1 0 1
DR_STR_C[1:0]. Select the drive strength for the clock output signal.
0 0 1 1
0 1 0 1
DR_STR[1:0]. Select the drive strength for the data output signals. Can be increased or decreased for EMC or crosstalk reasons.
0 0 1 1
0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0
0xF8
IF Comp Control
Reserved IFFILTSEL[2:0] IF filter selection for PAL and NTSC
xx
Low drive strength (1x). Medium-low drive strength (2x). Medium-high drive strength (3x). High drive strength (4x). Low drive strength (1x). Medium-low drive strength (2x). Medium-high drive strength (3x). High drive strength (4x). Low drive strength (1x). Medium-low drive strength (2x). Medium-high drive strength (3x). High drive strength (4x). No delay. Bypass mode. 2 MHz 5 MHz -3 dB -2 dB -6 dB -10 dB Reserved. 3 MHz -2 dB -5 dB -7 dB +3.5 dB +5 dB 6 MHz +2 dB +3 dB +5 dB
0 dB. NTSC filters.
PAL filters.
0xF9
VS Mode Control
Reserved EXTEND_VS_MAX_FREQ
00
0
0
0 Limit maximum Vsync frequency to 66.25 Hz (475 lines/frame). Limit maximum Vsync frequency to 70.09 Hz (449 lines/frame). Limit minimum Vsync frequency to 42.75 Hz (731 lines/frame). Limit minimum Vsync frequency to 39.51 Hz (791 lines/frame). Auto coast mode. 50 Hz coast mode. 60 Hz coast mode. Reserved.
1
EXTEND_VS_MIN_FREQ
0
1
VS_COAST_MODE[1:0]
0 0 1 1 00 0 0
0 1 0 1
This value sets up the output coast frequency.
Reserved
Rev. B | Page 87 of 100
ADV7183B I2C PROGRAMMING EXAMPLES
EXAMPLES IN THIS SECTION USE A 28 MHz CLOCK.
Mode 1 CVBS Input (Composite Video on AIN5)
All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8.
Table 87. Mode 1 CVBS Input
Register Address 0x00 0x15 0x17 0x1D 0x0F 0x3A 0x3D 0x3F 0x50 0x0E 0x50 0x52 0x58 0x77 0x7C 0x7D 0x90 0x91 0x92 0x93 0x94 0xCF 0xD0 0xD6 0xE5 0xD5 0xD7 0xE4 0xE9 0xEA 0x0E Register Value 0x04 0x00 0x41 0x40 0x40 0x16 0xC3 0xE4 0x04 0x80 0x20 0x18 0xED 0xC5 0x93 0x00 0xC9 0x40 0x3C 0xCA 0xdD 0x50 0x4E 0xDD 0x51 0xA0 0xEA 0x3E 0x3E 0x0F 0x00 Notes CVBS input on AIN5. Slow down digital clamps. Set CSFM to SH1. Enable 28 MHz crystal. TRAQ. Power down ADC 1 and ADC 2. MWE enable manual window. BGB to 36. Set DNR threshold to 4 for flat response. ADI recommended programming sequence. This sequence must be followed exactly when setting up the decoder. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting.
Rev. B | Page 88 of 100
ADV7183B
Mode 2 S-Video Input (Y on AIN1 and C on AIN4)
All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8.
Table 88. Mode 2 S-Video Input
Register Address 0x00 0x15 0x3A 0x1D 0x0F 0x3D 0x3F 0x50 0x0E 0x50 0x52 0x58 0x77 0x7C 0x7D 0x90 0x91 0x92 0x93 0x 94 0xCF 0xD0 0xD6 0xE5 0xD5 0xD7 0xE4 0xE9 0xEA 0x0E Register Value 0x06 0x00 0x12 0x40 0x40 0xC3 0xE4 0x04 0x80 0x20 0x18 0xED 0xC5 0x93 0x00 0xC9 0x40 0x3C 0xCA 0xdD 0x50 0x4E 0xDD 0x51 0xA0 0xEA 0x3E 0x3E 0x0F 0x00 Notes Y1 = AIN1, C1 = AIN4. Slow down digital clamps. Power down ADC 2. Enable 28 MHz crystal. TRAQ. MWE enable manual window. BGB to 36. Set DNR threshold to 4 for flat response. ADI recommended programming sequence. This sequence must be followed exactly when setting up the decoder. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting.
Rev. B | Page 89 of 100
ADV7183B
Mode 3 525i/625i YPrPb Input (Y on AIN2, PB on AIN3, and PR on AIN6)
All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8.
Table 89. Mode 3 YPrPb Input 525i/625i
Register Address 0x00 0x1D 0x0F 0x3D 0x3F 0x50 0x0E 0x52 0x58 0x77 0x7C 0x90 0x91 0x92 0x93 0x94 0xCF 0xD0 0xD6 0xE5 0xE9 0x0E Register Value 0x0A 0x40 0x40 0xC3 0xE4 0x04 0x80 0x18 0xED 0xC5 0x93 0xC9 0x40 0x3C 0xCA 0xdD 0x50 0x4E 0xDD 0x51 0x3E 0x00 Notes Y2 = AIN2, PB2 = AIN3, PR2 = AIN6. Enable 28 MHz crystal. TRAQ. MWE enable manual window. BGB to 36. Set DNR threshold to 4 for flat response. ADI recommended programming sequence. This sequence must be followed exactly when setting up the decoder. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting.
Rev. B | Page 90 of 100
ADV7183B
Mode 4 CVBS Tuner Input PAL Only on AIN4
8-bit, ITU-R BT.656 output on P15 to P8.
Table 90. Mode 4 Tuner Input CVBS PAL Only
Register Address 0x00 0x07 0x15 0x17 0x1D 0x0F 0x3D 0x3F 0x19 0x3A 0x50 0x0E 0x50 0x52 0x58 0x77 0x7C 0x7D 0x90 0x91 0x92 0x93 0x94 0xCF 0xD0 0xD6 0xE5 0xD5 0xD7 0xE4 0xE9 0xEA 0x0E Register Value 0x83 0x01 0x00 0x41 0x40 0x40 0xC3 0xE4 0xFA 0x16 0x0A 0x80 0x20 0x18 0xED 0xC5 0x93 0x00 0xC9 0x40 0x3C 0xCA 0xdD 0x50 0x4E 0xDD 0x51 0xA0 0xEA 0x3E 0x3E 0x0F 0x00 Notes CVBS AIN4 Force PAL only mode. Enable PAL autodetection only. Slow down digital clamps. Set CSFM to SH1. Enable 28 MHz crystal TRAQ MWE enable manual window BGB to 36 Stronger dot crawl reduction. Power down ADC 1 and ADC 2. Set higher DNR threshold. ADI recommended programming sequence. This sequence must be followed exactly when setting up the decoder. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting.
Rev. B | Page 91 of 100
ADV7183B
EXAMPLES USING 27 MHz CLOCK
Mode 1 CVBS Input (Composite Video on AIN5)
All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8.
Table 91. Mode 1 CVBS Input
Register Address 0x00 0x15 0x17 0x3A 0x50 0x0E 0x50 0x52 0x58 0x77 0x7C 0x7D 0xD0 0xD5 0xD7 0xE4 0xE9 0xEA 0x0E Register Value 0x04 0x00 0x41 0x16 0x04 0x80 0x20 0x18 0xED 0xC5 0x93 0x00 0x48 0xA0 0xEA 0x3E 0x3E 0x0F 0x00 Notes CVBS input on AIN5. Slow down digital clamps. Set CSFM to SH1. Power down ADC 1 and ADC 2. Set DNR threshold to 4 for flat response. ADI recommended programming sequence. This sequence must be followed exactly when setting up the decoder. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting Recommended setting. Recommended setting.
Mode 2 S-Video Input (Y on AIN1 and C on AIN4)
All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8.
Table 92. Mode 2 S-Video Input
Register Address 0x00 0x15 0x3A 0x50 0x0E 0x50 0x52 0x58 0x77 0x7C 0x7D 0xD0 0xD5 0xD7 0xE4 0xE9 0xEA 0x0E Register Value 0x06 0x00 0x12 0x04 0x80 0x20 0x18 0xED 0xC5 0x93 0x00 0x48 0xA0 0xEA 0x3E 0x3E 0x0F 0x00 Notes Y1 = AIN1, C1 = AIN4. Slow down digital clamps. Power down ADC 2. Set DNR threshold to 4 for flat response. ADI recommended programming sequence. This sequence must be followed exactly when setting up the decoder. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting Recommended setting. Recommended setting.
Rev. B | Page 92 of 100
ADV7183B
Mode 3 525i/625i YPrPb Input (Y on AIN2, PB on AIN3, and PR on AIN6)
All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8.
Table 93. Mode 3 YPrPb Input 525i/625i
Register Address 0x00 0x50 0x0E 0x52 0x58 0x77 0x7C 0x7D 0xD0 0xD5 0xE4 0xE9 0x0E Register Value 0x0A 0x04 0x80 0x18 0xED 0xC5 0x93 0x00 0x48 0xA0 0x3E 0x3E 0x00 Notes Y2 = AIN2, PB2 = AIN3, PR2 = AIN6. Set DNR threshold to 4 for flat response. ADI recommended programming sequence. This sequence must be followed exactly when setting up the decoder. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting Recommended setting.
Mode 4 CVBS Tuner Input PAL Only on AIN4
8-bit, ITU-R BT.656 output on P15 to P8.
Table 94. Mode 4 Tuner Input CVBS PAL Only
Register Address 0x00 0x07 0x15 0x17 0x19 0x3A 0x50 0x0E 0x50 0x52 0x58 0x77 0x7C 0x7D 0xD0 0xD5 0xD7 0xE4 0xE9 0xEA 0x0E Register Value 0x83 0x01 0x00 0x41 0xFA 0x16 0x0A 0x80 0x20 0x18 0xED 0xC5 0x93 0x00 0x48 0xA0 0xEA 0x3E 0x3E 0x0F 0x00 Notes CVBS AIN4 Force PAL only mode. Enable PAL autodetection only. Slow down digital clamps. Set CSFM to SH1. Stronger dot crawl reduction. Power down ADC 1 and ADC 2. Set higher DNR threshold. ADI recommended programming sequence. This sequence must be followed exactly when setting up the decoder. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting Recommended setting. Recommended setting.
Rev. B | Page 93 of 100
ADV7183B PCB LAYOUT RECOMMENDATIONS
The ADV7183B is a high precision, high speed, mixed-signal device. To achieve the maximum performance from the part, it is important to have a PCB board with a good layout. This section provides guidelines for designing a board using the ADV7183B.
ADV7183B
04997-042
ANALOG SECTION
DIGITAL SECTION
Figure 42. PCB Ground Layout
ANALOG INTERFACE INPUTS
Care should be taken when routing the inputs on the PCB. Track lengths should be kept to a minimum, and 75 trace impedances should be used when possible. Trace impedances other than 75 also increase the chance of reflections.
Experience shows that the noise performance is the same or better with a single ground plane. Using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result. In some cases, using separate ground planes is unavoidable. For those cases, it is recommended to place a single ground plane under the ADV7183B. The location of the split should be under the ADV7183B. For this case, it is even more important to place components wisely because the current loops will be much longer (current takes the path of least resistance). An example of a current loop: power plane to ADV7183B to digital output trace to digital data receiver to digital ground plane to analog ground plane.
POWER SUPPLY DECOUPLING
It is recommended to decouple each power supply pin with 0.1 F and 10 nF capacitors. The fundamental idea is to have a decoupling capacitor within about 0.5 cm of each power pin. Also, avoid placing the capacitor on the opposite side of the PC board from the ADV7183B, as doing so interposes resistive vias in the path. The decoupling capacitors should be located between the power plane and the power pin. Current should flow from the power plane to the capacitor to the power pin. Do not make the power connection between the capacitor and the power pin. Placing a via underneath the 100 nF capacitor pads, down to the power plane, is generally the best approach (see Figure 41).
269H 271H
PLL
Place the PLL loop filter components as close as possible to the ELPF pin. Do not place any digital or other high frequency traces near these components. Use the values suggested in Figure 46 with tolerances of 10% or less.
VDD 10nF GND 100nF
VIA TO SUPPLY
DIGITAL OUTPUTS (BOTH DATA AND CLOCKS)
Try to minimize the trace length the digital outputs have to drive. Longer traces have higher capacitance, which requires more current, which causes more internal digital noise. Shorter traces reduce the possibility of reflections. Adding a 30 to 50 series resistor can suppress reflections, reduce EMI, and reduce the current spikes inside the ADV7183B. If series resistors are used, place them as close as possible to the ADV7183B pins. However, try not to add vias or extra length to the output trace to make the resistors closer. If possible, limit the capacitance that each of the digital outputs drive to less than 15 pF. This can easily be accomplished by keeping traces short and by connecting the outputs to only one device. Loading the outputs with excessive capacitance increases the current transients inside the ADV7183B, creating more digital noise on its power supplies.
VIA TO GND
04997-041
Figure 41. Recommended Power Supply Decoupling
It is very important to maintain low noise and good stability of PVDD. Careful attention must be paid to regulation, filtering, and decoupling. It is highly desirable to provide separate regulated supplies for each of the analog circuitry groups (AVDD, DVDD, DVDDIO, and PVDD). Some graphic controllers use substantially different levels of power when active (during active picture time) and when idle (during horizontal and vertical sync periods). This can result in a measurable change in the voltage supplied to the analog supply regulator, which can, in turn, produce changes in the regulated analog supply voltage. This can be mitigated by regulating the analog supply, or at least PVDD, from a different, cleaner power source, such as a 12 V supply. It is also recommended to use a single ground plane for the entire board. This ground plane should have a space between the analog and digital sections of the PCB (see Figure 42).
270H
DIGITAL INPUTS
The digital inputs on the ADV7183B are designed to work with 3.3 V signals, and are not tolerant of 5 V signals. Extra components are needed if 5 V logic signals are required to be applied to the decoder.
Rev. B | Page 94 of 100
ADV7183B
ANTIALIASING FILTERS
For inputs from some video sources that are not bandwidth limited, signals outside the video band can alias back into the video band during A/D conversion and appear as noise on the output video. The ADV7183B oversamples the analog inputs by a factor of 4. This 54 MHz sampling frequency reduces the requirement for an input filter; for optimal performance, it is recommended that an antialiasing filter be used. The recommended low cost circuit for implementing this buffer and filter circuit for all analog input signals is shown in Figure 45.
274H 27H
CRYSTAL LOAD CAPACITOR VALUE SELECTION
Figure 44 shows an example of a reference clock circuit for the ADV7183B. Special care must be taken when using a crystal circuit to generate the reference clock for the ADV7183B. Small variations in reference clock frequency can cause autodetection issues and impair the ADV7183B performance. Load capacitor values are dependant on crystal attributes. The load capacitance given in a crystal data sheet specifies the parallel resonance frequency within the tolerance at 25C. Therefore, it is important to design a circuit that matches the load capacitance to achieve the frequency stipulated by the manufacturer. For accurate crystal circuit design and optimization, an applications note on crystal design considerations is available for more information.
XTAL R = 1M XTAL1
The buffer is a simple emitter-follower using a single npn transistor. The antialiasing filter is implemented using passive components. The passive filter is a third-order Butterworth filter with a -3 dB point of 9 MHz. The frequency response of the passive filter is shown in Figure 43. The flat pass band up to 6 MHz is essential. The attenuation of the signal at the output of the filter due to the voltage divider of R24 and R63 is compensated for in the ADV7183B part by using the automatic gain control. The ac-coupling capacitor at the input to the buffer creates a high-pass filter with the biasing resistors for the transistor. This filter has a cutoff of
273H
XTAL 28.63636MHz
Figure 44. Crystal Circuit
{2 x x (R39||R89) x C93}-1 = 0.62 Hz It is essential that the cutoff of this filter be less than 1 Hz to ensure correct operation of the internal clamps within the part. These clamps ensure the video stays within the 5 V range of the op amp used.
0
Follow these guidelines to ensure correct operation: * * * * Use the correct frequency crystal, which is 28.63636 MHz. Tolerance is 50 ppm or higher. Use a parallel-resonant crystal. Place a 1 M shunt resistor across pins XTAL and XTAL1, as is shown in Figure 44.
275H
-20
-40
*
-60
Know the CLOAD for the crystal part number selected. The value of Capacitor C1 and Capacitor C2 must match CLOAD for the specific crystal part number in the user's system. Use the following guideline to find CLOAD: C1 = C2 = C C = 2(CLOAD - CS) - Cpg where: Cpg is the pin-to-ground capacitance, approximately 4 pF to 10 pF. CS is the PCB stray capacitance, approximately 2 pF to 3 pF. For Example, CLOAD = 30 pF C = 2(30 - 3) - 4 = 50 pF Therefore, two 47 pF capacitors may be selected for C1 and C2.
-80
-100
300k
1M
3M 10M 30M FREQUENCY (Hz)
100M
300M
1G
Figure 43. Third-Order Butterworth Filter Response
04997-043
-120 100k
Rev. B | Page 95 of 100
04997-047
C1 47pF
C2 47pF
ADV7183B TYPICAL CIRCUIT CONNECTION
Figure 45 and Figure 46 show examples of how to connect the ADV7183B video decoder. For a detailed schematic diagram for the ADV7183B, refer to the ADV7183B evaluation note.
276H 27H
AVDD_5V R43 0 C B R53 56 R89 5.6k E R24 470 Q6
BUFFER
C93 100F R39 4.7k
FILTER
L10 12H C95 22pF C102 10pF R63 820
04997-044
R38 75
AGND
Figure 45. ADI Recommended Antialiasing Circuit for All Input Channels
Rev. B | Page 96 of 100
ADV7183B
DVDDIO (3.3V) FERRITE BEAD 33F 10F 0.1F DGND 0.01F POWER SUPPLY DECOUPLING FOR EACH POWER PIN DGND
PVDD (1.8V)
DGND DGND FERRITE BEAD 33F 10F
0.1F AGND
AVDD (3.3V)
AGND AGND FERRITE BEAD 33F 10F
0.01F POWER SUPPLY DECOUPLING FOR EACH POWER PIN AGND
0.1F AGND
DVDD (1.8V) AGND DGND S-VIDEO ANTI-ALIAS FILTER CIRCUIT ANTI-ALIAS FILTER CIRCUIT Y ANTI-ALIAS FILTER CIRCUIT ANTI-ALIAS FILTER CIRCUIT ANTI-ALIAS FILTER CIRCUIT ANTI-ALIAS FILTER CIRCUIT
75 75 75 75 75
AGND AGND FERRITE BEAD 33F DGND 100nF AIN1 100nF 100nF 100nF 100nF 100nF
75
0.01F POWER SUPPLY DECOUPLING FOR EACH POWER PIN AGND
10F DGND
AVDD DVDD PVDD DVDDIO
0.1F DGND P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15
0.01F POWER SUPPLY DECOUPLING FOR EACH POWER PIN DGND
AIN7 AIN2 AIN8 AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12
Pr Pb
ADV7183B
MULTIFORMAT PIXEL PORT P15-P8 8-BIT ITU-R BT.656 PIXEL DATA @ 27MHz P7-P0 Cb AND Cr 16-BIT ITU-R BT.656 PIXEL DATA @ 13.5MHz P15-P8 Y 16-BIT ITU-R BT.656 PIXEL DATA @ 13.5MHz
CBVS
RECOMMENDED ANTI-ALIAS FILTER CIRCUIT IS SHOWN IN FIGURE 45 ON THE PREVIOUS PAGE. THIS CIRCUIT INCLUDES A 75 TERMINATION RESISTOR, INPUT BUFFER AND ANTI-ALIASING FILTER.
AGND AGND 0.1F + CAPY1 10F 0.1F 1nF CAPY2 0.1F LLC1 LLC2 27MHz OUTPUT CLOCK 13.5MHz OUTPUT CLOCK
AGND + AGND + 10F 0.1F 1nF
CAPC1 CAPC2 CML OE OUTPUT ENABLE I/P
10F
0.1F 10F + 0.1F
REFOUT
CAPACITOR VALUES ARE DEPENDANT ON XTAL ATTRIBUTES.
INTRQ AGND 47pF DGND DVDDIO DGND 28.63636MHz XTAL1 47pF 1M XTAL SFL HS VS FIELD
INTERRUPT O/P SFL O/P HS O/P VS O/P FIELD O/P
SELECT I2C ADDRESS DVDDIO DVSS MPU INTERFACE CONTROL LINES 2k DVDDIO 2k 100
ALSB ELPF 1.69k SCLK 100 SDA PVDD DVDDIO 4.7k RESET 100nF DGND RESET AGND DGND 82nF 10nF
Figure 46. Typical Connection Diagram
Rev. B | Page 97 of 100
04997-045
AGND
DGND
ADV7183B OUTLINE DIMENSIONS
0.75 0.60 0.45 1.60 MAX
80 1 PIN 1
16.20 16.00 SQ 15.80
61 60
TOP VIEW (PINS DOWN)
14.20 14.00 SQ 13.80
1.45 1.40 1.35
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0 0.10 MAX COPLANARITY
20 21 40
41
VIEW A
VIEW A
ROTATED 90 CCW
0.65 BSC LEAD PITCH
0.38 0.32 0.22
COMPLIANT TO JEDEC STANDARDS MS-026-BEC
Figure 47. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-2) Dimensions shown in millimeters
ORDERING GUIDE
Model1 1 ADV7183BKSTZ1 2 ADV7183BBSTZ22 EVAL-ADV7183BEB
6F 7F 78H
Temperature Range 0C to +70C -40C to +85C
Package Description 80-lead Low Profile Quad Flat Package (LQFP) 80-lead Low Profile Quad Flat Package (LQFP) Evaluation Board
Package Option ST-80-2 ST-80-2
1
The ADV7183B is a Pb-free, environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications and can withstand surface-mount soldering at up to 255C (5C). In addition, the ADV71893B is backward-compatible with conventional SnPb soldering processes. This means the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220C to 235C. 2 Z = Pb-free part.
Rev. B | Page 98 of 100
ADV7183B NOTES
Rev. B | Page 99 of 100
ADV7183B NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04997-0-9/05(B)
Rev. B | Page 100 of 100

▲Up To Search▲

Price & Availability of ADV7183BKSTZ

	To Download ADV7183BKSTZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .