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Preliminary Technical Data
FEATURES
Single lane 2:1 mux/1:2 demux 3.2 Gbps to DC data rates Compensates over 40 inches of FR4 at 3.2 Gbps through Two levels of input equalization, or Four levels of output pre-emphasis Accepts ac- or dc-coupled differential inputs Low deterministic jitter, typically 20 ps p-p Low random jitter, typically 1 ps RMS BER < 10-16 On-chip terminations Unicast or bicast on 1:2 demux function Loopback capability on all ports 3.3 V core supply Flexible I/O supply Low power, typically 200 mW in basic configuration1 32-lead QFN package -40C to +85C operating temperature range
3.2 Gbps Single Buffered Switch AD8153
Receive Equalization Input A EQ Transmit PreEmphasis
2:1
Input B EQ Receive Equalization
Output C
Output A
1:2
Output B Transmit PreEmphasis
EQ
Input C
2:1 Multiplexer/ 1:2 Demultiplexer Control Logic
SEL BICAST LB_A LB_B LB_C SER/PARB RESETB EQ_A/I2C_SCL EQ_B/I2C_SDA EQ_C PE_A/I2C_ADDR0 PE_B/I2C_ADDR1 PE_C/I2C_ADDR2
APPLICATIONS
Low cost redundancy switch SONET OC48/SDH16 and lower data rates Gigabit Ethernet over backplane Fibre channel 1.06 Gbps and 2.12 Gbps over backplane Serial RapidIO PCI Express Infiniband over backplane
GENERAL DESCRIPTION
The AD8153 is an asynchronous, protocol agnostic, single-lane 2:1 switch with three differential PECL/CML-compatible inputs and three differential CML outputs. The AD8159, another member of the XstreamTM line of products, is suitable for similar applications that require more than one lane. The AD8153 is optimized for NRZ signaling with data rates of up to 3.2 Gbps per port. Each port offers two levels of input equalization and four levels of output pre-emphasis. The device consists of a 2:1 multiplexer and a 1:2 demultiplexer. There are three operating modes: pin mode, serial mode, and mixed mode. In pin mode, switching and equalization/preemphasis are controlled exclusively using external pins. In
serial mode, an I2C interface is used exclusively to control the device, and to provide access to advanced features, such as additional pre-emphasis settings and output disable. In the mixed mode mode, the user accesses the advanced features using I2C, but controls device switching using the external pins. The main application of the AD8153 is to support redundancy on both the backplane side and the line interface side of a serial link. The device has unicast and bicast capability, so it is capable of supporting either 1 + 1 or 1:1 redundancy. Another application for AD8153 is testing high speed serial links by duplicating incoming data and sending it to the destination port and to test equipment simultaneously.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2006 Analog Devices, Inc. All rights reserved.
AD8153
1
Preliminary Technical Data
Two ports active with minimum pre-emphasis.
Rev. PrA | Page 2 of 18
Preliminary Technical Data
TABLE OF CONTENTS
Features...............................................................................................1 Applications .......................................................................................1 General Description..........................................................................1 Table of Contents...............................................................................3 Revision History................................................................................3 Specifications .....................................................................................4 Absolute Maximum Ratings ............................................................5 ESD Caution ..................................................................................5 Pin configuration and function descriptions ................................6 Theory of Operation .........................................................................8
AD8153
Input Equalization (EQ) and Output Pre-Emphasis (PE).......8 Serial Control Interface ..................................................................10 Register Set...................................................................................10 General Functionality.................................................................10 I2C Data Write .............................................................................11 I2C Data Read ..............................................................................11 I2C Timing Specifications ..........................................................12 Applications .....................................................................................14 Outline Dimensions.....................Error! Bookmark not defined.
REVISION HISTORY
4/06--Revision 0: Initial version. 6/12--Revision 0.1: Updated pin configuration and package mechanical drawings.
Rev. PrA | Page 3 of 18
AD8153 SPECIFICATIONS
Preliminary Technical Data
VCC = +3.3 V, VEE = 0 V, RL = 50 , two outputs active with minimum pre-emphasis, data rate= 3.2 Gbps, VICM = 2.7 V1, VID = 800 mV pp2, TA = +25C, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE Data Rate/Channel (NRZ) Deterministic Jitter Random Jitter Propagation Delay Lane-to-Lane Skew Switching Time Output Rise/Fall Time INPUT CHARACTERISTICS Input Voltage Swing Input Voltage Range Input Bias Current Input Capacitance OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage Range Output Current Output Current Output Capacitance TERMINATION CHARACTERISTICS Resistance Temperature Coefficient POWER SUPPLY Operating Range VCC Supply Current ICC II/O = ITTO + ITTI Supply Current ICC II/O = ITTO + ITTI THERMAL CHARACTERISTICS Operating Temperature Range JA LOGIC INPUT CHARACTERISTICS Input High (VIH) Input Low (VIL)
1 2
Conditions
Min DC
Typ
Max 3.2
Unit Gbps ps p-p ps ps ps ns ps mV p-p V A pF mV p-p V mA mA pF
Data rate = 3.2 Gbps RMS Input to output
20% to 80% Differential, VICM = 2.7 V1 Common mode, VID = 800 mV p-p2 100 VEE + 1.0
20 1 600 100 5 100 2000 VCC + 0.3 4 2
Differential, PE = 0 Single-ended absolute voltage level Minimum pre-emphasis Maximum pre-emphasis, all ports
800 Vcc - 1.6 16 28 2 90 100 0.15 110 Vcc + 0.6
Differential
/C
VEE = 0 V Two outputs active, minimum pre-emphasis, dc-coupled inputs/outputs, 400 mV I/O swings (800 mV p-p differential), 50 far end terminations Three outputs active, maximum pre-emphasis, dc-coupled inputs/outputs, 400 mV I/O swings (800 mV p-p differential), 50 far end terminations
3.0
3.3 28 32 80 84
3.6
V mA mA mA mA
-40 Still air 2.4 VEE 30.0
+85
C C/W V V
VCC 0.8
VICM: Input common-mode voltage. VID: Input differential peak-to-peak voltage swing.
Rev. PrA | Page 4 of 18
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VCC to VEE VTTI VTTO Internal Power Dissipation Differential Input Voltage Logic Input Voltage Storage Temperature Range Lead Temperature Rating 3.7 V VCC + 0.6 V VCC + 0.6 V 4.1 W 2.0 V VEE - 0.3V < VIN < VCC + 0.6 V -65C to +125C 300C
AD8153
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA | Page 5 of 18
AD8153
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 31 30 29
PE_A/I2C_ADDR0
28
27
26
PE_B/I2C_ADDR1
25
PE_C/I2C_ADDR2
ONC
OPC
VEE
INC
IPC
1 2 3 4 5 6 7 8
VCC VTTO ONA OPA VTTI INA IPA VEE
MODE RESETB SEL BICAST LB_A LB_B LB_C
EQ_A/I2C_SCL
24 23 22 21 20 19 18 17
EQ_B/I2C_SDA
EQ_C
ONB
10
VCC
9
OPB
11
Figure 2: Pin Configuration
Rev. PrA | Page 6 of 18
VCC
12
INB
13
IPB
14
15
16
Preliminary Technical Data
Table 3. Pin Function Descriptions
AD8153
Pin 1,9,12 2 3 4 5 6 7 8,32 10 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Mnemonic VCC VTTO ONA OPA VTTI INA IPA VEE ONB OPB INB IPB EQ_C EQ_B/I2C_SDA EQ_A/I2C_SCL LB_C LB_B LB_A BICAST SEL RESETB MODE PE_C/I2C_ADDR2 PE_B/I2C_ADDR1 ONC OPC PE_A/I2C_ADDR0 INC IPC
Type Power Power I/O I/O Power I/O I/O Power I/O I/O I/O I/O Control Control Control Control Control Control Control Control Control Control Control Control I/O I/O Control I/O I/O
Description Positive Supply Output termination supply High speed output complement High speed output Input termination supply High speed input complement High speed input Negative Supply High speed output complement High speed output High speed input complement High speed input Port C input equalization control Port B input equalization control/I2C data Port A input equalization control/I2C clock Port C loopback enable Port B loopback enable Port A loopback enable Bicast enable A/B select Configuration registers reset Configuration mode Port C pre-emphasis control/I2C address bit 2 Port B pre-emphasis control/I2C address bit 1 High speed output complement High speed output Port A pre-emphasis control/I2C address bit 0 High speed input complement High speed output
Rev. PrA | Page 7 of 18
AD8153 THEORY OF OPERATION
On the demultiplexer side, the AD8153 relays received data on Input Port C to Output Port A and/or Output Port B, depending on the state of the BICAST and SEL bits. On the multiplexer side, the device relays received data on either Input Port A or Input Port B to Output Port C, depending on the state of the SEL bit. When bicast mode is off, the outputs of either Port A or Port B are in an idle state. In the idle state, the output tail current is set to 0, and the P and N sides of the lane are pulled up to the output termination voltage through the on-chip termination resistors. The device also supports loopback on all ports, illustrated in Figure 3. Enabling loopback on any port will override configurations set by the BICAST and SEL control bits. Table 7 summarizes the possible device switching configurations.
Preliminary Technical Data
a controlled amount of overshoot to the output waveform to compensate for the high frequency loss in a backplane trace. Tables Table 5-Table 6 summarize the high-frequency gain boost, amount of overshoot, and the typical backplane channel length (including two connectors) that can be compensated using each setting. A typical backplane is made of FR4 material with 8 mil wide trace and 8 mil spaced loosely coupled differential traces. Each channel consists of a backplane segment, two connectors, and two line cards. The total length of the channel includes 3 inches of trace on each line card. Table 4. Input Equalization Settings
EQ_x 0 1 Boost 6 dB 12 dB Typical Backplane Length 0 to 20 in. 20 to 40+ in.
Table 5. Output Pre-Emphasis Settings (Pin Mode)
PE_x 0 1 Boost 0 dB 3.5 dB Overshoot 0% 35 % Typical Backplane Length 0 to 10 in. 20 to 30 in.
INPUT EQUALIZATION (EQ) AND OUTPUT PRE-EMPHASIS (PE)
In backplane applications, the AD8153 needs to compensate for signal degradation over potentially long traces. The device supports two levels of input equalization, configured on a perport basis. line card. Table 4 summarizes the high-frequency gain boost for each control setting as well as the typical length of backplane trace that can be compensated using each setting. The device also has four levels of output pre-emphasis, configured for each port. The pre-emphasis circuitry adds
Table 6. Output Pre-Emphasis Settings (Serial Mode)
Typical Backplane Length 0 to 10 in. 10 to 20 in. 20 to 30 in. 30 to 40+ in.
PE_x[1] 0 0 1 1
PE_x[0] 0 1 0 1
Boost 0 dB 1.9 dB 3.5 dB 4.9 dB
Overshoot 0% 15 % 35 % 60 %
Output A Input C 1:2 DEMUX
Output B Port A Loopback Port B Loopback Port C Loopback
Input A 2:1 MUX Input B
Output C
Rev. PrA | Page 8 of 18
Preliminary Technical Data
Figure 3. Loopback Configurations
AD8153
Table 7. Switching Configurations
LB_A 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 LB_B 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 LB_C 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 SEL 0 0 1 1 0 X 1 0 1 1 0 1 X 0 0 1 0 X 1 0 1 X BICAST 0 1 0 1 0 1 0 X 0 1 X 0 1 0 1 X 0 1 X X X X Output A Input C Input C Idle Input C Input C Input C Idle Input C Idle Input C Input C Idle Input C Input A Input A Input A Input A Input A Input A Input A Input A Input A Output B Idle Input C Input C Input C Idle Input C Input C Input B Input B Input B Input B Input B Input B Idle Input C Input C Idle Input C Input C Input B Input B Input B Output C Input A Input A Input B Input B Input C Input C Input C Input A Input B Input B Input C Input C Input C Input A Input A Input B Input C Input C Input C Input A Input B Input C
Rev. PrA | Page 9 of 18
AD8153 SERIAL CONTROL INTERFACE
REGISTER SET
The AD8153 can be controlled in one of three modes: pin mode, serial mode, and mixed mode. In pin mode, the AD8153 control is derived from the package pins, whereas in serial mode a set of internal registers controls the AD8153. There is also a mixed mode where switching is controlled via external pins and equalization and pre-emphasis are controlled via the internal registers. The method for writing data to and reading data from the AD8153 are described in sections 0 to 0. The mode is controlled via the MODE pin. To set the part in pin mode, MODE should be driven low to VEE. When MODE is driven high to VCC, the part is set to serial or mixed mode. In pin mode, all controls are derived from the external pins. In serial mode, each channel's equalization and pre-emphasis are solely controlled through the registers as described in Table 8. Additionally, further functionality is available in serial mode as each channel's output can be enabled/disabled with the Output
Preliminary Technical Data
Enable control bits, which is not possible in pin mode. In order to change the switching in the AD8153 in serial mode, the mask bits (register 0x00) must be set to 1 by writing the value 0x1F to this register as explained in the following sections. Once all the mask bits are set to 1, switching is controlled via the LB A, LB B, LB C, BICAST and SEL bits in the register set. In mixed mode, each channel's equalization and pre-emphasis are controlled through the registers as described above. The switching, however, can be controlled using either the external pins or the internal register set. The source of the control is selected using the mask bits (0x00). If a mask bit is set to 0, the external pin acts as the source for that specific control. If a mask bit is set to 1, the associated internal register acts as the source for that specific control. As an example, if one were to set register 0x00 to the value 0x0C, the SEL and LB C controls would come from the internal register set (bit 0 of register 0x04 and bit 3 of register 0x03 respectively), and BICAST, LB A and LB B controls would come from the external pins.
Table 8: Register Map
Address
00000000 (0x00) 00000001 (0x01) 00000010 (0x02) 00000011 (0x03) 0000100
Bit 7
Bit 6
Bit 5
Bit 4
BICAST MASK
Bit 3
SEL MASK
Bit 2
LB_C MASK
Bit 1
LB_B MASK
Bit 0
LB_A MASK
Default
00000000 (0x00) 00010000
OUTPUT ENABLE A
LB A
EQ A
PE A [1]
PE A [0] (0x10) 00010000
OUTPUT ENABLE B
LB B
EQ B
PE B [1]
PE B [0] (0x10) 00010000 (0x10) 00000000
OUTPUT ENABLE C
LB C
EQ C
PE C [1]
PE C [0]
BICAST
SEL (0x00)
(0x04)
GENERAL FUNCTIONALITY
The AD8153 register set is controlled through a two-wire I2C interface. The AD8153 acts only as an I2C slave device. Therefore, the I2C bus in the system needs to include an I2C master in order to configure the AD8153 and other I2C devices that may be on the bus. Data transfers are controlled through the use of the two I2C wires: the SCL input clock pin and the SDA bi-directional data pin. In order to set the AD8153 part in I2C Mode the MODE input needs to be set high to VCC.
The AD8153 I2C interface can be run in the standard (100 kHz) and fast (400 kHz) modes. The SDA line only changes value when the SCL pin is low with two exceptions. In order to indicate the beginning or continuation of a transfer, the SDA pin is driven low while the SCL pin is high, and in order to indicate the end of a transfer, the SDA line is driven high while the SCL line is high. Therefore, it is important to control the SCL clock to only toggle when the SDA line is stable unless indicating a start, repeated start or stop condition.
Rev. PrA | Page 10 of 18
Preliminary Technical Data
I2C DATA WRITE
In order to write data to the AD8153 register set, a microcontroller, or any other I2C master, needs to send the appropriate control signals to the AD8153 slave device. The steps that need to be followed are listed below, where the signals are controlled by the I2C master unless otherwise specified. A diagram of the procedure can be seen in Figure 4.
AD8153
continue with step 2 in this procedure to perform another write. 9c. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with step 2 of the read procedure (in the next section) to perform a read from a another address. 9d. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with step 8 of the read procedure (in the next section) to perform a read from the same address set in step 5.
1. Send a start condition (while holding the SCL line high, pull the SDA line low) 2. Send the AD8153 part address (7 bits) whose upper 4 bits are the static value b1001 and whose lower 3 bits are controlled by the input pins I2C_ADDR[2:0]. This transfer should be MSB first. 3. Send the write indicator bit (0). 4. Wait for the AD8153 to acknowledge the request. 5. Send the register address (8 bits) to which data is to be written. This transfer should be MSB first. 6. Wait for the AD8153 to acknowledge the request. 7. Send the data (8 bits) to be written to the register whose address was set in step 5. This transfer should be MSB first. 8. Wait for the AD8153 to acknowledge the request. 9a. Send a stop condition (while holding the SCL line high, pull the SDA line high) and release control of the bus. 9b. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and
In Figure 4, the AD8153 write process is shown. The SCL signal is shown along with a general write operation and a specific example. In the example, data 0x92 is written to address 0x6D of an AD8153 part with a part address of 0x4B. The part address is 7 bits wide and is composed of the AD8153 static upper 4 bits (b1001) and the pin programmable lower 3 bits (I2C_ADDR[2:0]). In this example, the I2C_ADDR bits are set to b011. In the figure, the corresponding step number is visible in the circle under the waveform. The SCL line is driven by the I2C master and never by the AD8153 slave. As for the SDA line, the data in the shaded polygons is driven by the AD8153, whereas the data in the non-shaded polygons is driven by the I2C master. The end phase case shown is that of 9a.
It is important to note that the SDA line only changes when the SCL line is low, except for the case of sending a start, stop, or repeated start condition, steps 1 and 9 in this case.
SCL General Case SDA Example SDA
1 2 2 3 4
2
START
FIXED PART ADDR
ADDR [2:0]
RW ACK
REGISTER ADDR
ACK
DATA
ACK
STOP
5
6
7
8
9a
Figure 4: I C Write Diagram
I2C DATA READ
To read data from the AD8153 register set, a microcontroller, or any other I2C master, needs to send the appropriate control signals to the AD8153 slave device. The steps that need to be followed are listed below, where the signals are controlled by the I2C master unless otherwise specified. A diagram of the procedure can be seen in Figure 5.
1. Send a start condition (while holding the SCL line high, pull the SDA line low). 2. Send the AD8153 part address (7 bits) whose upper 4 bits are the static value b1001 and whose lower 3 bits are controlled by the input pins I2C_ADDR[2:0]. This transfer should be MSB first. 3. Send the write indicator bit (0). 4. Wait for the AD8153 to acknowledge the request.
Rev. PrA | Page 11 of 18
AD8153
5. Send the register address (8 bits) from which data is to be read. This transfer should be MSB first. The register address will be kept in memory in the AD8153 until the part is reset or the register address is written over with the same procedure (steps 1-6). 6. Wait for the AD8153 to acknowledge the request. 7. Send a repeated start condition (while holding the SCL line high, pull the SDA line low). 8. Send the AD8153 part address (7 bits) whose upper 4 bits are the static value b1001 and whose lower 3 bits are controlled by the input pins I2C_ADDR[1:0]. This transfer should be MSB first. 9. Send the read indicator bit (1). 10. Wait for the AD8153 to acknowledge the request. 11. The AD8153 will then serially transfer the data (8 bits) held in the register indicated by the address set in step 5. 12. Acknowledge the data. 13a. Send a stop condition (while holding the SCL line high, pull the SDA line high) and release control of the bus. 13b. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with step 2 of the write procedure (previous section) to perform a write. 13c. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with step 2 of this procedure to perform a read from a another address.
Preliminary Technical Data
13d. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with step 8 of this procedure to perform a read from the same address.
In Figure 5, the AD8153 read process is shown. The SCL signal is shown along with a general read operation and a specific example. In the example, data 0x49 is read from address 0x6D of an AD8153 part with a part address of 0x4B. The part address is 7 bits wide and is composed of the AD8153 static upper 4 bits (b1001) and the pin programmable lower 3 bits (I2C_ADDR[2:0]). In this example, the I2C_ADDR bits are set to b011. In the figure, the corresponding step number is visible in the circle under the waveform. The SCL line is driven by the I2C master and never by the AD8153 slave. As for the SDA line, the data in the shaded polygons is driven by the AD8153, whereas the data in the non-shaded polygons is driven by the I2C master. The end phase case shown is that of 13a.
It is important to note that the SDA line only changes when the SCL line is low, except for the case of sending a start, stop, or repeated start condition, as in steps 1, 7, and 13. In Figure 5, A is the same as ACK in Figure 4. Equally, Sr represents a repeated start where the SDA line is brought high before SCL is raised. SDA is then dropped while SCL is still high.
SCL General Case SDA START Example SDA
1 2 2 3 4 5 6 7 8 8 9 10 11 12 13a
FIXED PART ADDR
ADDR [2:0]
RA W
REGISTER ADDR
A Sr
FIXED PART ADDR
ADDR [2:0]
RA W
DATA
A
STOP
Figure 5: I2C Read Diagram
I2C TIMING SPECIFICATIONS
Rev. PrA | Page 12 of 18
Preliminary Technical Data
AD8153
Figure 6: I2C Timing Diagram
Table 9: I2C Timing Parameters
Parameter SCL clock frequency Hold time for a start condition Set-up time for a repeated start condition LOW period of the SCL clock HIGH period of the SCL clock Data hold time Data set-up time Rise time for both SDA and SCL Fall time for both SDA and SCL Set-up time for stop condition Bus free time between a stop and a start condition Capacitance for each I/O pin
Symbol fSCL tHD;STA tSU;STA tLOW tHIGH tHD;DAT tSU;DAT tr tf tSU;STO tBUF Ci
Min 0 0.6 0.6 1.3 0.6 0 10 1 1 0.6 1 5
Max 400+ 300 300 7
Unit kHz s s s s s Ns Ns Ns s Ns Pf
Rev. PrA | Page 13 of 18
AD8153 APPLICATIONS
The main application of the AD8153 is to support redundancy on both the backplane side and the line interface side of a serial link. Figure 7 illustrates redundancy in a typical backplane system. Each line card is connected to two switch fabrics (primary and redundant). The device can be configured to support either 1 + 1 or 1:1 redundancy.
Preliminary Technical Data
Another application for the AD8153 is in test equipment for evaluating high speed serial links. Figure 9 illustrates a possible application of the AD8153 in a simple link tester.
Physical Interface
Digital Engine
AD8153
Primary Switch Fabric
Line Cards
Redundant Switch Fabric
Physical Interface
Digital Engine Fabric cards
AD8153
Backplane
Figure 7. Switch Redundancy Application
SFP SFP
CDR CDR
AD8153
Processing Engine/ Crossbar /Backplane
Figure 8. Line Interface Redundancy Application
Rev. PrA | Page 14 of 18
Preliminary Technical Data
DUT
Connector
AD8153
Connector
AD8153
Protocol Analyzer
FPGA
Figure 9. Test Equipment Application
Rev. PrA | Page 15 of 18
AD8153 OUTLINE DIMENSIONS
Notes The 8153 has a conductive heat slug to help dissipate heat and ensure reliable operation of the device over the full industrial temperature range. The slug is exposed on the bottom of the package and is electrically connected to VEE. It is recommended that no PCB signal traces or vias be located under the package that could come into contact with the slug.
Figure 10. 32-Lead QFN, Exposed Paddle Dimensions shown in millimeters
Rev. PrA | Page 16 of 18
Preliminary Technical Data
NOTES
AD8153
Rev. PrA | Page 17 of 18
AD8153 NOTES
Preliminary Technical Data
(c) 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06393-0-9/06(PrA)
Rev. PrA | Page 18 of 18

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