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ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module
Features
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6 Low Power Micron 1M X 16 Synchronous Dynamic Random Access Memory Chips in one MCM User Configureable as "2" Independent 512K X 48 X 2 Banks High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface 3.3-V Power Supply (10% Tolerance) Separate Logic and Output Driver Power Pins Two Banks for On-Chip Interleaving (Gapless Accesses) Up to 50-MHz Data Rates CAS Latency (CL) Programmable to 2 Cycles From Column-Address Entry
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Burst Length Programmable to 4 or 8 Pipeline Architecture Cycle-by-Cycle DQ-Bus Write Mask Capability With Upper and Lower Byte Control Chip Select and Clock Enable for Enhanced-System Interfacing Serial Burst Sequence Auto-Refresh 4K Refresh (Total for Both Banks) 200-lead CQFP, cavity-up package
General Description
The ACT-D1M96S device is a high-speed 96Mbit synchronous dynamic random access memory (SDRAM) organized as 2 independent 512K X 48 X 2 banks. All inputs and outputs of the ACT-D1M96S are compatible with the LVTTL interface. All inputs and outputs are synchronized with the CLK input to simplify system design and enhance use with high-speed microprocessors and caches.
BLOCK DIAGRAM
CS1 CLK1 CKE1 DQMU1 DQML1 RAS1 CAS1 WE1 A0-A11 BANK T BANK B
16 16 16
S E C T I O N A
12
1M X 16 or 512K X 16 X 2 Banks
1M X 16 or 512K X 16 X 2 Banks
1M X 16 or 512K X 16 X 2 Banks
DQ0-15 CS2 CLK2 CKE2 DQMU2 DQML2 RAS2 CAS2 WE2 BA0-BA11 BANK T BANK B
16
DQ16-31
DQ32-47
S E C T I O N B
12
1M X 16 or 512K X 16 X 2 Banks
1M X 16 or 512K X 16 X 2 Banks
16
1M X 16 or 512K X 16 X 2 Banks
16
DQ48-63
DQ64-79
DQ80-95
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Operation
All inputs to the ACT-D1M96S SDRAM are latched on the rising edge of the system (synchronous) clock. The outputs, DQ0-DQ95, also are referenced to the rising edge of CLK. The ACT-D1M96S has two banks in each section that are accessed independently. A bank must be activated before it can be accessed (read from or written to). Refresh cycles refresh both banks alternately. Five basic commands or functions control most operations of the ACT-D1M96S: G Bank activate/row-address entry G Column-address entry/write operation G Column-address entry/read operation G Bank deactivate G Auto-refresh Additionally, operations can be controlled by three methods: G Chip select (CS) to select/ deselect the devices G DQMx to enable/mask the DQ signals on a cycle-by-cycle basis G CKE to suspend (or gate) the CLK input The device contains a mode register that must be programmed for proper operation. Table 1 through Table 3 show the various operations that are available on the ACT-D1M96S. These truth tables identify the command and/or operations and their respective mnemonics. Each truth table is followed by a legend that explains the abbreviated symbols. An access operation refers to any read or write command in progress at cycle n. Access operations include the cycle upon which the read or write command is entered and all subsequent cycles through the completion of the access burst.
complete (as determined by the programmed-burst length), the outputs are in the high-impedance state until the next read access is initiated.
Latency
The beginning data-out cycle of a read burst can be programmed to occur two CLK cycles after the read command. The delay between the READ command and the beginning of the output burst is known as CAS latency. After the initial output cycle begins, the data burst occurs at the CLK frequency without any intervening gaps. There is no latency for data-in cycles (write latency). The first data-in cycle of a write burst is entered at the same rising edge of CLK on which the WRT command is entered. The write latency is fixed and is not determined by the mode-register contents.
Two-Bank Operation
The ACT-D1M96S contains two independent banks that can be accessed individually or in an interleaved fashion. Each bank must be activated with a row address before it can be accessed. Each bank then must be deactivated before it can be activated again with a new row address. The bank-activate/row-address-entry command (ACTV) is entered by holding RAS low, CAS high, WE high, and A11 valid on the rising edge of CLK. A bank can be deactivated either automatically during a READ-P or a WRT-P command or by use of the deactivate-bank (DEAC) command. Both banks can be deactivated at once by use of the DCAB command (see Table 1 and the section on bank deactivation).
Two-Bank Row-Access Operation
The two-bank feature allows access of information on random rows at a higher rate of operation than is possible with a standard DRAM, by activating one bank with a row address and, while the data stream is being accessed to/from that bank, activating the second bank with another row address. When the data stream to or from the first bank is complete, the data stream to or from the second bank can begin without interruption. After the second bank is activated, the first bank can be deactivated to allow the entry of a new row address for the next round of accesses. In this manner, operation can continue in an interleaved fashion.
2
Burst Sequence
All data for the ACT-D1M96S is written or read in a burst fashion, that is, a single starting address is entered into the device and then the ACT-D1M96S internally accesses a sequence of locations based on that starting address. After the first access some of the subsequent accesses can be at preceding as well as succeeding column addresses, depending on the starting address entered. This sequence is programmed to follow a serial burst (see Table 4 and 5). The length of the burst can be programmed is 4 or 8. After a read burst is
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Two-Bank Column-Access Operation
The availability of two banks allows the access of data from random starting columns between banks at a higher rate of operation. After activating each bank with a row address (ACTV command), A11 can be used to alternate READ or WRT commands between the banks to provide gapless accesses at the CLK frequency, provided all specified timing requirements are met.
DQ80-87 and DQMU controls DQ8-15, DQ24-31, DQ40-47, DQ56-63, DQ72-79, and DQ88-95. The application of DQMx to a write burst has no latency (nDID = 0 cycle). During a write burst, if DQMx is held high on the rising edge of CLK, the data-input is ignored on that cycle.
CLK-Suspend
For normal device operation, CKE should be held high to enable CLK. If CKE goes low during the execution of a READ (READ-P) or WRT (WRT-P) operation, the DQ bus occurring at the immediate next rising edge of CLK is frozen at its current state, and no further inputs are accepted until CKE returns high. This is known as a CLK-suspend operation, and its execution indicates a HOLD command. The device resumes operation from the point when it was placed in suspension, beginning with the second rising edge of CLK after CKE returns high.
Bank Deactivation (Precharge)
Both banks can be deactivated (placed in precharge) simultaneously by using the DCAB command. A single bank can be deactivated by using the DEAC command. The DEAC command is entered identically to the DCAB command except that A10 must be low and A11 used to select the bank to be precharged as shown in Table 1. A bank can be deactivated automatically by using A10 during a read or write command. If A10 is held high during the entry of a read or write command, the accessed bank (selected by A11) is deactivated automatically upon completion of the access burst. If A10 is held low during the entry of a read or write command, that bank remains active following the burst. The read and write commands with automatic deactivation are signified as READ-P and WRT-P.
Setting the Mode Register
The ACT-D1M96S contains a mode register in each chip that must be programmed with the CAS latency, the burst type, and the burst length. This is accomplished by executing a mode-register set (MRS) command with the information entered on the address lines A0-A9. A logic 0 must be entered on A7 and A8, but A10 and A11 are don't-care entries for the ACT-D1M96S. When A9 = 0, the write-burst length is defined by A0-A2. Figure 1 shows the valid combinations for a successful MRS command. Only valid addresses allow the mode register to be changed. If the addresses are not valid, the previous contents of the mode register remain unaffected. The MRS command is executed by holding RAS, CAS, and WE low and the input mode word valid on A0-A9 on the rising edge of CLK (see Table 1). The MRS command can be executed only when both banks are deactivated.
Chip Select (CS)
CS can be used to select or deselect the ACT-D1M96S for command entry, which might be required for multiple-memory-device decoding. If CS is held high on the rising edge of CLK (DESL command), the device does not respond to RAS, CAS, or WE until the device is selected again by holding CS low on the rising edge of CLK. Any other valid command can be entered simultaneously on the same rising CLK edge of the select operation. The device can be selected/deselected on a cycle-by-cycle basis (see Table 1 and Table 2). The use of CS does not affect an access burst that is in progress; the DESL command can only restrict RAS, CAS, and WE input to the ACT-D1M96S.
Refresh
The ACT-D1M96S must be refreshed at intervals not exceeding tREF (see timing requirements) or data cannot be retained. Refresh can be accomplished by performing a read or write access to every row in both banks or 4096 auto-refresh (REFR) commands. Regardless of the method used, refresh must be accomplished before tREF has expired.
3
Data Mask
The mask command or its opposite, the data-in enable (ENBL) command (see Table 3), is performed on a cycle-by-cycle basis to gate any data cycle within a write burst. DQML controls DQ0-7, DQ16-23, DQ32-39, DQ48-55, DQ64-71,
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Auto Refresh (REFR)
Before performing a REFR, both banks of all 6 chips must be deactivated (placed in precharge). To enter a REFR command, RAS and CAS must be low and WE must be high upon the rising edge of CLK (see Table 1). The refresh address is generated internally such that, after 4096 REFR commands, both banks of all 6 chips of the ACT-D1M96S have been refreshed. The external address and bank select (A11) are ignored. The execution of a REFR command automatically deactivates both banks upon completion of the internal auto-refresh cycle, allowing consecutive REFR-only commands to be executed, if desired, without any intervening DEAC commands. The REFR commands do not necessarily have to be consecutive, but all 4096 must be completed before tREF expires.
Power Up Initialization
Device initialization should be performed after a power up to the full VCC level. After power is established, a 200s interval is required (with no inputs other than CLK). After this interval, both banks of the device must be deactivated. Eight REFR commands must be performed, and the mode register must be set to complete the device initialization.
General Information for AC Timing Measurements
All specifications referring to READ commands are also valid for READ-P commands unless otherwise noted. All specifications referring to WRT commands are also valid for WRT-P commands unless otherwise noted. All specifications referring to consecutive commands are specified as consecutive commands for the same bank unless otherwise noted.
Note: For all pin references in the General Description, both sections apply. For example, A11 signals also apply for BA11 signals.
For additional Detail Information regarding the operation of the individual chip (MT48LC1M16A1) see Micron's 524,288-WORD BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY Datasheet Revision 8/99 or contact the Aeroflex Sales Department.
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A11 BA11
A10 BA10
A9 BA9
A8 BA8
A7 BA7
A6 BA6
A5 BA5
A4 BA4
A3 BA3
A2 BA2
A1 BA1
A0 BA0
Reserved
0
0
0 = Serial
Register Bit A9/ BA9
Register Bits Write Burst Length A6 BA6 A2 - A0 BA2 - BA0 0 A5 BA5 1
A4 CAS Latency
Register Bits A2 BA2 2 0 0 A1 BA1 1 1
A0 Burst Length
BA4 0
BA0 0 1 4 8
0
NOTES: All other combinations are reserved.
Figure 1 - Mode Register Programming
3.3 V
1200 Output 10 pF 870
AC Test Conditions
Parameter Input Pulse Level Input Rise and Fall Input and Output Timing Reference Typical 0.4 - 2.4 5 1.5 Units V ns V
Figure 2 - LVTTL-Load Circuit
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Table 1 -- Basic Command Truth Table
Command State of Bank(s) T = deac B = deac X X SB = deac SB = actv SB = actv SB = actv SB = actv SB = actv X X T = deac B = deac CS1 CS2 RAS1 RAS2 CAS1 CAS2 WE1 WE2 A11
A10 BA10
A9-A0 BA9-BA0 A9,BA9 = V
BA11
Mnemonic
Mode register set
L
L
L
L
X
X
A8,BA8,A7,BA7 = 0 A6-A0,BA6-BA0 = V
MRS
Bank deactivate (precharge) Deactivate all banks (precharge) Bank activate/row-address entry Column-address entry/write operation Column-address entry/write operation with auto-deactivate Column-address entry/read operation Column-address entry/read operation with auto-deactivate Burst stop No operation Control-input inhibit/no operation Auto refresh
L L L L L L L L L H L
L L L H H H H H H X L
H H H L L L L H H X L
L L H L L H H L H X H
BS X BS BS BS BS BS X X X X
L H V L H L H X X X X
X X V V V V V X X X X
DEAC DCAB ACTV WRT WRT-P READ READ-P STOP NOOP DESL REFR
NOTES: For execution of these commands on cycle n: -CKE (n-1) must be high, or -tCES and nCLE must be satisfied for clock-suspend exit. DQMx(n) is a don't care. All other unlisted commands are considered vendor-reserved commands or illegal commands. Auto-refresh entry requires that all banks be deactivated or in an idle state prior to the command entry. Legend: n = CLK cycle number, L = Logic low, H = Logic high, X = Don't care, either logic low or logic high, V = Valid, T = Bank T, B = Bank B, actv = Activated, deac = Deactivated, BS = Logic high to select bank T; logic low to select bank B, SB = Bank selected by A11 at cycle n
Table 2 -- Clock Enable (CKE) Command Truth Table
Command State of Bank(s) T = access operation B = access operation T = access operation B = access operation CKE (n-1) H CKE (n) L CS (n) X RAS (n) X CAS (n) X WE (n) X Mnemonic
CLK suspend on cycle (n + 1)
HOLD
CLK suspend exit on cycle (n + 1)
L
H
X
X
X
X
--
NOTES: For execution of these commands, A0-A11 (n) and DQMx (n) are don't cares. All other unlisted commands are considered vendor-reserved commands or illegal commands. A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write operation. Legend: n = CLK cycle number, L = Logic low, H = Logic high, X = Don't care, either logic low or logic high, T = Bank T, B = Bank B
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Table 3 -- Data-Mask (DQM) Command Truth Table
DQML (n) -- T = deac and B = deac T = actv and -- B = actv (no access operation) Data-in enable T = Write or B = Write T = Write or B = Write T = Write or B = Write L V X N/A X N/A
Command
State of Bank(s)
DQMU
Data In (n)
Data Out (n+2)
Mnemonic
Hi-Z
--
Hi-Z
--
N/A
ENBL
Data-in mask
H
M
N/A
MASK
Data-out enable
L
N/A
V
ENBL
NOTES: For execution of these commands on cycle n: - CKE (n) must be high, or -t CES and n CLE must be satisfied for clock suspend exit. CS(n), RAS(n), CAS(n), WE(n), and A0-A11 are don't cares. All other unlisted commands are considered vendor-reserved commands or illegal commands. DQML controlsDQ0-7, DQ16-23, DQ32-39, DQ48-55, DQ64-71, DQ80-87 and DQMU controls DQ8-15, DQ24-31, DQ40-47, DQ56-63, DQ72-79, and DQ88-95. A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write operation. Legend: n = CLK cycle number, L = Logic low, H = Logic high, X = Don't care, either logic low or logic high, V = Valid, M = Masked input data, N/A = Not applicable, T = Bank T, B = Bank B, actv = Activated, deac = Deactivated, write = Activated and accepting data inputs on cycle n, read = Activated and delivering data outputs on cycle (n + 2)
Table 4 -- Serial 4-Word Burst Sequences
INTERNAL COLUMN ADDRESS A1-A0, BA1-BA0 DECIMAL START 0 1 2 3 2ND 1 2 3 0 3RD 2 3 0 1 4TH 3 0 1 2 START 00 01 10 11 2ND 01 10 11 00 BINARY 3RD 10 11 00 01 4TH 11 00 01 10
Table 5 - Serial 8-Word Burst Sequences
INTERNAL COLUMN ADDRESS A2-A0, BA2-BA0 DECIMAL START 0 1 2 3 4 5 6 7 2ND 1 2 3 4 5 6 7 0 3RD 2 3 4 5 6 7 0 1 4TH 3 4 5 6 7 0 1 2 5TH 4 5 6 7 0 1 2 3 6TH 5 6 7 0 1 2 3 4 7TH 6 7 0 1 2 3 4 5 8TH 7 0 1 2 3 4 5 6 7 START 000 001 010 011 100 101 110 111 2ND 001 010 011 100 101 110 111 000 3RD 010 011 100 101 110 111 000 001 BINARY 4TH 011 100 101 110 111 000 001 010 5TH 100 101 110 111 000 001 010 011 6TH 101 110 111 000 001 010 011 100 7TH 110 111 000 001 010 011 100 101 8TH 111 000 001 010 011 100 101 110
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Absolute Maximum Ratings1 Symbol VCC VCCQ VRANGE TBIAS TSTG ISHORT PW Supply Voltage Supply Voltage range for output drivers Voltage range on any pin with respect to VSS Case Temperature under Bias Storage Temperature Short-Circuit Output Current Power Dissipation
2
Rating
Range -0.5 to 4.6 -0.5 to 4.6 -0.5 to 4.6 -55 to +125 -65 to +150 50 4.2
Units V V V C C mA W
1. Stresses above those listed under "Absolute Maximums Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The temperature rise of jc is negligible due to the low duty cycle during testing.
Recommended Operating Conditions Symbol VCC VCCQ VSS VSSQ VIH VIL TC Supply Voltage Supply Voltage range for output drivers Supply Voltage Supply Voltage range for output drivers Input High Voltage Input Low Voltage 1 Operating Temperature (Case)
2
Parameter
Minimum 3 3
Typical 3.3 3.3 0 0
Maximum 3.6 3.6
Units V V V V
2 -0.3 -55
VCC + 0.3 0.8 +110
V V C
1. VIL Minimum = 1.5Vac (Pulsewidth < 5ns) 2. The temperature rise of jc is negligible due to the low duty cycle during testing.
DC Characteristics (VCC = 3.3V 10%; Tc =-55C to +110C, See Notes 1 & 5) Parameter Output Low Voltage Output High Voltage Input current (Leakage) Output current (Leakage) Precharge standby current in non-power-down mode Symbol VOL VOH II IO ICC2N ICC2NS IOL = 2mA IOH = -2mA 0V < VI < VCC + 0.3V, All other pins = 0V to VCC 0V < VO < VCC + 0.3V, Output disabled CKE > VIH MIN, tCK = 20ns (See note 2) CKE > VIH MIN, CLK < VIL MAX, tCK = (See note 3) 2.4 -10 -10 +10 +10 180 40 Conditions Min Max 0.4 Units V V A A mA mA
1. All specifications apply to the device after power- up initialization. All control and address inputs must be stable and valid. 2. Control, DQ, and address inputs change state only once every 40 ns. 3. Control, DQ, and address inputs do not change (stable). 4. All ICC parameters measured with VCC, not VCCQ. 5. The temperature rise of jc is negligible due to the low duty cycle during testing.
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Capacitance
(f = 1MHz, Tc = 25C)
Symbol Ci(S) Ci(AC) Ci(E) CO
Parameter Input Capacitance, CLK Input Input Capacitance, Address and Control Inputs: A0-A11, CS, DQMx, RAS, CAS, WE Input Capacitance, CKE Input Output Capacitance
Min
Max 50 40 50 20
Units pF pF pF pF
Parameters Guaranteed but not tested
AC Timing (Vcc = 3.3V 0.3V, Tc = -55C to +110C, See Note 4)
Parameter Cycle time, CLK Pulse duration, CLK high Pulse duration, CLK low Access time, CLK high to data out (see Note 1) Hold time, CLK high to data out Setup time, address, control, and data input Hold time, address, control, and data input Delay time, ACTV command to DEAC or DCAB command Delay time, ACTV or REFR to ACTV, MRS or REFR command Delay time ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 2) Delay time, DEAC or DCAB command to ACTV, MRS or REFR command Delay time, ACTV command in one bank to ACTV command in the other bank Delay time, MRS command to ACTV, MRS or REFR command Final data out of READ-P operation to ACTV, MRS or REFR command Final data in of WRT-P operation to ACTV, MRS or REFR command Symbol Test Conditions CAS latency = 2 Min 20 6 6 CAS latency = 2 1 5 3 72 108 30 36 24 30 Min 100000 13 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns
tCK2 tCH tCL tAC2 tOH tIS tIH tRAS tRC tRCD tRP tRRD tRSA
tAPR
t RP - (CL -1) * tCK
ns
(see Note 3)
tAPW
60
ns
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(cont.) AC Timing (Vcc = 3.3V 0.3V, Tc = -55C to +110C, See Note 4)
Parameter Delay time, final data in of WRT operation to DEAC or DCAB command Refresh interval Delay time, CS low or high to input enabled or inhibited Delay time, CKE high or low to CLK enabled or disabled Delay time, final data in of WRT operation to READ, READ-P, WRT, or WRT-P Delay time, ENBL or MASK command to enabled or masked data in Delay time, ENBL or MASK command to enabled or masked data out Delay time, DEAC or DCAB, command to DQ in high-impedance state Delay time, WRT command to first data in Delay time, STOP command to READ or WRT command Symbol Test Conditions Min 20 50 0 1 1 0 2 CAS latency = 2 0 0 2 2 0 2 0 1 Max Units ns ms cycle cycle cycle cycle cycle cycle cycle cycle
tWR tREF
nCDD nCLE nCWL nDID nDOD nHZP2 nWCD
nBSD
See Figure 2 - LVTTL Load Circuit for load circuits. All references are made to the rising transition of CLK, unless otherwise noted. NOTES: 1. tAC is referenced from the rising transition of CLK that is previous to the data-out cycle. For example, the first data out tAC is referenced from the rising transition of CLK within the following cycle: CAS latency minus one cycle after the READ command. An access time is measured at output reference level 1.5 V. 2. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS . 3. CL = CAS Latency. 4. The temperature rise of jc is negligible due to the low duty cycle during testing.
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tCK tCH CLK tCL tT tT
tiS tiH DQ, A0-A11, CS, RAS, CAS, WE, DQMx, CKE tT tiH
tiS, tCESP DQ, A0-A11, CS, RAS, CAS, WE, DQMx, CKE tT
Figure 3 - Input-Attribute Parameters
CAS latency
CLK tAC tLZ tOH DQ tHZ
ACTV Command
READ Command
Figure 4 - Output Parameters
DESL ACTV ACTV, REFR ACTV DEAC, DCAB ACTV MRS
nCDD tRAS tRC tRCD tRP tRRD tRSA
Command Disable DEAC, DCAB ACTV (same bank), MRS, REFR READ, READ-P, WRT, WRT-P ACTV, MRS, REFR ACTV (Different Bank) ACTV, MRS, REFR
Figure 5 - Command-to-Command Parameters
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Package Information - "F20" - CQFP 200 Leads
1.464 (37.186) SQ 1.436 (36.474) SQ
150 151 101 100
.028 (.711) .022 (.559)
.010R MIN .010R MIN .015 (.381) .009 (.229) .130 (3.302) MAX 05 .100 (2.540) .080 (2.032) .035 (.889) .025 (.635) .012 (.304) .009 (.229)
1.230 (31.242) 1.220 (30.988) 49 Spaces at .025 (49 Spaces at .635)
Detail "A"
200 51 1 50
Pin 1 Chamfer
Detail "A"
.1.290 (32.766) SQ REF
.045 (1.143) REF
.115 (2.921) MAX
.008 (.202) .005 (.127)
1.664 (42.266) 1.596 (40.538)
.066 (1.676) .054 (1.372)
Note: 1. All Dimensions in inches (Millimeters) MAX or Typical where noted. MIN
Pin Nomenclature
A0-A10 BA0-BA10 Address Inputs A0-A10, BA0-BA10 Row Addresses A0-A7, BA0-BA7 Column Addresses A10, BA10 Automatic-Precharge Select Bank Select Column-Address Strobe Clock Enable System Clock Chip Select SDRAM Data Input/Output DQML1,2 DQMU1,2 Data/Input Mask Enables
A11,BA11 CAS1,CAS2 CKE1,CKE2 CLK1,CLK2 CS1,CS2 DQ0-DQ95
RAS1,RAS2 VCC VCCQ VSS VSSQ WE1,WE2
Row-Address Strobe Power Supply Power Supply for Output Drivers Ground Ground for Output Drivers Write Enable
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ACT-D1M96S CQFP Pinouts - "F20" PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 FUNCTION DQ2 DQ3 VSSQ DQ4 DQ5 VCCQ DQ6 DQ7 VSSQ DQML1 WE1 VSSQ CAS1 RAS1 VCC CS1 A11 VSS A10 A0 VSSQ A1 A2 VCCQ A3 BA4 VCCQ BA5 BA6 VSSQ BA7 BA8 VSS BA9 DQMU2 VCC DQ88 DQ89 VSSQ DQ90 PIN # 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 FUNCTION DQ91 VSSQ DQ92 DQ93 VCCQ DQ94 DQ95 VSSQ DQ87 DQ86 DQ85 DQ84 VSSQ DQ83 DQ82 VCCQ DQ81 DQ80 VSSQ DQ79 DQ78 VSSQ DQ77 DQ76 VCC DQ75 DQ74 VSS DQ73 DQ72 VSSQ CLK2 CKE2 VCCQ DQ71 DQ70 VCCQ DQ69 DQ68 VSSQ PIN # 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
13
FUNCTION DQ67 DQ66 VSS DQ65 DQ64 VCC DQ63 DQ62 VSSQ DQ61 DQ60 VSSQ DQ59 DQ58 VCCQ DQ57 DQ56 VSSQ DQ48 DQ49 DQ50 DQ51 VSSQ DQ52 DQ53 VCCQ DQ54 DQ55 VSSQ DQML2 WE2 VSSQ CAS2 RAS2 VCC CS2 BA11 VSS BA10 BA0
PIN # 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
FUNCTION VSSQ BA1 BA2 VCCQ BA3 A4 VCCQ A5 A6 VSSQ A7 A8 VSS A9 DQMU1 VCC DQ40 DQ41 VSSQ DQ42 DQ43 VSSQ DQ44 DQ45 VCCQ DQ46 DQ47 VSSQ DQ39 DQ38 DQ37 DQ36 VSSQ DQ35 DQ34 VCCQ DQ33 DQ32 VSSQ DQ31
PIN # 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
FUNCTION DQ30 VSSQ DQ29 DQ28 VCC DQ27 DQ26 VSS DQ25 DQ24 VSSQ CLK1 CKE1 VCCQ DQ23 DQ22 VCCQ DQ21 DQ20 VSSQ DQ19 DQ18 VSS DQ17 DQ16 VCC DQ15 DQ14 VSSQ DQ13 DQ12 VSSQ DQ11 DQ10 VCCQ DQ9 DQ8 VSSQ DQ0 DQ1
Aeroflex Circuit Technology
SCD3369-1 REV C 5/31/00 Plainview NY (516) 694-6700
CIRCUIT TECHNOLOGY
Sample Ordering Information
Part Number ACT-D1M96S-020F20C ACT-D1M96S-020F20T ACT-D1M96S-020F20M Screening Commercial Temperature Extended Temperature Extended Temperature Screening Speed 20 ns 20 ns 20 ns Package 200 Lead CQFP 200 Lead CQFP 200 Lead CQFP
Part Number Breakdown
ACT- D 1M 96 S - 020 F20 M
Aeroflex Circuit Technology Memory Type D = DRAM Memory Depth, Locations Screening C = Commercial Temp, 0C to +70C I = Industrial Temp, -40C to +85C T = Extended Temp, -55C to +110C M = Extended Temp, -55C to +110C, Screened * Q = MIL-PRF-38534 Compliant/SMD if applicable Package Type & Size Surface Mount Package F20 = 1.45" SQ 200 Lead CQFP
Memory Width, Bits Options S = Syncronous
Memory Speed, ns
* Screened to the individual test methods of MIL-STD-883
Specifications subject to change without notice.
Aeroflex Circuit Technology 35 South Service Road Plainview New York 11803 www.aeroflex.com/act1.htm
Aeroflex Circuit Technology
Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: (800) 843-1553 E-Mail: sales-act@aeroflex.com
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SCD3369-1 REV C 5/31/00 Plainview NY (516) 694-6700

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