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| 3D3444 MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D3444) FEATURES * * * * * * * * * * * * Four indep't programmable lines on a single chip All-silicon CMOS technology Low voltage operation (3.3V) Low quiescent current (1mA typical) Leading- and trailing-edge accuracy Vapor phase, IR and wave solderable Auto-insertable (DIP pkg.) Increment range: 2ns through 25ns Delay tolerance: 1ns or 2% (See Table 1) Temperature stability: 2% typical (0C-70C) Vdd stability: 1% typical Minimum input pulse width: 10% of total delay I1 SC I2 I3 I4 SI GND 1 2 3 4 5 6 7 PACKAGES 14 13 12 11 10 9 8 VDD AL O1 SO O2 O3 O4 I1 SC I2 I3 I4 SI GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD AL O1 SO O2 O3 O4 DIP-14 3D3444-xx SOIC-14 3D3444D-xx For mechanical dimensions, click here. For package marking details, click here. FUNCTIONAL DESCRIPTION The 3D3444 device is a small, versatile, quad 4-bit programmable monolithic delay line. Delay values, programmed via the serial interface, can be independently varied over 15 equal steps. The step size (in ns) is determined by the device dash number. Each input is reproduced at the corresponding output without inversion, shifted in time as per user selection. For each line, the delay time is given by: TDn = T0 + An * TI PIN DESCRIPTIONS I1-I4 O1-O4 AL SC SI SO VDD GND Signal Inputs Signal Outputs Address Latch In Serial Clock In Serial Data In Serial Data Out 3.3V Ground where T0 is the inherent delay, An is the delay address of the n-th line and TI is the delay increment (dash number). The desired addresses are shifted into the device via the SC and SI inputs, and the addresses are latched using the AL input. The serial interface can also be used to enable/disable each delay line. The 3D3444 operates at 3.3 volts and has a typical T0 of 9ns. The 3D3444 is CMOS-compatible, capable of sourcing or sinking 4mA loads, and features both rising- and falling-edge accuracy. The device is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 14-pin SOIC. TABLE 1: PART NUMBER SPECIFICATIONS PART NUMBER 3D3444-2 3D3444-4 3D3444-5 3D3444-8 3D3444-10 3D3444-15 3D3444-20 3D3444-25 DELAYS AND TOLERANCES (ns) Delay Increment 2.0 1.50 4.0 2.00 5.0 2.25 8.0 3.00 10 3.00 15 4.00 20 6.00 25 7.00 Total Delay 30.0 1.0 60.0 1.2 75.0 1.5 120 2.4 150 3.0 225 4.5 300 6.0 375 7.5 Inherent Delay 9 2.0 9 2.0 9 2.0 9 2.0 9 2.0 9 2.0 9 2.0 9 2.0 INPUT RESTRICTIONS Max Freq. (MHz) Recommended Absolute 13.8 166 7.57 83.3 6.17 66.6 3.96 41.6 3.20 33.3 2.16 22.2 1.63 16.6 1.31 13.3 Min P.W. (ns) Recommended Absolute 36.0 3.0 66.0 6.0 81.0 7.5 126.0 12.0 156.0 15.0 231.0 22.5 306.0 30.0 381.0 37.5 NOTES: Any increment between 2 and 25 ns not shown is also available as standard Total delay is given by delay at address 15 minus delay at address 0 2002 Data Delay Devices Doc #00119 8/2/02 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 1 3D3444 APPLICATION NOTES THEORY OF OPERATION The quad 4-bit programmable 3D3444 delay line architecture is comprised of a number of delay cells connected in series with their respective outputs multiplexed onto the Delay Out pin (O1O4) by the user-selected programming data. Each delay cell produces at its output a replica of the signal present at its input, shifted in time. Each of the four lines can be controlled independently, via the serial interface. line to its normal operation. The device contains an SO output, which can be used to cascade multiple devices, as shown in Figure 3. TABLE 2: BIT SEQUENCE Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Delay Line 4 3 2 1 1 Function Output Enable Output Enable Output Enable Output Enable Address Bit 3 Address Bit 2 Address Bit 1 Address Bit 0 Address Bit 3 Address Bit 2 Address Bit 1 Address Bit 0 Address Bit 3 Address Bit 2 Address Bit 1 Address Bit 0 Address Bit 3 Address Bit 2 Address Bit 1 Address Bit 0 PROGRAMMED DELAY (ADDRESS) INTERFACE Figure 1 illustrates the main functional blocks of the 3D3444 device. Since the device is a CMOS design, all unused input pins must be returned to well defined logic levels (VDD or GND). The delays are adjusted by first shifting a 20-bit programming word into the device via the SC and SI pins, then strobing the AL signal to latch the values. The bit sequence is shown in Table 2, and the associated timing diagram is shown in Figure 2. Each line has associated with it an enable bit. Setting this bit low will force the corresponding delay line output to a high impedance state, while setting it high returns the 2 3 4 I4 DELAY LINE DELAY LINE DELAY LINE DELAY LINE ADDR4 ADDR3 ADDR2 ADDR1 ENABLES O4 I3 O3 I2 O2 I1 O1 AL SI SC 20-BIT LATCH 20-BIT SHIFT REGISTER Figure 1: Functional block diagram SO Doc #00119 8/2/02 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2 3D3444 PROGRAMMED DELAY (ADDRESS) UPDATE A delay line is a memory device. It stores information present at the input for a time equal to the delay setting before presenting it at the output with minimal distortion. Each 4-bit delay line in the 3D3444 can be represented by 15 serially connected delay elements (individually addressed by the programming data), each capable of storing data for a time equal to the device increment (step time). The delay line memory property, in conjunction with the operational requirement of "instantaneously" connecting the delay element addressed by the programming data to the output, may inject spurious information onto the output data stream. In order to ensure that spurious outputs do not occur, it is essential that the input signal be idle (held high or low) for a short duration prior to updating the programmed delay. This duration is given by the maximum programmable delay. Satisfying this requirement allows the delay line to "clear" itself of spurious edges. When the new address is loaded, the input signal can begin to switch (and the new delay will be valid) after a time given by tPDV or tEDV (see section below). POWER SUPPLY AND TEMPERATURE CONSIDERATIONS The delay of CMOS integrated circuits is strongly dependent on power supply and temperature. The monolithic 3D3444 programmable delay line utilizes novel and innovative compensation circuitry to minimize the delay variations induced by fluctuations in power supply and/or temperature. The thermal coefficient is reduced to 400 PPM/C, which is equivalent to a variation, over the 0C-70 C operating range, of 2% from the room-temperature delay settings. The power supply coefficient is reduced, over the 3.0V3.6V operating range, to 1.5% of the delay settings at the nominal 3.3VDC power supply and/or 2ns, whichever is greater. It is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should be of as low an impedance construction as possible. Power planes are preferred. tLW LATCH (AL) CLOCK (SC) SERIAL INPUT (SI) SERIAL OUTPUT (SO) DELAY TIMES tCW tCW tCSL tDSC NEW BIT 1 tDHC NEW BIT 2 NEW BIT 20 tPCQ OLD BIT 1 OLD BIT 2 OLD BIT 20 NEW BIT 1 tLDX PREVIOUS VALUES tLDV NEW VALUES Figure 2: Serial interface timing diagram 3D3444 SC AL SI SO SI 3D3444 SC AL SO SI 3D3444 SC AL SO FROM WRITING DEVICE TO NEXT DEVICE Figure 3: Cascading Multiple Devices Doc #00119 8/2/02 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 3 3D3444 INPUT SIGNAL CONSIDERATIONS The Frequency and/or Pulse Width (high or low) of operation may adversely impact the specified delay and increment accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Recommended and an Absolute Maximum operating input frequency and a Recommended and an Absolute Minimum operating pulse width have been specified. will increase as the absolute maximum frequency is approached. However, if the input frequency and pulse width remain constant, the device will exhibit the same delays from one period to the next (ie, no appreciable jitter). OPERATING PULSE WIDTH The Absolute Minimum Operating Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest pulse width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. The Minimum Operating Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed. Operation below the recommended minimum pulse width will cause the delays to shift slighty with respect to their values at long-pulse-width operation. The magnitudes of these deviations will increase as the absolute minimum pulse width is approached. However, if the input pulse width and frequency remain constant, the device will exhibit the same delays from one period to the next (ie, no appreciable jitter). OPERATING FREQUENCY The Absolute Maximum Operating Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. The Recommended Maximum Operating Frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed. Operation above the recommended maximum frequency will cause the delays to shift slighty with respect to their values at low-frequency operation. The magnitudes of these deviations Doc #00119 8/2/02 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 4 3D3444 DEVICE SPECIFICATIONS TABLE 3: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN -0.3 -0.3 -10 -55 MAX 7.0 VDD+0.3 10 150 300 UNITS V V mA C C NOTES 25C 10 sec TABLE 4: DC ELECTRICAL CHARACTERISTICS (0C to 70C, 3.0V to 3.6V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current Low Level Output Current Output Rise & Fall Time SYMBOL IDD VIH VIL IIH IIL IOH IOL TR & TF MIN 2.0 -0.1 -0.1 0.0 0.0 -8.0 7.5 2 0.8 0.1 0.1 -6.0 TYP 1.3 MAX 2.0 UNITS mA V V A A mA mA ns NOTES VDD = 3.6V VIH = VDD VIL = 0V VDD = 3.0V VOH = 2.4V VDD = 3.0V VOL = 0.4V CLD = 5 pf 6.0 *IDD(Dynamic) = 4 * CLD * VDD * F where: CLD = Average capacitance load/line (pf) F = Input frequency (GHz) Input Capacitance = 10 pf typical Output Load Capacitance (CLD) = 25 pf max TABLE 5: AC ELECTRICAL CHARACTERISTICS (0C to 70C, 3.0V to 3.6V) PARAMETER Latch Width Data Setup to Clock Data Hold from Clock Clock Width (High or Low) Clock Setup to Latch Clock to Serial Output Latch to Delay Valid Latch to Delay Invalid Input Pulse Width Input Period Input to Output Delay SYMBOL TLW tDSC tDHC tCW tCSL tPCQ tLDV tLDX tWI Period tPLH, tPHL MIN 10 10 1 15 20 TYP MAX UNITS ns ns ns ns ns ns ns ns % of Total Delay % of Total Delay ns NOTES 12 35 5 10 20 20 45 1 1 See Table 1 See Table 1 See Text NOTES: 1 - Refer to PROGRAMMED DELAY (ADDRESS) UPDATE section Doc #00119 8/2/02 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 5 3D3444 SILICON DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: Ambient Temperature: 25oC 3oC Supply Voltage (VDD): 3.3V 0.1V Input Pulse: High = 3.3V 0.1V Low = 0.0V 0.1V Source Impedance: 50 Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.7V ) Pulse Width: PWIN = 1.25 x Total Delay Period: PERIN = 2.5 x Total Delay OUTPUT: Rload: Cload: Threshold: 10K 10% 5pf 10% 1.65V (Rising & Falling) Device Under Test 10K 5pf Digital Scope 470 NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. COMPUTER SYSTEM PRINTER REF PULSE GENERATOR OUT TRIG IN1 DEVICE UNDER IN2 TEST (DUT) IN3 IN4 OUT1 OUT2 OUT3 OUT4 IN TRIG DIGITAL SCOPE/ TIME INTERVAL COUNTER Figure 4: Test Setup PERIN PW IN tRISE INPUT SIGNAL 2.7V 1.65V 0.6V tFALL VIH 2.7V 1.65V 0.6V VIL tPHL tPLH OUTPUT SIGNAL 1.65V VOH 1.65V VOL Figure 5: Timing Diagram Doc #00119 8/2/02 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 6 |
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