Read:

Following are the details: : Start signal SCL SDA High High High Low The Start signal is HIGH to LOW transition on the SDA line when SCL is HIGH. : Write Slave Address: 70h or 72h : Read Slave Address: 71h or 73h : Value of the AL300 register index. : Acknowledge stage The acknowledge-related clock pulse is generated by the host (master). The host releases the SDA line (HIGH) for the AL300 (slave) to
STOP bit [P] SCL SDA Data bit [1] or NA SCL
SDA Data bit [0] or A SCL
SDA START bit [S] SCL
SDA Not significant SCL
AL250-15 I2C drawing
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AL300
pull down the SDA line during the acknowledge clock pulse. : Not Acknowledged stage The acknowledge-related clock pulse is generated by the host (master). The host releases the SDA line (HIGH) during the acknowledge clock pulse, but the AL300 does not pull it down during this stage. : Data byte write to or read from the register index. In read operation, the host must release the SDA line (high) before the first clock pulse is transmitted to the AL300.

: Stop signal SCL SDA High Low High High The Stop signal is LOW to HIGH transition on the SDA line when SCL is HIGH. Suppose data F0h is to be written to register 0Fh using write slave address 70h, the timing is as follows:
Start Slave addr = 70h Ack Index = 0Fh Ack Data = F0h Ack Stop
SDA SCL
AL300-13 I2C Write timing
Suppose data is to be read from register 55h using read slave address 71h, the timing is as follows:
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29
AL300 Start Ack Stop Read slave addr = 71h NAck Start Ack Data read cycle Stop
Slave addr = 70h
Index = 55h
Ack
SDA SCL
AL300-14 I2C Read timing
More information on the AL300 functionality can be found in the Register Definition section.
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AL300
7.0 Electrical Characteristics
7.1 Recommended Operating Conditions
Parameter VDD TAMB Supply Voltage Ambient Operating Temperature Min +3.0 0 Max +4.0 +70 Unit V C
7.2 Characteristics
Parameter IDD P VIH VIL VOH VOL IO Supply current Power consumption Hi-level input voltage Lo-level input voltage Hi-level output voltage Lo-level output voltage Output current, data Output current, bus driver ILI Ci CK2 tiS tiH tr tf CL toH tPD Input leakage current Input pin capacitance Duty factor (tCK2H/tCK2) Input data set-up time Input data hold time Input rise time Input fall time Digital output load cap. Output hold time Propagation delay CL = 15pF CL = 40pF Vi = 0.6 to 2.6V Vi = 2.6 to 0.6V -0.5VNovember 28, 2001
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AL300
7.3 Timing Diagram
tCK
TVCLK/ GCLK R/YIN[7:0] G/UVIN[7:0] BIN[7:0]
tCKH
tCKL tiS
tiH
AL300 Input timing
tCK2
tr
tf
SCLK RA[7:0] GA[7:0] BA[7:0]
tCK2H tCK2L tPD
toH
AL300 Single pixel output timing
SCLK
PCLKA
PCLKB RA[7:0] GA[7:0] BA[7:0]
AL300 Dual pixel output timing
tPD toH
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AL300
8.0 AL300 Register Definition
Following is the summary of the AL300 control registers:
Register Configuration COMPANYID REVISION BOARDCONFIG GENERAL FAMILY POLARITY DITHER ADJUSTMENT PLLDIV PLLREFDIV HRATIO VRATIO HINITPHASE VINITPHASEODD VINITPHASE GOUT Input Timing CAPHSTART CAPHEND RESETTEST CAPVSTART CAPVEND FRAMEVSTART R/W R/W R/W R/W R/W R/W 20h, 21h 22h 23h 24h, 25h 26h, 27h 28h, 29h Horizontal capture start position Horizontal capture size Testing Vertical capture start position Vertical capture end position Display vertical counter start position relative to input vertical counter R R R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00h 01h 02h 03h 04h 05h 06h 07h 10h, 11h 12h, 13h 14h, 15h 16h, 17h 18h 19h 1Ah 1Bh Company ID (46h) Revision number Board configuration General control Chip family number Polarity control Dither control Adjustment control PLL divider number Display PLL reference input divider number Horizontal scale ratio Vertical scale ratio Horizontal zoom scaler initial phase Vertical zoom scalar initial phase in odd field of interlaced input Vertical zoom scalar initial phase Panel Power Control R/W Address Function
Output Clock PLL and Zoom Ratio
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AL300
Output Timing DSPHTOTAL DSPHSEND DSPHDESTART DSPHDEEND DSPVSEND BLINKCTRL DSPVDESTART DSPVDEEND FRAMEDELAY R/W R/W R/W R/W R/W R/W R/W R/W R/W 30h, 31h 32h 33h 34h 35h 36h 37h, 38h 39h, 3Ah 3Bh 3Ch Display horizontal total Output display horizontal sync end position Output horizontal display start Output horizontal display end Output display vertical sync end position OSD blinking control Output vertical display start position Output vertical display end position Output HSYNC delay adjustment relative to input HSYNC FRAMEDELAYODD R/W Interrupt and internal timing IREQSOURCE REFHTOTAL REFVTOTAL Look-up Table RLUTPORT GLUTPORT BLUTPORT LUTWADDR OSD RAM OSDRAMWADDR OSDRAMWPORT HBLANKSTART HBLANKEND VBLANKSTART VBLANKEND INPUTSTATUS LINERATE R/W R/W R/W R/W R/W R/W R R 4Ch, 4Dh 4Eh 50h, 51h 52h, 53h 54h, 55h 56h, 57h 60h 61h, 62h OSD RAM write address OSD RAM write port Horizontal blank start Horizontal blank end Vertical blank start Vertical blank end Input Status Input line rate, which is counted by clock from XIN pin R/W R/W R/W R/W 48h 49h 4Ah 4Bh Red LUT write data port Green LUT write data port Blue LUT write data port Address of LUT wrote port R/W R/W R/W 40h 41h 42h 43h Interrupt Source Horizontal total of internal reference timing Vertical total of internal reference timing Output Control Output HSYNC delay adjustment relative to input HSYNC in odd field
OUTPUTCONTROL R/W
Blanking/Border Control
Input Timing Measurement
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AL300
INVTOTAL IREQSTATUS INHTOTAL Automatic positioning HLINENUMBER
R R R R/W
63h, 64h 65h 66h, 67h 70h 71h 72h, 73h 74h, 75h 79h 7Ah, 7Bh 7Ch, 7Dh 80h 81h 82h 84h 85h 86h 90h 91h 92h 93h, 8Bh 94h, 95h 96h, 97h 98h, 99h 9Ah, 9Bh 9Ch 9Dh AEh 88h 89h
Total vertical line count of input video Interrupt Status Input horizontal pixel total Horizontal line number for horizontal active start and end detection Data threshold value used to determine non-blanking pixel Detected horizontal active start pixel position Detected horizontal active end pixel position Vertical column for vertical active start and end detection Detected vertical active start line Detected vertical active end line OSD(On Screen Display) modes Logic operation Fading alpha value OSD1 Control OSD1 ROM start address OSD1 font address unit On Screen Display horizontal start position On Screen Display vertical start position OSD1 RAM start address OSD1 RAM line stride OSD1 horizontal bitmap size OSD1 bitmap horizontal total OSD1 bitmap vertical size OSD1 bitmap vertical total OSD1 horizontal icon total OSD1 vertical icon total OSD1 font line size OSD2 Control OSD2 ROM start address
DATATHRESHOLD R/W HDESTART HDEEND VCOLUMN VDESTART VDEEND OSD Control OSDMODE FOREOP FADEALPHA OSD 1 OSDCONTROL1 FONTADDRUNIT1 OSDHSTART1 OSDVSTART1 RAMADDRST1 RAMSTRIDE1 BMAPHSIZE1 BMAPHTOTAL1 BMAPVSIZE1 BMAPVTOTAL1 ICONHTOTAL1 ICONVTOTAL1 FONTLINESIZE1 OSD 2 OSDCONTROL2 R/W ROMSTARTADDR2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ROMSTARTADDR1 R/W R/W R/W R/W R R R/W R R
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AL300
FONTADDRUNIT2 OSDHSTART2 OSDVSTART2 RAMADDRST2 RAMSTRIDE2 BMAPHSIZE2 BMAPHTOTAL2 BMAPVSIZE2 BMAPVTOTAL2 ICONHTOTAL2 ICONVTOTAL2 FONTLINESIZE2 OSD Color Registers COLOR0RED COLOR0GREEN COLOR0BLUE COLOR1RED COLOR1GREEN COLOR1BLUE COLOR2RED COLOR2GREEN COLOR2BLUE COLOR3RED COLOR3GREEN COLOR3BLUE
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
8Ah A0h A1h A2h A3h, 8Ch A4h, A5h A6h, A7h A8h, A9h AAh,ABh ACh ADh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh
OSD2 font address unit On Screen Display horizontal start position On Screen Display vertical start position OSD2 RAM start address OSD2 RAM line stride OSD2 horizontal bitmap size OSD2 bitmap horizontal total OSD2 bitmap vertical size OSD2 bitmap vertical total OSD2 horizontal icon total OSD2 vertical icon total OSD2 font line size Color 0 Red Component Color 0 Green Component Color 0 Blue Component Color 1 Red Component Color 1 Green Component Color 1 Blue Component Color 2 Red Component Color 2 Green Component Color 2 Blue Component Color 3 Red Component Color 3 Green Component Color 3 Blue Component
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AL300
8.1 Register Description
Configuration: 00h: Company ID (R) [COMPANYID] CompanyId <7:0> Company ID (46h) Revision (R) [REVISION] Revision <7:0> Revision number Board Configuration (R only; R/W for bit 0) [BOARDCONFIG] If SoftCinfig (0x03<4>) = 0, this register setting represent board configuration. If SoftCinfig (0x03<4>) = 1, bit 0 (only) is programmable by software. The other bits still represent board configuration. VideoIn <0> 0 Accept graphic input 1 Accept video input I2C <6> 0 Serial I2C input 1 Reserved I2C Addr <7> 0 I2C write address is 70h, read address is 71h. 1 I2C write address is 72h, read address is 73h. General (R/W) [GENERAL] PwrDown <0> 0 Normal operation 1 Power down mode SoftTiming <1> Should always be 1 to enable s/w timing configuration. DisablePll* <2> Should always be 0 to enable internal/external PLL. PllDivHs <3> 0 Use input HSYNC as the display clock PLL input reference to generate output pixel clock. Use registers #10h and 11h to define the PLL divider. 1 Use divided input HSYNC as display clock PLL input reference. It needs to be enabled when required output PLL divider is higher than 2047, but can be used any time when output pixel rate is higher than input pixel rate. The divider ratio is defined by registers #10h ~ #13h. Refer to registers #10h ~ #13h for additional reference. SoftConfig <4> 0 Input video type is defined by external pin VIDEOIN. 1 Input video type is defined by bit 0 of register 02h. Refer to register 02h for additional reference. Bypass <5> Video pass through without scaling. 0 Enable scaling defined in registers 14h, 15h, 16h and 17h 1 Bypass When in Bypass mode, only output timing registers 30h, 31h, 37h, 38h, 39h and 3Ah affect the timing control. The PLL and input timing registers are ignored. Ddr12* <6> Reserved. Should be always 0. RefTiming <7> 0 Normal operation 1 Free running
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01h:
02h:
03h:
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AL300
In free running mode, external input HSYNC and VSYNC are disabled. Nominal input timing is defined by registers 41h and 42h instead. This is useful when external video source is disconnected or unstable. The reference clock is given by XIN pin. Refer to registers 36h, 41h and 42h for additional reference. 04h: Chip Family (R) [FAMILY] Family <7:0> 00110000, AL300 series Polarity (R/W) [POLARITY] InvPllRef <0> 0 Display clock PLL reference signal is of negative polarity 1 Display clock PLL reference signal is of positive polarity InvPllFb <1> 0 Display clock PLL feedback signal is of negative polarity 1 Display clock PLL feedback signal is of positive polarity HsPol <2> 0 Output HSYNC is of positive polarity 1 Output HSYNC is of negative polarity BlnkPol <3> 0 Output display enable PDSPEN is of positive polarity 1 Output display enable PDSPEN is of negative polarity VsPol <4> 0 Output VSYNC is positive polarity 1 Output VSYNC is negative polarity ABDelay <5> Delay A data so that A and B data outputs are of the same timing. Usually written as 1 for dual pixel panels. NC for single pixel panels. Please also program registers #07h and #43h accordingly for dual pixel panels. CsyncOut <6> 0 Normal HSYNC output 1 Send composite sync output from PHS pin InvOddFiled <7> For CCIR601 or square pixel video input, this bit should be written as 1 for correct interlaced odd/even field detection. In case of error, rewrite this bit as 0.
05h:
06h:
Dither control (R/W) [DITHER] Sharpness <1:0> Sharpness control 00 turn off sharpness control 01 sharpness level 1 10 sharpness level 2 (sharper than level 1) 11 sharpness level 3 (sharpest) Reserved <2> Reserved <3> Should be always 1 for optimized output. DithMode <5:4> Dither mode select 00 RGB 888 01 RGB 666 10 RGB 444 11 RGB 444 without dithering. It is recommended not to use dithering for graphics input for best sharpness. SoftTVRef <6> 0 YUV video horizontal capture start is defined by the hardware TVREF pin
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AL300
1
Interpolation
<7>
YUV Video horizontal capture start is defined by register #20h and #21h. Note that when #20h values changes between odd and even, the output U/V may flip. #20h should stay either odd or even at all times to ensure correct U/V. When SoftTVRef is 0, register#20h<0> will be used as U/V Flip The counterpart for controlling graphic reference is defined by SoftGraRef (register #80h<6>) 0 turn on interpolation 1 turn off interpolation (duplicate pixels only)
07h:
Adjustment (R/W) [ADJUSTMENT] Reserved <7> HDEDelay <6:4> PDSPEN delay relative to output data phase Reserved <3:0> Optimized value is 00h for single pixel mode, 20h for dual pixel mode Please also program registers #05h<5>, #43h<7>, and #43h<4> accordingly for dual pixel mode.
Output Clock PLL and Zoom Ratio: The output pixel clock is generated from the input HSYNC (or with input pixel clock) relative to the ratio between the output and input display resolution. The PLL divider (PLLDIV, defined by registers #10h and 11h) has a maximum value of 2047 programmed by an 11-bit word. PLLDIV is defined by the following equation:
Vo
PLLDIV(N) =
Ho Vi Where, Ho is the total number of pixels per output line Vo is the output active lines per frame Vi is the input active lines per frame
For the best scaling quality, PLLREFDIV (defined by registers #12h and #13h) is used as a PLL reference divider. In this case, PLLREFDIV (M) should be equal to the total number of pixels per input line (Hi). If N is greater than 2047, both N and M need to be adjusted by dividing the scaling ratio by a simple integer as in the following example: Example: (N greater than 2047)
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AL300
858 240 720 Input Display 768
1200
1024 Output Display
Vo = 768 Vi = 240 Ho = 1200 Therefore, using the equation for PLLDIV, N = 3840 which is much greater than 2047. The scaling ratio is:
N M 3840 858
Since N is greater than 2047, the scaling ratio can be divided by 2 for the best scaling quality. Dividing this ratio by 2, the scaling ratio becomes:
N M 1920 429
These scaled values are ideal for N and M. Note: Ideally, for the PLL, N should be an even integer. 10h: PLL Divider Low (R/W) [PLLDIV] PllDivL <7:0> Bits <7:0> of PLL divider number PLL Divider High (R/W) [PLLDIV] Feb2_d2 <7> Feedback Divider 2 control 0: bypass Feedback Divider 2 1: enable Feedback Divider 2. Output clock frequency is doubled when the Feedback Divider is turned on. Feb1_d2 <6> Feedback Divider 1 control 0: bypass Feedback Divider 1 1: enable Feedback Divider 1. Output clock frequency is doubled when the Feedback Divider is turned on. Out_d2 <5> Output 1-bit Divider control 0: bypass Output Divider 2 1: enable Output Divider 2. Output clock frequency is divided by 2 when the Output Divider is turned on. Pre_d2 <4> Input 1-bit Divider control 0: bypass Input Divider 2
11h:
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AL300
PllDivH (10:8)
<2:0>
1: enable Input Divider 2. Output clock frequency is divided by 2 when the Input Divider is turned on. Bits 8~10 of the PLL divider
The value of PLLDIV is determined by subtracting from the actual target divider by 2 when internal PLL is used. For example, if the desired divider value is 840, then the value set to the related registers should be 838 = 346h. Therefore, PllDivH[2:0] should be set to 3h ("011") and PllDivL[7:0] should be set to 46h ("01000110"). However, when an external genlock PLL such as ICS9173 is used, programming registers 10h and 11h is still needed. In such applications, the PLLDIV should be the actual target divider instead of being subtracted by 2 as in the above case. Please review the AL300Programming algorithm for more details. 12h: PLL Reference Divider Low (R/W) [PLLREFDIV] PllRefDivL <7:0> Bits <7:0> of display PLL reference input divider number (Unit: 1 pixel) PLL Reference Divider High (R/W) [PLLREFDIV] PllRefDivH <2:0> Bits <10:8> of display PLL reference input divider number
13h:
Registers 14h~17h are used to define the independent horizontal and vertical scaling ratio. 14h: Horizontal Zoom Ratio Low (R/W) [HRATIO] HRatioL <7:0> Bits <7:0> of horizontal scale ratio Value valid only when register 03h<5> = 0. Horizontal Zoom Ratio High (R/W) [HRATIO] HRatioH <2:0> Bits <10:8> of horizontal scale ratio Value valid only when register 03h<5> = 0. Horizontal Zoom Ratio = (HDST x 256) / HSRC HSRC = Horizontal source capture size (register 22h) HDST = Horizontal destination active width (registers 33h and 34h) 16h: Vertical Zoom Ratio Low (R/W) [VRATIO] VRatioL <7:0> Bits <7:0> of vertical scale ratio Value valid only when register 03h<5> = 0. Vertical Zoom Ratio High (R/W) [VRATIO] VRatioH <6:0> Bits <14:8> of vertical scale ratio Value valid only when register 03h<5> = 0. Vertical Zoom Ratio = (VDST x 4096) / VSRC
15h:
17h:
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AL300
VSRC = (output vertical active line count x output horizontal line total) / N, or (Voa x Hot) / N. This value should be very close to Vertical source active lines (register 24h, 25h, 26h and 27h), but please keep the decimal. VDST = Vertical destination active lines (registers 37h, 38h, 39h and 3Ah) Note: when vertical zoom ratio is to be changed, input capture timing, PLL divider and M/N values should also be modified. Please refer to the AL300 Programming Algorithm for detailed description. 18h: Horizontal Zoom Initial Phase (R/W) [HINITPHASE] HinitPh <7:0> Horizontal zoom scaler initial phase The purpose of phase adjustment is to optimize the scaling quality when the scaling ratio is a simple fraction such as 2/1 or 3/2. The initial interpolation phase can be 0 up to close to 1 pixel, HinitPh = (1 -Hia/2/Hoa) x 32. Please refer to the AL300 Programming Algorithm for detailed description. The vertical counterpart is defined by register #1Ah Vertical Zoom Initial Phase at Odd Field (R/W) [VINITPHASEODD] VinitPhOdd <7:0> Vertical zoom scalar initial phase for the odd field of interlaced input. Enter the same value as register 1Ah for non-interlaced input. Refer to the AL300 Programming Algorithm for more details.
19h:
1Ah:
Vertical Zoom Initial Phase (R/W) [VINITPHASE] VinitPh <7:0> Vertical zoom scalar initial phase. This is the initial phase for graphics input or even field of interlaced input. The recommended value is 20h. The horizontal zoom initial phase is defined by register #18h Panel Power Control (R/W) [GOUT] ControlEn <0> Enable panel interface control signals Gout3 <1> General purpose register for GOUT3 pin. Gout1 <2> General purpose register for GOUT1 pin. Gout2 <3> General purpose register for GOUT2 pin. The Gout bits are reserved in case additional control pins are required for specific panels. YUV444In <4> 0 YUV422 input 1 YUV444 input (Set <5>=0) CCIR601 <5> 0 CCIR601 input timing format 1 Reserved YUVOut <6> 0 RGB output 1 YUV output YUV444Out <7> 0 YUV422 output 1 YUV444 output Bits<7:4> is valid only if register #02h<0>, VideoIn is 1
1Bh:
Input timing:
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AL300
Please refer to section 6.5 Input Video Timing for additional reference. The input timing diagram (AL30007) shows it pictorially. 20h: Horizontal Capture Start Low (R/W) [CAPHSTART] CapHStartL <7:0> Bits<7:0> of horizontal capture start position (Unit: 1 pixel) Horizontal Capture Start High (R/W) [CAPHSTART] CapHStartH <2:0> Bits <10:8> of horizontal capture start position Horizontal Capture Size (R/W) [CAPHSIZE] CapHSize <7:0> Horizontal capture size (Unit: 8 pixels) Testing (R/W) [RESETTEST] Reserved <7:0> Reserved Vertical Capture Start Low (R/W) [CAPVSTART] CapVStartH <7:0> Bits <7:0> of vertical capture start position (Unit: 1 line) Vertical Capture Start High (R/W) [CAPVSTART] CapVStartL <2:0> Bits <10:8> of vertical capture start position Vertical Capture End Low (R/W) [CAPVEND] CapVEndL <7:0> Bits <7:0> of vertical capture end position (Unit: 1 line) Vertical Capture End High (R/W) [CAPVEND] CapVEndH <2:0> Bits <10:8> of vertical capture end position
21h:
22h:
23h:
24h:
25h:
26h:
27h:
Registers #28h and #29h are used to control the delay of vertical lines between the output and the input. The counterpart for horizontal delay is controlled by the registers #3Bh and #3Ch. 28h: Vertical display Frame Start Position Low (R/W) [FRAMEVSTART] FrameVStartL <7:0> Bits <7:0> of display vertical counter start position relative to input vertical counter. (Unit: 1 line) Vertical display Frame Start Position High (R/W) [FRAMEVSTART] FrameVStartH <2:0> Bits <10:8> of display vertical counter start position relative to input vertical counter.
29h:
Output timing: Please refer to section 6.6 Output Video Timing for additional reference. The output timing diagram (AL300-08) shows it pictorially. 30h: Horizontal Total Low (R/W) [DSPHTOTAL] DspHTotalL <7:0> Bits <7:0> of display horizontal total. (Unit: 1 pixel)
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AL300
31h:
Horizontal Total High (R/W) [DSPHTOTAL] DspHTotalH <2:0> Bits <10:8> of display horizontal total. Horizontal Sync End (R/W) [DSPHSEND] DspHsEnd <7:0> Output display horizontal sync end position (Unit: 8 pixels) Horizontal Display Start (R/W) [DSPHDESTART] DspHdeStart <7:0> Output horizontal display start (Unit: 8 pixels) Horizontal Display End (R/W) [DSPHDEEND] DspHdeEnd <7:0> Output horizontal display end (Unit: 8 pixels) Vertical Sync End (R/W) [DSPVSEND] DspVsEnd <7:0> Output display vertical sync end position (Unit: 8 line) Blink Control (R/W) [BLINKCTRL] BlinkTime <1:0> OSD blinking time constant 00 32 frames of internal reference timing per blink 01 64 frames of internal reference timing per blink 10 128 frames of internal reference timing per blink 11 256 frames of internal reference timing per blink (Refer to registers 41h, 42h, 84h<1> and 88h<1> for additional reference) BlinkType <2> 0 Blinking is defined in BlinkTime 1 No blinking, just reverse the index color Vertical Display Start Low (R/W) [DSPVDESTART] DspVdeStartL <7:0> Bits <7:0> of vertical display start position. (Unit: 1 line) Vertical Display Start High (R/W) [DSPVDESTART] DspVdeStartH <2:0> Bits <10:8> of vertical display start position. Vertical Display End Low (R/W) [DSPVDEEND] DspVdeEndL <7:0> Bits <7:0> of vertical display end position. (Unit: 1 line) Vertical Display End High (R/W) [DSPVDEEND] DspVdeEndH <2:0> Bits <10:8> of vertical display end position.
32h:
33h:
34h:
35h:
36h:
37h:
38h:
39h:
3A:
Registers #3Bh and #3Ch are used to control the delay of horizontal pixels between the output and the input. The counterpart for vertical delay is controlled by the registers #28h and #29h. 3B: Frame Head Delay Adjustment (R/W) [FRAMEDELAY] FrameDly <7:0> Output HSYNC delay adjustment relative to input HSYNC (Unit: 16 pixels) Refer to the AL300 Programming Algorithm for more details.
3C:
Frame Head Delay Adjustment for Odd Field (R/W) [FRAMEDELAYODD]
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AL300
FrameDlyOdd <7:0> Output HSYNC delay adjustment relative to input HSYNC in odd field. (Unit: 16 pixels) For non-interlaced video, FrameDlyOdd has the same value as FrameDly. For interlaced video, FrameDlyOdd is half line more than FrameDly. Refer to the AL300 Programming Algorithm for more details.
Interrupt and internal timing: 40h: Interrupt Source (R/W) [IREQSOURCE] LineRateIreq <0> If 1, enable interrupt if line rate changes VSYNCIreq <1> If 1, enable interrupt if VSYNC comes OddFieldIreq <2> If 1, enable interrupt when odd field of input video comes To check what causes the interruption when more than one Interrupt Source is enabled, read register #65h for the status and then clear it for the next interruption. 41h: Reference H Total (R/W) [REFHTOTAL] RefHTotal <7:0> Horizontal total of internal reference timing (Unit: 8 pixels). Enabled when register 03h<7>=1 Registers #41h and #42h are used to define free running mode when input is disconnected or is undefined. This is especially useful for showing error messages with OSD. Refer to register #42h for examples. Reference V Total (R/W) [REFVTOTAL] RefVTotal <7:0> Vertical total of internal reference timing (Unit: 8 lines) Enabled when register 03h<7>=1 Register 41h and 42h are used to define free running mode when input is disconnected or is undefined. This is especially useful for showing error message with OSD. For instance, a reference clock of 14.31818 MHz is used to generate HSYNC and VSYNC with vertical frame refresh rate of 60Hz, the resulted H-total and V-total would be as follows: PANEL 640x480: 800x600: 1024x768: 1280x1024 H-total (Reg.#41h x 8) 456 376 296 216 V-total (Reg.#42h x 8) 520 632 800 1072
42h:
To correct the H-total if necessary, program the input PLL circuitry to generate correct input pixel clock rate. 43h: Output Control (R/W) [OUTPUTCONTROL] Reserved <2:0> Should be written as 000. NoBlank <3> No blanking, all data pass through; for testing only. DualOut <4> output odd/even pixels for dual pixel panels LutEn <5> Enable LUT
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AL300
ColorOut
Replace the input video with color 3 (refer to registers #B9h, #BAh, and #BBh for additional reference) InvOutClk <7> Invert the phase of SCLK, PCLKA, and PCLKB. This bit is usually 1 for dual pixel panels. Please also program registers #05h and #07h accordingly for dual pixel panels.
<6>
65h:
Interrupt Status (R only) [IREQSTATUS] Please refer to the register 65h description in the Input Timing Measurement section, after register 64h.
Look-up Table: 48h: Red LUT write data port (R/W) [RLUTPORT] RLutPort <7:0> Red LUT write data port Green LUT write data port (R/W) [GLUTPORT] GLutPort <7:0> Green LUT write data port Blue LUT write data port (R/W) [BLUTPORT] BLutPort <7:0> Blue LUT write data port LUT write port address (R/W) [ LUTWADDR] LutWrAddr <7:0> Address of LUT wrote port
49h:
4Ah:
4Bh:
OSD RAM: 4Ch: OSD RAM address Low byte (R/W) [OSDRAMWADDR] OsdRamAddrL <7:0> Bits <7:0> of OSD RAM write address OSD RAM address high byte (R/W) [OSDRAMWADDR ] OsdRamAddrH<1:0> Bits <9:8> of OSD RAM write address OSD RAM write data port (R/W) [OSDRAMWPORT] OsdRamPort <7:0> OSD RAM write port Writing data to this register #4Eh automatically increases the OSD RAM address defined in registers #4Ch and #4Dh.
4Dh:
4Eh:
Blanking/border control: The blanking control is used as output data cropping 50h: Horizontal Blank Start Low (R/W) [HBLANKSTART] HBlankStartL <7:0> Bits <7:0> of Horizontal blank start position + 12. (Unit: 1 pixel)
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AL300
51h:
Horizontal Blank Start High (R/W) [HBLANKSTART] HBlankStartH <2:0> Bits <10:8> of Horizontal blank start position + 12. (Unit: 1 pixel) Horizontal Blank End Low (R/W) [HBLANKEND] HBlankEndL <7:0> Bits <7:0> of Horizontal blank end position + 12. (Unit: 1 pixel) Horizontal Blank End High (R/W) [HBLANKEND] HBlankEndH <2:0> Bits <10:8> of Horizontal blank end position + 12. (Unit: 1 pixel) Vertical Blank Start Low (R/W) [VBLANKSTART] VBlankStartL <7:0> Bits <7:0> of Vertical blank start position. (Unit: 1 line) Vertical Blank Start High (R/W) [VBLANKSTART] VBlankStartH <2:0> Bits <10:8> of Vertical blank start position. (Unit: 1 line) Vertical Blank End Low (R/W) [VBLANKEND] VBlankEndL <7:0> Bits <7:0> of Vertical blank end position. (Unit: 1 line) Vertical Blank End High (R/W) [VBLANKEND] VBlankEndH <2:0> Bits <10:8> of Vertical blank end position. (Unit: 1 line)
52h:
53h:
54h:
55h:
56h:
57h:
Input Timing Measurement: 60h: Input Status (R only) [INPUTSTATUS] InHsPol <0> Input HSYNC Polarity. 0 Active low/ negative polarity 1 Active high/ positive polarity InVsPol <1> Input VSYNC polarity. 0 Active low/ negative polarity 1 Active high/ positive polarity OddFIeld <2> 1, if input is in odd field Reserved <3> InVde <4> 1, if input video is in active region OutVde <5> 1, if output video is in active region RefVs <6> 1, if refence timing is in VSYNC cycle (in free running mode) InVSYNC <7> 1, if input timing is in VYSNC cycle Input Line Rate Low (R only) [LINERATE] LineRateL <7:0> Bits <7:0> of input line rate, which is in terms of how many reference lock cycles per horizontal line. Refresh Rate = (Reference clock frequency) / (LINERATE x INVTOTAL) Reference clock is the clock from XIN pin. LINERATE is the input line rate defined in registers #61h and #62h INVTOTAL is the input vertical total line defined in registers #63h and #64h
61h:
November 28, 2001
47
AL300
62h:
Input Line Rate High (R only) [LINERATE] LineRateH <3:0> Bits <11:8> of input line rate, which is in terms of how many reference lock cycle per horizontal line. Input Vertical Line Total Low (R only) [INVTOTAL] InVTotalL <7:0> Bits <7:0> of total vertical line count of input video Refresh Rate = (Reference clock frequency) / (LINERATE x INVTOTAL) Reference clock is the clock from XIN pin. LINERATE is the input line rate defined in registers #61h and #62h INVTOTAL is the input vertical total line defined in registers #63h and #64h Input Vertical Line Total High (R only) [INVTOTAL] InVTotalH <3:0> Bits <11:8> of total vertical line count of input video Interrupt Status (R only) [IREQSTATUS] NewHSYNCRate<0> 1, if HSYNC line rate of input video changes. Reset by clearing the related bit of register #40h, then enable it if desired. NewVysnc <1> 1, if VSYNC of input video happens. Reset by clearing the related bit of register #40h, then enable it if desired. NewField <2> 1, if odd field of input video comes. Reset by clearing the related bit of register #40h, then enable it if desired. Input Horizontal Pixel Total Low (R only) [INHTOTAL] InHTotalL <7:0> Bits<7:0> of total horizontal pixel count of input video Input Horizontal Pixel Total High (R only) [INHTOTAL] InHTotalH <2:0> Bits<10:8> of total horizontal pixel count of input video The two registers can be used to reconfirm if the input pixel-total number is reasonable or as expected. For instance, an odd number may indicate that the PLL of the preceding ADC may not have worked as how it is programmed.
63h:
64h:
65h:
66h:
67h:
Automatic positioning: 70h: Horizontal Line Number for HDEST & HDEEND detection (R/W) [HLINENUMBER] HLineNumber <7:0> Horizontal line number for horizontal active start and end detection; refer to register #71h for additional reference. (Unit: 8 lines) Data Threshold (R/W) [DATATHRESHOLD] DataThreshold <6:0> Luma (brightness) threshold value. DataThreshold is used to determine whether an input pixel exists for both horizontal and vertical directions. Any pixel luma value less than this value is regarded as blank. LinePosDetect <7> 0 whole frame active data detection. 1 Single line/column active data detection.
71h:
November 28, 2001
48
AL300
When LinePosDetect is 1, the horizontal line used to detect horizontal active start and end is defined in register 70h, and the vertical column used to detect vertical active start and end is defined in register 79h. Values of register #72h~#75h reflect the detected input active pixels start/end positions or the GHREF signal star/end positions, depending on the status of register #82h<7:6>. 72h: Horizontal Active Start Low (R only) [HDESTART] HDEStartL <7:0> Bits <7:0> of detected horizontal active start pixel position. (Unit: 1 pixel) Horizontal Active Start High (R only) [HDESTART] HDEStartH <2:0> Bits <10:8> of detected horizontal active start pixel position. Horizontal Active End Low (R only) [HDEEND] HDEEndL <7:0> Bits <7:0> of detected horizontal active end pixel position (Unit: 1 pixel) Horizontal Active End High (R only) [HDEEND] HDEEndH <2:0> Bits <10:8> of detected horizontal active end pixel position. Vertical Column for VDESTART & VDEEND detection (R/W) [VCOLUMN] VColumn <7:0> Vertical column number for vertical active start and end detection; refer to register #71h for additional reference. (Unit: 8 pixels) Vertical Active Start Low (R only) [VDESTART] VDEStartL <7:0> Bits <7:0> of detected vertical active start line (Unit: 1 line) Vertical Active Start High (R only) [VDESTART] VDEStartH <2:0> Bits <10:8> of detected vertical active start line Vertical Active End Low (R only) [VDEEND] VDEEndL <7:0> Bits <7:0> of detected vertical active end line (Unit: 1 line) Vertical Active End High (R only) [VDEEND] VDEEndH <2:0> Bits <10:8> of detected vertical active end line
73h:
74h:
75h:
79h:
7Ah:
7Bh:
7Ch:
7Dh:
OSD Control: 80h: OSD Modes (R/W) [OSDMODE] RomMode <0> Enable ROM mode 0 Internal RAM mode 1 External ROM mode This bit should be 0 when OSD1 and OSD2 are both disabled. BypassHPos <5> 0 The output horizontal start/end position is defined by register #33h & #34h, which resolution is 8-pixel. 1 the output horizontal start/end position is defined by registers #20h~22h
November 28, 2001
49
AL300
SoftGraRef
<6>
0
Graphic horizontal capture start is defined by the hardware GHREF pin 1 Graphic horizontal capture start is defined by register #20h and #21h. The counterpart for controlling graphic reference is defined by SoftTVRef (register #06h<6>)
81h:
Logic Operation (R/W) [FOREOP] Color0Op <1:0> Logic operation between color 0 and video 00 NOP show only OSD 01 OR video or color 0 10 AND video and color 0 11 XOR video xor color 0 Color1Op <3:2> Logic operation between color 1 and video 00 NOP show only OSD 01 OR video or color 1 10 AND video and color 1 11 XOR video xor color 1 Color2Op <5:4> Logic operation between color 2 and video 00 NOP show only OSD 01 OR video or color 2 10 AND video and color 2 11 XOR video xor color 2 Color3Op <7:6> Logic operation between color 3 and video 00 NOP show only OSD 01 OR video or color 3 10 AND video and color 3 11 XOR video xor color 3 Color 0, 1, 2 and 3 are defined in registers B0h ~ BBh. Fading Alpha Value (R/W) [FADEALPHA] FadeAlpha <5:0> The alpha factor for fading effect ranging from 00h to 20h, i.e., there is 33level of fade-in/fade-out effect. Output = input * alpha + OSD * (1 - (alpha/32)) 000000 - minimum alpha value. Show only OSD. 100000 - maximum alpha value. Show only video GHREFPol <7:6> 00 Auto positioning registers #72h~#75h controlled by hardware internal detection. 01 Reserved 10 Auto positioning registers #72h~#75h controlled by GHREF pin, if GHREF is active high. 11 Auto positioning registers #72h~#75h controlled by GHREF pin, if GHREF is active low.
82h:
On Screen Display 1 Registers: 84h: OSD1 Control (R/W) [OSDCONTROL1] PixDepth1 <0> Number of bits per pixel of On Screen Display (OSD) 1
November 28, 2001
50
AL300
BlinkEn1
HZoom1
VZoom1
Font2Byte1
OsdEn1
0 One bit per pixel 1 Two bits per pixel <1> OSD1 blinking enable, effective only when RomMode = `1'. 0 Disable blinking 1 Enable blinking <3:2> OSD1 horizontal zoom factor 00 OSD pixel H size equals to 1X of video pixel 01 OSD pixel H size equals to 2X of video pixel 10 OSD pixel H size equals to 4X of video pixel 11 OSD pixel H size equals to 8X of video pixel <5:4> OSD1 vertical zoom factor 00 OSD line V size equals to 1X of video line 01 OSD line V size equals to 2X of video line 10 OSD line V size equals to 4X of video line 11 OSD line V size equals to 8X of video line <6> Two-byte font charter code mode, effective only when RomMode = `1' 0 One-byte character code mode 1 Two-byte character code mode Please refer to OSD data addressing in ROM mode diagram (AL300-11) <7> On Screen Display (OSD) 1 enable 0 Disable OSD1; 80h<0> should be 0 when OSD1 and OSD2 are both disabled. 1 Enable OSD1
85h:
OSD1 ROM Start Address (R/W) [ROMSTARTADDR1] RomStAddr1H <7:0> Bits<11:4> of OSD1 ROM start address (Unit: 16 bytes) Bits<3:0> of OSD1 ROM start address is defined in register #86h<3:0> OSD1 ROM start address = RomStAddr1H * 256 + RomStAddr1L * 16 OSD1 Font Address Unit (R/W) [FONTADDRUNIT1] FontAddrUnit1 <7:4> OSD1 font address unit 0000 font address is multiple of 25 bytes 0001 font address is multiple of 26 bytes 0010 font address is multiple of 27 bytes 0011 font address is multiple of 28 bytes 0100 font address is multiple of 29 bytes 0101 font address is multiple of 210 bytes 0110 font address is multiple of 211 bytes 0111 font address is multiple of 212 bytes 1000 font address is multiple of 213 bytes 1001 font address is multiple of 214 bytes 1010 font address is multiple of 215 bytes 1011 font address is multiple of 216 bytes RomStAddr1L <3:0> Bits<3:0> OSD1 ROM start address (Unit: 16 bytes) Font address = (Character Code) * (Font Address Unit) + (OSD1 ROM Start Address) `Character Code' is the data retrieved from internal OSD RAM.
86h:
November 28, 2001
51
AL300
`Font Address Unit' is defined in register #86h. `OSD1 ROM Start Address' is defined in registers #85h and #86h.
90h:
OSD1 Horizontal Start (R/W) [OSDHSTART1] OsdHStart1 <7:0> On Screen Display horizontal start position (Unit: 8 video pixels) Relative to display HSYNC start Please also refer to OSD screen timing diagram (AL300-15) for additional reference. OSD1 Vertical Start (R/W) [OSDVSTART1] OsdVStart1 <7:0> On Screen Display vertical start position (Unit: 8 video lines) Relative to display VSYNC start Please also refer to OSD screen timing diagram (AL300-15) for additional reference. OSD1 RAM Start Address (R/W) [RAMADDRST1] RamAddrSt1 <7:0> OSD1 RAM start address (Unit: 4 or 8 bytes) OSD1 RAM Start Address = 1. Register 92h<7:0> * 4, if register 84h<6> = 0 2. Register 92h<7:0> * 8, if register 84h<6> = 1 AL300 has built in 1K Byte RAM In RAM mode (register 80h<0> = 0): RAM start address defines the start address of stored internal OSD RAM bitmap. In ROM mode (register 80h<0> = 1): RAM start address defines the start address of OSD ROM font character codes retrieved from internal OSD RAM. font address = (Character Code) * (Font Address Unit) + (OSD1 ROM Start Address) `Character Code' is the data retrieved from internal OSD RAM. `Font Address Unit' is defined in register #86h. `OSD1 ROM Start Address' is defined in register #85h. OSD1 RAM Horizontal Stride Low (R/W) [RAMSTRIDE1] RamStride1L <7:0> Bits<7:0> of OSD1 RAM line stride (Unit: 1 bytes) In RAM mode (register 80h<0> = 0): RAM horizontal stride defines the number of bytes occupied in internal OSD RAM for each OSD bitmap line. Total bitmap bytes stored in OSD RAM: `RAM Horizontal Stride' x `Bitmap Vertical Size' (bytes) where `RAM Horizontal Stride' is defined by register #8Bh and #93h. `Bitmap Vertical Size' is defined by register #98h and #99h. In ROM mode (register 80h<0> = 1): RAM horizontal stride defines the total bytes occupied in internal OSD RAM for each OSD text row. Total character code bytes stored in OSD RAM: `RAM Horizontal Stride' x `Icon Vertical Total' (bytes) Total character code bytes retrieved in OSD RAM: `Icon Horizontal Total' x `Icon Vertical Total' x `Character code size' (bytes)
91h:
92h:
93h:
November 28, 2001
52
AL300
Where `RAM Horizontal Stride' is defined in register #8Bh and #93h. `Icon Horizontal Total' is defined in register #9Ch. `Icon Vertical Total' is defined in register #9Dh. `Character Code Size' is defined in register #84h<6>. 8Bh: OSD1 RAM Horizontal Stride High (R/W) [RAMSTRIDE1] RamStride1H <1:0> Bits <9:8> of OSD1 RAM line stride (Unit: 1 bytes) The lower byte is defined by register #93h. OSD1 Bitmap Horizontal Size Low (R/W) [BMAPHSIZE1] BMAPHSIZE1 = Actual Bitmap Horizontal Size - 1 BmapHSize1L <7:0> Bits<7:0> of OSD1 horizontal bitmap size (Unit: 1 OSD pixel) Value of (`Bitmap Horizontal Total' - `Bitmap Horizontal Size') defines the extra gap between each character shown on OSD screen. `Bitmap Horizontal Size' is defined by register #94h and #95h. `Bitmap Horizontal Total' is defined by register #96h and #97h. Please refer to OSD screen timing diagram (AL300-15) for additional reference. OSD1 Bitmap Horizontal Size High (R/W) [BMAPHSIZE1] BMAPHSIZE1 = Actual Bitmap Horizontal Size - 1 BmapHSize1H <1:0> Bits<9:8> of OSD1 bitmap horizontal size The lower byte is defined by register #94h. OSD1 Bitmap Horizontal Total Pixels Low (R/W) [BMAPHTOTAL1] BMAPHTOTAL1 = Actual Bitmap Horizontal total - 1 BmapHTotal1L <7:0> Bits<7:0> of OSD1 bitmap horizontal total (Unit: 1 OSD pixel) Value of (`Bitmap Horizontal Total' - `Bitmap Horizontal Size') defines the extra gap between each character shown on OSD screen. `Bitmap Horizontal Size' is defined by register 94h and 95h. `Bitmap Horizontal Total' is defined by register 96h and 97h. Please refer to OSD screen timing diagram (AL300-15) for additional reference. OSD1 Bitmap Horizontal Total Pixels High (R/W) [BMAPHTOTAL1] BMAPHTOTAL1 = Actual Bitmap Horizontal Total - 1 BmapHTotal1H <1:0> Bits<9:8> of OSD1 bitmap horizontal total The lower byte is defined by register #96h. OSD1 Bitmap Vertical Size Low (R/W) [BMAPVSIZE1] BMAPVSIZE1 = Actual Bitmap Vertical Size - 1 BmapVSize1L <7:0> Bits<7:0> of OSD1 bitmap vertical size (Unit: 1 OSD line) Value of (`Bitmap Vertical Total' - `Bitmap Vertical Size') defines the extra line(s) between each text row shown on OSD screen. `Bitmap Vertical Size' is defined by register #98h and #99h. `Bitmap Vertical Total' is defined by register #9Ah and #9Bh. Please refer to OSD screen timing diagram (AL300-15) for additional reference.
94h:
95h:
96h:
97h:
98h:
November 28, 2001
53
AL300
99h:
OSD1 Bitmap Vertical Size High (R/W) [BMAPVSIZE1] BMAPVSIZE1 = Actual Bitmap Vertical Size - 1 BmapVSize1H <1:0> Bits<9:8> of OSD1 bitmap vertical size The lower byte is defined by register #98h. OSD1 Bitmap Vertical total Lines Low (R/W) [BMAPVTOTAL1] BMAPVTOTAL1 = Actual Bitmap Vertical Total - 1 BmapVTotal1L <7:0> Bits<7:0> of OSD1 bitmap vertical total (Unit: 1 OSD line) Value of (`Bitmap Vertical Total' - `Bitmap Vertical Size') defines the extra line(s) between each text row shown on OSD screen. `Bitmap Vertical Size' is defined by register #98h and #99h. `Bitmap Vertical Total' is defined by register #9Ah and #9Bh. Please refer to OSD screen timing diagram (AL300-15) for additional reference. OSD1 Bitmap Vertical Total Lines High (R/W) [BMAPVTOTAL1] BMAPVTOTAL1 = Actual Bitmap Vertical Total - 1 BmapVTotal1H <1:0> Bits<9:8> of OSD1 bitmap vertical total The lower byte is defined by register #9Ah. OSD1 Icon Horizontal Total (R/W) [ICONHTOTAL1] ICONHTOTAL1 = actual icon horizontal total - 1 IconHtotal1 <7:0> OSD1 horizontal icon total (Unit: 1 icon) Icon Horizontal total defines how many character codes should be retrieved from internal OSD RAM and shown on OSD screen per OSD line. Total character code bytes stored in OSD RAM: `RAM Horizontal Stride' x `Icon Vertical Total' (bytes) Total character code bytes retrieved in OSD RAM: `Icon Horizontal Total' x `Icon Vertical Total' x `Character Code Size' (bytes) Where `RAM Horizontal Stride' is defined by register #8Bh and #93h. `Icon Horizontal Total' is defined by register #9Ch. `Icon Vertical Total' is defined by register #9Dh. `Character Code Size' is defined by register #84h<6>. Please refer to OSD screen timing diagram (AL300-15) for additional reference. OSD1 Icon Vertical Total (R/W) [ICONVTOTAL1] ICONVTOTAL1 = actual vertical icon total - 1 IconVTotal1 <7:0> OSD1 vertical icon total (Unit: 1 icon) Icon vertical total defines how many text rows shown on OSD screen. Total character code bytes stored in OSD RAM: `RAM Horizontal Stride' x `Icon Vertical Total' (bytes) Total character code bytes retrieved in OSD RAM: `Icon Horizontal Total' x `Icon Vertical Total' x `Character code size' (bytes) Where `RAM Horizontal Stride' is defined by register #8Bh and #93h. `Icon Horizontal Total' is defined by register #9Ch.
9Ah:
9Bh:
9Ch:
9Dh:
November 28, 2001
54
AL300
`Icon Vertical Total' is defined by register #9Dh. `Character Code Size' is defined by register #84h<6>. Please refer to OSD screen timing diagram (AL300-15) for additional reference. AEh: OSD1 Font Line Size (R/W) [FONTLINESIZE1] Fontlinesize1 <7:0> memory size of a line of font (Unit: 1 byte) Registers #94h and #95h define the size by bits, but #AEh defines it by bytes.
On Screen Display 2 Registers: 88h: OSD2 Control (R/W) [OSDCONTROL2] PixDepth2 <0> Number of bits per pixel of On Screen Display (OSD) 2 0 One bit per pixel 1 Two bits per pixel BlinkEn2 <1> OSD2 blinking enable, effective only when RomMode = `1'. 0 Disable blinking 1 Enable blinking HZoom2 <3:2> OSD2 horizontal zoom factor 00 OSD pixel H size equals to 1X of video pixel 01 OSD pixel H size equals to 2X of video pixel 10 OSD pixel H size equals to 4X of video pixel 11 OSD pixel H size equals to 8X of video pixel VZoom2 <5:4> OSD2 vertical zoom factor 00 OSD line V size equals to 1X of video line 01 OSD line V size equals to 2X of video line 10 OSD line V size equals to 4X of video line 11 OSD line V size equals to 8X of video line Font2Byte2 <6> Two-byte font charter code mode, effective only when RomMode = `1' 0 One-byte character code mode 1 Two-byte character code mode Please refer OSD data addressing in ROM mode diagram (AL300-11) OsdEn2 <7> On Screen Display (OSD) 2 enable 0 Disable OSD2; 80h<0> should be 0 when OSD1 and OSD2 are both disabled. 1 Enable OSD2 OSD2 ROM Start Address (R/W) [ROMSTARTADDR2] RomStAddr2H <7:0> Bits<11:4> of OSD2 ROM start address (Unit: 16 bytes) Bits<3:0> of OSD2 ROM start address is defined in register #8Ah<3:0> OSD1 ROM start address = RomStAddr1H * 256 + RomStAddr1L * 16 OSD2 Font Address Unit (R/W) [FONTAADDRUNIT2] FontAddrUnit2 <7:4> OSD2 font address unit 0000 font address is multiple of 25 bytes 0001 font address is multiple of 26 bytes
89h:
8Ah:
November 28, 2001
55
AL300
0010 font address is multiple of 27 bytes 0011 font address is multiple of 28 bytes 0100 font address is multiple of 29 bytes 0101 font address is multiple of 210 bytes 0110 font address is multiple of 211 bytes 0111 font address is multiple of 212 bytes 1000 font address is multiple of 213 bytes 1001 font address is multiple of 214 bytes 1010 font address is multiple of 215 bytes 1011 font address is multiple of 216 bytes RomStAddr2L <3:0> Bits<3:0> OSD2 ROM start address (Unit: 16 bytes) Font address = (Character Code) * (Font Address Unit) + (OSD2 ROM Start Address) `Character Code' is the data retrieved from internal OSD RAM. `Font Address Unit' is defined by register #8Ah. `OSD2 ROM Start Address' is defined by register #89h and #8Ah. A0h: OSD2 Horizontal Start (R/W) [OSDHSTART2] OsdHStart2 <7:0> On Screen Display horizontal start position (Unit: 8 video pixels) Relative to display HSYNC start Please refer to OSD screen timing diagram (AL300-15) for additional reference. OSD2 Vertical Start (R/W) [OSDVSTART2] OsdVStart2 <7:0> On Screen Display vertical start position (Unit: 8 video lines) Relative to display VSYNC start Please refer to OSD screen timing diagram (AL300-15) for additional reference. OSD2 RAM Start Address (R/W) [RAMADDRST2] RamAddrSt2 <7:0> OSD2 RAM start address (Unit: 4 or 8 bytes) OSD2 RAM Start Address = 1. Register A2h<7:0> * 4, if register 88h<6> = 0 2. Register A2h<7:0> * 8, if register 88h<6> = 1 AL300 has built in 1K Byte RAM In RAM mode (register 80h<0> = 0): RAM start address defines the start address of stored internal OSD RAM bitmap. In ROM mode (register 80h<0> = 1): RAM start address defines the start address of OSD ROM font character codes retrieved from internal OSD RAM. font address = (Character Code) * (Font Address Unit) + (OSD2 ROM Start Address) Where `Character Code' is the data retrieved from internal OSD RAM. `Font Address Unit' is defined by register #8Ah. `OSD2 ROM Start Address' is defined by register #89h. OSD2 RAM Horizontal Stride Low (R/W) [RAMSTRIDE2] RamStride2L <7:0> Bits<7:0> of OSD2 RAM line stride (Unit: 1 bytes) In RAM mode (register 80h<0> = 0):
A1h:
A2h:
A3h:
November 28, 2001
56
AL300
RAM horizontal stride defines the amount of bytes occupied in internal OSD RAM for each OSD bitmap line. Total bitmap bytes stored in OSD RAM: `RAM Horizontal Stride' x `Bitmap Vertical Size' (bytes) Where `RAM Horizontal Stride' is defined by registers #8Ch and #A3h. `Bitmap Vertical Size' is defined by registers #A8h and #A9h. In ROM mode (register 80h<0> = 1): RAM horizontal stride defines the total bytes occupied in internal OSD RAM for each OSD text row. Total character code bytes stored in OSD RAM: `RAM Horizontal Stride' x `Icon Vertical Total' (bytes) Total character code bytes retrieved in OSD RAM: `Icon Horizontal Total' x `Icon Vertical Total' x `Character code size' (bytes) Where `RAM Horizontal Stride' is defined by register #8Bh and #93h. `Icon Horizontal Total' is defined by register #9Ch. `Icon Vertical Total' is defined by register #9Dh. `Character Code Size' is defined by register #84h<6>. Please refer to OSD screen timing diagram (AL300-15) for additional reference. 8Ch: OSD2 RAM Horizontal Stride High (R/W) [RAMSTRIDE2] RamStride2H <1:0> Bits<9:8> of OSD2 RAM line stride (Unit: 1 bytes) Refer to register #A3h for additional reference. OSD2 Bitmap Horizontal Size Low (R/W) [BMAPHSIZE2] BMAPHSIZE2 = Actual Bitmap Horizontal Size - 1 BmapHSize2L <7:0> Bits<7:0> of OSD2 horizontal bitmap size (Unit: 1 OSD pixel) Value of (`Bitmap Horizontal Total' - `Bitmap Horizontal Size') defines the extra gap between each character shown on OSD screen. `Bitmap Horizontal Size' is defined by registers #A4h and #A5h. `Bitmap Horizontal Total' is defined by registers #A6h and #A7h. Please refer to OSD screen timing diagram (AL300-15) for additional reference. OSD2 Bitmap Horizontal Size High (R/W) [BMAPHSIZE2] BMAPHSIZE2 = Actual Bitmap Horizontal Size - 1 BmapHSize2H <1:0> Bits<9:8> of OSD2 bitmap horizontal size The lower byte is defined by register #A4h. OSD2 Bitmap Horizontal Total Pixels Low (R/W) [BMAPHTOTAL2] BMAPHTOTAL2 = Actual Bitmap Horizontal total - 1 BmapHTotal2L <7:0> Bits<7:0> of OSD2 bitmap horizontal total (Unit: 1 OSD pixel) Value of (`Bitmap Horizontal Total' - `Bitmap Horizontal Size') defines the extra gap between each character shown on OSD screen. `Bitmap Horizontal Size' is defined by registers #A4h and #A5h. `Bitmap Horizontal Total' is defined by registers #A6h and #A7h.
A4h:
A5h:
A6h:
November 28, 2001
57
AL300
Please refer to OSD screen timing diagram (AL300-15) for additional reference. A7h: OSD2 Bitmap Horizontal Total Pixels High (R/W) [BMAPHTOTAL2] BMAPHTOTAL2 = Actual Bitmap Horizontal Total - 1 BmapHTotal2H <1:0> Bits<9:8> of OSD2 bitmap horizontal total The lower byte is defined by register #A6h. OSD2 Bitmap Vertical Size Low (R/W) [BMAPVSIZE2] BMAPVSIZE2 = Actual Bitmap Vertical Size - 1 BmapVSize2L <7:0> Bits<7:0> of OSD1 bitmap vertical size (Unit: 1 OSD line) Value of (`Bitmap Vertical Total' - `Bitmap Vertical Size') defines the extra line(s) between each text row shown on OSD screen. `Bitmap Vertical Size' is defined by registers #A8h and #A9h. `Bitmap Vertical Total' is defined by registers #AAh and #ABh. Please refer to OSD screen timing diagram (AL300-15) for additional reference. OSD2 Bitmap Vertical Size High (R/W) [BMAPVSIZE2] BMAPVSIZE2 = Actual Bitmap Vertical Size - 1 BmapVSize2H <1:0> Bits<9:8> of OSD2 bitmap vertical size The lower byte is defined by register #A8h.
A8h:
A9h:
AAh: OSD2 Bitmap Vertical total Lines Low (R/W) [BMAPVTOTAL2] BMAPVTOTAL2 = Actual Bitmap Vertical Total - 1 BmapVTotal2L <7:0> Bits<7:0> of OSD2 bitmap vertical total (Unit: 1 OSD line) Value of (`Bitmap Vertical Total' - `Bitmap Vertical Size') defines the extra line(s) between each text row shown on OSD screen. `Bitmap Vertical Size' is defined by registers #A8h and #A9h. `Bitmap Vertical Total' is defined by registers #AAh and #ABh. Please refer to OSD screen timing diagram (AL300-15) for additional reference. ABh: OSD2 Bitmap Vertical Total Lines High (R/W) [BMAPVTOTAL2] BMAPVTOTAL2 = Actual Bitmap Vertical Total - 1 BmapVTotal2H <1:0> Bits<9:8> of OSD2 bitmap vertical total The lower byte is defined by register #AAh. ACh: OSD2 Icon Horizontal Total (R/W) [ICONHTOTAL2] ICONHTOTAL2 = actual icon horizontal total - 1 IconHTotal2 <7:0> OSD1 horizontal icon total (Unit: 1 icon) Icon Horizontal total defines how many character codes should be retrieved from internal OSD RAM and shown on OSD screen per OSD line. Total character code bytes stored in OSD RAM: `RAM Horizontal Stride' x `Icon Vertical Total' (bytes) Total character code bytes retrieved in OSD RAM: `Icon Horizontal Total' x `Icon Vertical Total' x `Character code size' (bytes) Where `RAM Horizontal Stride' is defined by registers #8Ch and #A3h. `Icon Horizontal Total' is defined by register #ACh.
November 28, 2001
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AL300
`Icon Vertical Total' is defined by register #ADh. `Character Code Size' is defined by register #88h<6>. Please refer to OSD screen timing diagram (AL300-15) for additional reference. ADh: OSD2 Icon Vertical Total (R/W) [ICONVTOTAL2] ICONVTOTAL2 = actual vertical icon total - 1 IconVTotal2 <7:0> OSD2 vertical icon total (Unit: 1 icon) Icon vertical total defines how many text rows shown on OSD screen. Total character code bytes stored in OSD RAM: `RAM Horizontal Stride' x `Icon Vertical Total' (bytes) Total character code bytes retrieved in OSD RAM: `Icon Horizontal Total' x `Icon Vertical Total' x `Character code size' (bytes) Where `RAM Horizontal Stride' is defined by registers #8Ch and #A3h. `Icon Horizontal Total' is defined by register #ACh. `Icon Vertical Total' is defined by register #ADh. `Character Code Size' is defined by register #88h<6>. Please refer to OSD screen timing diagram (AL300-15) for additional reference. AFh: OSD2 Font Line Size (R/W) [FONTLINESIZE2] Fontlinesize2 <7:0> memory size of a line of font (Unit: 1 byte) Please refer to OSD screen timing diagram (AL300-15) for additional reference. On Screen Display Color Registers: Color 0 is the color of pixel with value: `0' when in 1-bit/2-color mode or "00" when in 2-bit/4-color mode. Color 1 is the color of pixel with value: `1' when in 1-bit/ 2-color mode or "01" when in 2-bit/4-color mode. Color 2 is the color of pixel with value "10" when in 2-bit, 4-color mode. Color 3 is the color of pixel with value "11" when in 2-bit, 4-color mode. B0h: Color 0 Red (R/W) [COLOR0RED] Color0Red <7:0> Color 0 Red Component Color 0 Green (R/W) [COLOR0GREEN] Color0Green <7:0> Color 0 Green Component Color 0 Blue (R/W) [COLOR0BLUE] Color0Blue <7:0> Color 0 Blue Component Color 1 Red (R/W) [COLOR1RED] Color1Red <7:0> Color 1 Red Component Color 1 Green (R/W) [COLOR1GREEN]
B1h:
B2h:
B3h:
B4h:
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AL300
Color1Green B5h:
<7:0> Color 1 Green Component
Color 1 Blue (R/W) [COLOR1BLUE] Color1Blue <7:0> Color 1 Blue Component Color 2 Red (R/W) [COLOR2RED] Color2Red <7:0> Color 2 Red Component Color 2 Green (R/W) [COLOR2GREEN] Color2Green <7:0> Color 2 Green Component Color 2 Blue (R/W) [COLOR2BLUE] Color2Blue <7:0> Color 2 Blue Component Color 3 Red (R/W) [COLOR3RED] Color3Red <7:0> Color 3 Red Component
B6h:
B7h:
B8h:
B9h:
BAh: Color 3 Green (R/W) [COLOR3GREEN] Color3Green <7:0> Color 3 Green Component BBh: Color 3 Blue (R/W) [COLOR3BLUE] Color3Blue <7:0> Color 3 Blue Component
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AL300
8.2 Programming Flowchart
1. Wait until AL300 stablizes by checking if Reg.#00h=46h 2. Set Reg.#40h=07h to force interrupt 3. Initialize Video decoder if necessary
Interrup? (check Reg.#65h or mode change) Yes Disable LCD panel output Set Reg#40h = 00h to clear interrupt
No
Input stable? (check Reg.#61h~64h) Yes Video/Graphic input exists? (check Reg.#61h~64h) Yes
No
No
1. Set reference timing (Reg#03h<7>, 41h & 42h) 2. Set up OSD for warning
Define proper values for input/output timing based on input signals: - Read VTOTAL(Reg.#63h,64h) and LINERATE(Reg.#61h,62h) -Read predefined input/output timing values in EEPROM or do auto-positioning detection(Reg.#70h~7Dh)
- Set input timing registers (Reg.#20h~22h, 24h~29h) - Set output timing registers (Reg.#30h~35h, 37h~3Ah) - Set zooming/phase/delay registers (Reg.#14h~1Ah, 3Bh and 3Ch) - Program ADC or decoder if necessary - Program output PLL (Reg.#10h~13h)
Adjust clock phase of the ADC (AL875) to minimize jitters if necessary
Wait until output display is stable (delay for 100 mS)
Enable LCD panel output Set Reg.#40h = 01h to enable interrupt
AL300-25 Programming Flowchart_ver B
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AL300
9.0 Mechanical Drawing
AL300: 28mm x 28mm 160-pin 0.65-pitch PQFP package
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AL300
10.0 Power Consumption
The AL300 works at single 3.3V power. The following table shows the current consumption of the AL300 (with output buffers to the panel) at different operating frequencies and supply voltages. Output frequency AL300@3.3V AL300@3.3V AL300@3.3V AL300@3.3V Power down 110MHz 70MHz 50MHz 30MHz Current consumption 135 mA (typ.) 95 mA (typ.) 75 mA (typ.) 55 mA (typ.) 5 mA (typ.)
The current consumption may be somewhat higher when the output of the AL300 drives a panel directly. For more information about the AL300 or other AverLogic products, please contact your local authorized representatives, visit our website, or contact us directly.
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CONTACT INFORMATION
AverLogic Technologies, Inc. 6840 Via Del Oro Suite 160 San Jose, CA 95119 USA
Tel Fax E-mail URL
: 1 408 361-0400 : 1 408 361-0404 : sales@averlogic.com : www.averlogic.com