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Preliminary Specification
PE42671 DIE
SP7T UltraCMOSTM 2.75 V Switch 100 - 3000 MHz, +68 dBm IIP3
Figure 1. Functional Diagram
Features
* 2 TX, 2 TRX, 3 RX ports * Three pin CMOS logic control with * *
RX1
RX2
TRX1 (WCDMA, RX)
RX3
*
TX1 (GSM/PCS) TRX2 (WCDMA, RX)
*
CMOS Control/Driver and ESD
V1 V2 V3 TX2 (GSM/PCS)
* * *
integral decoder/driver Exceptional harmonic performance: 2fo = -83 dBc and 3fo = -78 dBc Low TX insertion loss: 0.65 dB at 900 MHz, 0.75 dB at 1900 MHz TX - RX Isolation of 47 dB at 900 MHz, 40 dB at 1900 MHz 1500 V HBM ESD tolerance all ports +68 dBm IIP3 @ 50 -111 dBm IMD3 No blocking capacitors required
Product Description
Figure 2. Die Top View* The PE42671 is a HaRPTM-enhanced SP7T RF Switch developed on the UltraCMOSTM process technology. It addresses the specific design needs of the Quad-Band GSM Handset Antenna Switch Module Market for use in GSM/PCS/EDGE/WCDMA handsets. The switch is comprised of two transmit ports that can be used for GSM/PCS/EDGE, two transmit/receive ports (TRX1 and TRX2) that can be used for either WCDMA or as receive ports, and three symmetric receive ports. Onchip CMOS decode logic facilitates three-pin low voltage CMOS control, while high ESD tolerance of 1500 V at all ports, no blocking capacitor requirements, and on-chip SAW filter over-voltage protection devices make this the ultimate in integration and ruggedness. Peregrine's HaRPTM technology enhancements deliver high linearity and exceptional harmonics performance. It is an innovative feature of the UltraCMOSTM process, providing performance superior to GaAs with the economy and integration of conventional CMOS.
(c)2005-2006 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 4
RX1 GND TRX1
ANT
RX2 GND RX3 GND TRX2
GND
1576 m
ANT GND GND TX2 TX1 GND GND GND VDD V1 GND V2 V3 GND
1156 m
* Dimensions shown are drawn die size.
Document No. 70-0196-03 www.psemi.com Contact sales@psemi.com for full version of datasheet
PE42671
Preliminary Specification
Table 1. Target Electrical Specifications @ 25 C, VDD = 2.75 V
Parameter
TX - ANT (850 / 900) TX - ANT (1800 / 1900) TRX - ANT ( 850 WCDMA ) TRX - ANT ( 2100 WCDMA ) RX - ANT (850 / 900) RX - ANT (1800 / 1900) Port under test in on state (850 / 900) (1800 / 1900 / 2100) TX - RX (850 / 900) TX - RX (1800 / 1900) TX - TX (850 / 900) TX - TX (1800 / 1900) TX - TRX (850 / 900) TX - TRX (1800 / 1900) TRX - RX ( 850 WCDMA) TRX - RX (2100 WCDMA) TX 850 / 900 MHz, +35 dBm output power, 50 TX 1800 / 1900 MHz, +33 dBm output power, 50 TX 850 / 900 MHz, +35 dBm output power, 50 TX 1800 / 1900 MHz, +33 dBm output power, 50 TRX1 / TRX2: Measured at 2.14 GHz at ANT port, input +20 dBm CW signal at 1.95 GHz and -15 dBm CW signal at 1.76 GHz TRX1 / TRX2: Measured at 2.14 GHz at ANT port, input +20 dBm CW signal at 1.95 GHz and -15 dBm CW signal at 1.76 GHz
Condition
Typ
0.65 0.75 0.6 0.75 0.95 1.0 20 15 47 40 33 27 36 29 40 31 -83 -82 -78 -78 -111 +68
Units
dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBc dBc dBc dBc dBm dBm
Insertion loss1
Return Loss
Isolation
2nd Harmonic 3rd Harmonic WCDMA 2100 IMD3 WCDMA 2100 IIP3
Note: 1. Insertion loss specified with optimal impedance matching.
Table 2. Operating Ranges
Parameter
Temperature range VDD Supply Voltage IDD Power Supply Current (VDD = 2.75 V) TX input power2 (VSWR 3:1) 824-915 MHz TX input power2 (VSWR 3:1) 1710-1910 MHz TRX input power (VSWR 3:1) 824 - 2170 MHz RX input power2 (VSWR =1:1) Control Voltage High PIN PIN
Table 3. Absolute Maximum Ratings
Symbol
VDD VI
Symbol Min Typ Max Units
TOP VDD -40 2.65 2.75 +85 2.85 C V
Parameter/Conditions
Power supply voltage Voltage on any input Storage temperature range TX input power (50 ) 3,4 824-915 MHz
Min
-0.3 -0.3 -65
Max
4.0 VDD+ 0.3 +150 +38 +36
Units
V V C
TST
IDD
13
50
A PIN(50 )
+35 +33 +31 dBm
TX input power (50 ) 3,4 1710-1910 MHz TRX input power (50 ) 824 - 2170 MHz RX input power (50 ) 3,4 TX input power (VSWR = (:1)3,4 824-915 MHz
dBm +34 +23 +35 +33 +31 1500 V dBm
+20
dBm
PIN (:1)
TX input power (VSWR = (:1)3,4 1710-1910 MHz TRX input power (VSWR = (:1) 824 - 2170 MHz
VIH
1.4
V VESD
Control Voltage Low
VIL
0.4
V
ESD Voltage (HBM, MIL_STD 883 Method 3015.7)
Note: 2. Assumes RF input period of 4620 s and duty cycle of 50%.
Note: 3. Assumes RF input period of 4620 s and duty cycle of 50%. 4. V DD within operating range specified in Table 2.
Part performance is not guaranteed under these conditions. Exposure to absolute maximum conditions for extended periods of time may adversely affect reliability. Stresses in excess of absolute maximum ratings may cause permanent damage.
(c)2005-2006 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 4 Document No. 70-0196-03 UltraCMOSTM RFIC Solutions Contact sales@psemi.com for full version of datasheet
PE42671
Preliminary Specification
Table 4. Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name ANT RX16 GND5 TRX1
6
Figure 3. Pad Configuration (Top View)
Description
RX1 GND TRX1 ANT
2 3 4 1
RF Common - Antenna Redundant ANT pins for flexible bonding RF I/O - RX1 Ground RF I/O - TRX1 Ground RF Common - Antenna Redundant ANT pins for flexible bonding Ground RF I/O - TX1
5
24 23 22 21 20
RX2 GND RX3 GND TRX2
GND5 ANT GND5 TX1
6
GND ANT GND
5 6 7
PE42671 Die
19 18
GND TX2
TX1 GND
8 9
17
GND
GND
Ground Ground Supply Switch control input, CMOS logic level
GND5 VDD V1 GND V2 V3 GND
5 5
GND
10
11
12
13
14 15
16
V1
GND
V2 V3
Ground Switch control input, CMOS logic level Switch control input, CMOS logic level Ground Ground RF I/O - TX2 Ground RF I/O - TRX2 Ground RF I/O - RX3 Ground RF I/O - RX2
Table 5. Truth Table
Path TX1 - ANT TX2 - ANT TRX1 - ANT TRX2 - ANT RX1 - ANT RX2 - ANT RX3 - ANT V3 0 0 0 1 0 1 1 V2 0 0 1 1 1 0 0 V1 0 1 0 0 1 0 1
GND5 TX2
6
GND5 TRX2
6
GND5 RX3
6
GND5 RX26
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating.
Notes: 5. Bond wires should be physically short and connected to ground plane for best performance. 6. Blocking capacitors needed only when non-zero DC voltage present.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up.
Table 6. Ordering Information
Order Code 42671-90 42671-99 42671-00 Description PE42671-DIE-D PE42671-DIE-400G PE42671-DIE-1H Package Film Frame Waffle Pack Evaluation Kit Shipping Method Wafer (Gross Die / Wafer Quantity) 400 Dice / Waffle Pack 1/ box
Document No. 70-0196-03 www.psemi.com Contact sales@psemi.com for full version of datasheet
(c)2005-2006 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 4
GND
VDD
PE42671
Preliminary Specification
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Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp.
Preliminary Specification
The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice).
(c)2005-2006 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 4
Document No. 70-0196-03 UltraCMOSTM RFIC Solutions Contact sales@psemi.com for full version of datasheet

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