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| CXP921000A CMOS 16-bit Single Chip Microcomputer Description The CXP921000A is a CMOS 16-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP921064A. Piggy/ evaluation type 100 pin PQFP (Ceramic) Features (LQFP supported) (QFP supported) * An efficient instruction set as a controller - Direct addressing, numerous abbreviated forms, multiplication and division instructions * Instruction sets for C Ianguage and RTOS - Highly quadratic instruction system, general-purpose register of eight 16-bit x 16-bank configuration * Minimum instruction cycle time 100ns at 20MHz operation (2.7 to 3.3V) 61s at 32kHz operation (2.2 to 3.3V) * Incorporated EPROM CXP27V1000K * Incorporated RAM capacity 10K bytes * Peripheral functions -- A/D converter 8-bit 12 analog input, 2 channels successive approximation system, automatic scanning function, (Conversion time: 3.4s at 20MHz) -- Serial interface 128 -byte buffer RAM, 3 channels 8-stage FIFO, 1 channel (supports special mode master/slave) -- I2C bus interface 64-byte buffer RAM , 2 channels (supports master/slave and automatic transfer mode) -- Timers 8-bit timer/counter, 2 channels (with timing output) 16-bit timer, 3 channels -- Real-time pulse generator 5-bit output, 1 channel (2-stage FIFO) -- Clock prescaler -- Remote control receive circuit 8-bit pulse measurement counter, 8-stage FIFO * Interruption 30 factors, 30 vectors, multi-interruption and priority selection possible * Standby mode Sleep/stop * Package 100-pin Ceramic PQFP * Mask ROM CXP921064A * FLASH EEPROM incorporated type CXP921F064A Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E99X11-PS CXP921000A Pin Assignment in Piggyback Mode (Top View) 100-pin QFP package PJ7/AN11/KS15 PJ6/AN10/KS14 PJ5/AN9/KS13 PJ4/AN8/KS12 PJ3/AN7/KS11 PJ2/AN6/KS10 PB1/AN21 PB0/AN20 PA2/AN14 PA1/AN13 PA0/AN12 PA7/AN19 PA6/AN18 PA5/AN17 PA4/AN16 PA3/AN15 VDD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC PJ1/AN5/KS9 VSS PB2/AN22 PB3/AN23 PB4/SI3 PB5/SO3 PB6/SCK3 PB7/RMC PC0/SDA0 PC1/SCL0 PC2/SDA1 PC3/SCL1 PC4 PC5 PC6 PC7 VSS PD0/KS0 PD1/KS1 PD2/KS2 PD3/KS3 PD4/KS4 PD5/KS5 PD6/KS6 PD7/KS7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Vss 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD A11 A12 D7 D6 D5 D4 D3 D2 D1 D0 Vss A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 Vss 25 26 27 28 29 30 31 32 33 34 35 36 48 47 46 45 44 43 42 41 40 39 38 37 VDD CE NC D15 D14 D13 D12 D11 D10 D9 D8 Vss 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PJ0/AN4/KS8 AVDD AVREF1 AVREF0 AVss AN3 AN2 AN1 PI7/AN0 PI6/NMI PI5/INT7 PI4/INT6 PI3/INT5 PI2/INT4 PI1/INT3 PI0/INT2 PH7/INT1 PH6/INT0 PH5/XOUT PH4/RTO4 PH3/RTO3 PH2/RTO2 PH1/RTO1 PH0/RTO0 Vss TX TEX VDD PG7/SCK2 PG6/SO2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PG0/CS1 PG1/SI1 PG2/SO1 PG3/SCK1 PG4/CS2 PF5/SCK0 PF2/CS0 PF4/SO0 PF7/TMO Note) 1. NC (Pin 88) must be left open. However, use this pin for FLASH EEPROM incorporated version. 2. Vss (Pins 15, 41, 56 and 90) must be connected to GND. 3. VDD (Pins 44, 53 and 89) must be connected to VDD. 4. A20 to A23 are always high level output. -2- PG5/SI2 PE7 PF0 PF1/EC PF3/SI0 PF6/TO RST XTAL EXTAL VDD VSS CXP921000A Pin Assignment in Evaluator Mode (Top View) 100-pin QFP package PJ7/AN11/KS15 PJ6/AN10/KS14 PJ5/AN9/KS13 PJ4/AN8/KS12 PJ3/AN7/KS11 PJ2/AN6/KS10 PB1/AN21 PB0/AN20 PA2/AN14 PA1/AN13 PA0/AN12 PA7/AN19 PA6/AN18 PA5/AN17 PA4/AN16 PA3/AN15 VDD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC PJ1/AN5/KS9 VSS PB2/AN22 PB3/AN23 PB4/SI3 PB5/SO3 PB6/SCK3 PB7/RMC PC0/SDA0 PC1/SCL0 PC2/SDA1 PC3/SCL1 PC4 PC5 PC6 PC7 VSS PD0/KS0 PD1/KS1 PD2/KS2 PD3/KS3 PD4/KS4 PD5/KS5 PD6/KS6 PD7/KS7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Vss 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD AD11 AD12 I/T MON ERST C1 C2 QS0 QS1 QS2 Vss A23 A22 A21 A20 A19 A18 A17 A16 AD15 AD14 AD13 Vss 25 26 27 28 29 30 31 32 33 34 35 36 48 47 46 45 44 43 42 41 40 39 38 37 VDD E/P ST0 ST1 ST2 ST3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 PJ0/AN4/KS8 AVDD AVREF1 AVREF0 AVss AN3 AN2 AN1 PI7/AN0 PI6/NMI PI5/INT7 PI4/INT6 PI3/INT5 PI2/INT4 PI1/INT3 PI0/INT2 PH7/INT1 PH6/INT0 PH5/XOUT PH4/RTO4 PH3/RTO3 PH2/RTO2 PH1/RTO1 PH0/RTO0 Vss TX TEX VDD PG7/SCK2 PG6/SO2 WTACK 65 JRQH 64 JRQL 63 ENMI 62 MS Vss 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PE7 PF0 PF2/CS0 PF3/SI0 PF4/SO0 PF5/SCK0 PF1/EC PF6/TO PF7/TMO RST PG0/CS1 PG1/SI1 PG2/SO1 PG3/SCK1 PG4/CS2 Note) 1. NC (Pin 88) must be left open. However, use this pin for FLASH EEPROM incorporated version. 2. Vss (Pins 15, 41, 56 and 90) must be connected to GND. 3. VDD (Pins 44, 53 and 89) must be connected to VDD. -3- PG5/SI2 VSS XTAL EXTAL VDD CXP921000A Pin Assignment in Piggyback Mode (Top View) 100-pin LQFP package PJ7/AN11/KS15 PJ6/AN10/KS14 PJ5/AN9/KS13 PJ4/AN8/KS12 PJ3/AN7/KS11 PJ2/AN6/KS10 PJ1/AN5/KS9 PB3/AN23 PB2/AN22 PB1/AN21 PB0/AN20 PA7/AN19 PA6/AN18 PA5/AN17 PA4/AN16 PA3/AN15 PA2/AN14 PA1/AN13 PA0/AN12 PJ0/AN4/KS8 VDD VSS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AVREF0 AVss AN3 AN2 AN1 PI7/AN0 PI6/NMI PI5/INT7 PI4/INT6 PI3/INT5 PI2/INT4 PI1/INT3 PI0/INT2 PH7/INT1 PH6/INT0 PH5/XOUT PH4/RTO4 PH3/RTO3 PH2/RTO2 PH1/RTO1 PH0/RTO0 Vss TX TEX VDD PB4/SI3 PB5/SO3 PB6/SCK3 PB7/RMC PC0/SDA0 PC1/SCL0 PC2/SDA1 PC3/SCL1 PC4 PC5 PC6 PC7 VSS PD0/KS0 PD1/KS1 PD2/KS2 PD3/KS3 PD4/KS4 PD5/KS5 PD6/KS6 PD7/KS7 PE0 PE1 PE2 PE3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Vss 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD A11 A12 D7 D6 D5 D4 D3 D2 D1 D0 Vss A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 Vss 25 26 27 28 29 30 31 32 33 34 35 36 48 47 46 45 44 43 42 41 40 39 38 37 VDD CE NC D15 D14 D13 D12 D11 D10 D9 D8 Vss NC AVREF1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PG7/SCK2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PG0/CS1 PG1/SI1 PG2/SO1 PG3/SCK1 PG4/CS2 PF2/CS0 PF4/SO0 PF5/SCK0 PF7/TMO PG5/SI2 VSS PE7 PF0 PF3/SI0 PF1/EC PF6/TO RST XTAL EXTAL VDD Note) 1. NC (Pin 86) must be left open. However, use this pin for FLASH EEPROM incorporated version. 2. Vss (Pins 13, 39, 54 and 88) must be connected to GND. 3. VDD (Pins 42, 51 and 87) must be connected to VDD. 4. A20 to A23 are always high level output. -4- PG6/SO2 PE4 PE5 PE6 AVDD CXP921000A Pin Assignment in Evaluator Mode (Top View) 100-pin LQFP package PJ7/AN11/KS15 PJ6/AN10/KS14 PJ5/AN9/KS13 PJ4/AN8/KS12 PJ3/AN7/KS11 PJ2/AN6/KS10 NC (PWE) PJ1/AN5/KS9 PB3/AN23 PB2/AN22 PB1/AN21 PB0/AN20 PA7/AN19 PA6/AN18 PA5/AN17 PA4/AN16 PA3/AN15 PA2/AN14 PA1/AN13 PA0/AN12 PJ0/AN4/KS8 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AVREF0 AVss AN3 AN2 AN1 PI7/AN0 PI6/NMI PI5/INT7 PI4/INT6 PI3/INT5 PI2/INT4 PI1/INT3 PI0/INT2 PH7/INT1 PH6/INT0 PH5/XOUT PH4/RTO4 PH3/RTO3 PH2/RTO2 PH1/RTO1 PH0/RTO0 Vss TX TEX VDD PB4/SI3 PB5/SO3 PB6/SCK3 PB7/RMC PC0/SDA0 PC1/SCL0 PC2/SDA1 PC3/SCL1 PC4 PC5 PC6 PC7 VSS PD0/KS0 PD1/KS1 PD2/KS2 PD3/KS3 PD4/KS4 PD5/KS5 PD6/KS6 PD7/KS7 PE0 PE1 PE2 PE3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Vss 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD AD11 AD12 I/T MON ERST C1 C2 QS0 QS1 QS2 Vss A23 A22 A21 A20 A19 A18 A17 A16 AD15 AD14 AD13 Vss 25 26 27 28 29 30 31 32 33 34 35 36 48 47 46 45 44 43 42 41 40 39 38 37 VDD E/P ST0 ST1 ST2 ST3 WTACK JRQH JRQL ENMI MS Vss VDD VSS AVREF1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PG7/SCK2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PG0/CS1 PG1/SI1 PG2/SO1 PG3/SCK1 PG4/CS2 PF2/CS0 PF4/SO0 PF5/SCK0 PF7/TMO PG5/SI2 VSS PE7 PF0 PF3/SI0 PF1/EC PF6/TO RST XTAL EXTAL VDD Note) 1. NC (Pin 86) must be left open. However, use this pin for FLASH EEPROM incorporated version. 2. Vss (Pins 13, 39, 54 and 88) must be connected to GND. 3. VDD (Pins 42, 51 and 87) must be connected to VDD. -5- PG6/SO2 PE4 PE5 PE6 AVDD CXP921000A EPROM Read Timing (Ta = -20 to +75C, VDD = 2.7 to 3.3V, Vss = 0V) Item Address data Input delay time Address data hold time Symbol Pins A0 to A23 D0 to D15 A0 to A23 D0 to D15 0 Min. Max. 50 Unit ns ns tACC tIH 0.8VDD A0 to A23 Address data 0.2VDD tACC tIH 0.8VDD Input data 0.2VDD D0 to D15 Product List Products Optional item Mask ROM CXP921064A Package ROM capacity Reset pin pull-up resistor Piggy/evaluation chip CXP921000A-U01Q CXP921000A-U01R 100-pin ceramic PQFP (LQFPsupported) 100-pin plastic QFP/LQFP 100-pin ceramic PQFP 104-pin plastic LFLGA (QFP supported) 256K bytes Existent/Non-existent EPROM 256K bytes Existent -6- CXP921000A Switching of Piggyback Mode and Evaluator Mode Piggyback mode can be used by setting two LCC-type EPROM (for upper bytes, for lower byte) and connecting to the connector of top of the chip. Evaluator mode can be used by connecting in-circuit emulator CPU probe to the connector of top of the chip. Piggyback mode Pin 1 marking 0 1 For lower bytes For upper bytes EPROM adaptor Chip LCC-type PROM Evaluator mode CPU probe Chip Notes on PF7 Usage FLASH EEPROM incorporated PF7 is also used as flash mode setting function. Note the followings: 1. "H" is output to PF7 during a reset. That is driven at comparatively high impedance (approximately 150k), and take care that VOH should not fall under 0.7VDD by the partial pressure with external circuit load impedance. 2. When using software reset functions, PF7 may not rise enough during a reset. Switching PF7 to "H" output prior to software reset execution or connecting pull-up resistor is recommended. RST Normal operation PF7 Flash mode Keep PF7 above 0.7 VDD during this period. Mask ROM and piggy/evaluation chip do not have flash mode setting function. Considering that EEPROM incorporated type is used, above countermeasure should be performed. -7- CXP921000A Package Outline Unit: mm 100PIN PQFP(CERAMIC) 24.7 0.5 22.3 0.25 80 81 51 50 18.0 1.5 0.05 18.7 0.5 16.3 0.2 3.2 0.2 31 1 0.8 0.1 30 INDEX INDEX 3.57 0.36 0.5 0.25 + 0.05 0.15 - 0.02 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE PQFP-100C-L04 AQFP100-C-0000 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS CERAMIC GOLD PLATING 42 ALLOY 4.9g -8- 8.6 MAX 0.3 0.08 100 13.9 0.65 0.05 CXP921000A 100PIN PQFP(CERAMIC) 16.0 0.5 0.5 0.05 14.0 0.2 75 76 51 50 12.4 12.0 0.15 + 0.08 0.18 - 0.03 1.5 0.05 100 1 25 0.8 0.1 26 INDEX 3.2 0.2 INDEX + 0.05 0.127 - 0.02 3.32 0.33 + 0.15 0.2 - 0.13 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE PQFP-100C-L03 AQFP100-C-0000 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS CERAMIC GOLD PLATING 42 ALLOY 2.7g -9- 8.0 MAX |
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