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Philips Semiconductors
Product specification
8-bit Futurebus+ transceiver
FB2040A
FEATURES
* 8-bit BTL transceivers * Separate I/O on TTL A-port * Inverting * Drives heavily loaded backplanes with equivalent load
impedances down to 10.
* Compatible with IEEE Futurebus+ or proprietary BTL backplanes * Controlled output ramp and multiple GND pins minimize ground
bounce
* High drive 100mA BTL open collector drivers on B-port * Allows incident wave switching in heavily loaded backplane buses * Reduced BTL voltage swing produces less noise and reduces
power consumption
* Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
* Each BTL driver has a dedicated Bus GND for a signal return * Glitch-free power up/power down operation * Low ICC current * Tight output skew * Supports live insertion * Pins for the optional JTAG boundary scan function are provided * High density packaging in plastic Quad Flat Pack
QUICK REFERENCE DATA
SYMBOL tPLH tPHL tPLH tPHL COB IOL Propagation delay AIn to Bn Propagation delay Bn to AOn Output capacitance (B0 - B7 only) Output current (B0 - B7 only) Standby AIn to Bn (outputs Low or High) ICC Supply current Bn to AOn (outputs Low) Bn to AOn (outputs High) PARAMETER TYPICAL 4.4 3.1 3.4 3.2 4 100 4 4 22 12 mA UNIT ns ns pF mA
ORDERING INFORMATION
PACKAGES 52-pin Plastic Quad Flat Pack (QFP) COMMERCIAL RANGE VCC = 5V10%; Tamb = 0C to +70C FB2040BB DRAWING NUMBER SOT379-1
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. SYMBOL VCC VIN IIN VOUT IOUT Tamb TSTG Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature A0 - A7 B0 - B7 AI0 - AI7, OEB0, OEB1, OEA B0 - B7 PARAMETER RATING -0.5 to +7.0 -1.2 to +7.0 -1.2 to +5.5 -18 to +5.0 -0.5 to +VCC 48 200 -40 to ++85 -65 to +150 UNIT V V mA V mA C C
1995 May 25
1
853-1801 15279
Philips Semiconductors
Product specification
8-bit Futurebus+ transceiver
FB2040A
PIN CONFIGURATION
TCK (option) LOGIC VCC TMS (option) BUS GND BUS VCC BIAS V
52 51 50 49 48 47 46 45 44 43 42 41 40 LOGIC GND AI1 AI2 AO2 LOGIC GND AO3 LOGIC GND AI3 AI4 AO4 LOGIC GND AO5 LOGIC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 BG VCC LOGIC GND TDI (option) BUS VCC AI5 AI6 TDO (option) AO6 BG GND AO7 AI7 NC B7 39 38 37 36 BUS GND B1 BUS GND B2 BUS GND B3 BUS GND B4 BUS GND B5 BUS GND B6 BUS GND
8-Bit Transceiver FB2040A
B0/B0 35 34 33 32 31 30 29 28 27
OEB0
52-lead PQFP
OEB1
AO1
AO0
AI0
OEA
SG00076
DESCRIPTION
The FB2040A is an 8-bit bidirectional BTL transceiver and is intended to provide the electrical interface to a high performance wired-OR bus. The FB2040A is an inverting transceiver. The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V. The B-port interfaces to "Backplane Transceiver Logic" (See the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. The A-port operates at TTL levels with separate I/O. The 3-state A-port drivers are enabled when OEA goes High after an extra 6ns delay which is built in to provide a break-before-make function. When OEA goes Low, A-port drivers become High impedance without any extra delay. During power on/off cycles, the A-port drivers are held in a High impedance state when VCC is below 2.5V. The B-port has two output enables, OEB0 and OEB1. When OEB0 is High and OEB1 is Low the output is enabled. When OEB0 is Low
or if OEB1 is High, the B-port is inactive and is at the level of the backplane signal. To support live insertion, OEB0 is held Low during power on/off cycles to insure glitch free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 5V level while VCC is Low. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin. The LOGIC GND and BUS GND pins are isolated in the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a "hard" signal failure occurs instead of a pattern dependent error that may be very infrequent and impossible to trouble-shoot. The LOGIC VCC and BUS VCC pins are also isolated internally to minimize noise and may be externally decoupled separately or simply tied together. JTAG boundary scan pins are provided with signals TMS, TCK, TDI and TDO. TMS and TCK are no-connects (no bond wires) and TDI and TDO are shorted together internally. Boundary scan functionality is not implemented at this time.
1995 May 25
2
Philips Semiconductors
Product specification
8-bit Futurebus+ transceiver
FB2040A
PIN DESCRIPTION
SYMBOL AI0 - AI7 AO0 - AO7 B0 - B7 OEB0 OEB1 OEA BUS GND LOGIC GND BUS VCC LOGIC VCC BG VCC BG GND BIAS V TMS TCK TDI TDO NC PIN NUMBER 51, 2, 3, 8, 9, 14, 18, 24 50, 52, 4, 6, 10, 12, 16, 20 40, 38, 36, 34, 32, 30, 28, 26 46 45 47 41, 39, 37, 35, 33, 31, 29, 27 1, 5, 7, 11, 13, 15 23, 43 49 17 19 48 42 44 22 21 25 TYPE Input Output I/O Input Input Input GND GND Power Power Power GND Power Input Input Input Output NC Data inputs (TTL) 3-state outputs (TTL) Data inputs/Open Collector outputs. High current drive (BTL) Enables the B outputs when High Enables the B outputs when Low Enables the A outputs when High Bus ground (0V) Logic ground (0V) Positive supply voltage Positive supply voltage Band Gap threshold voltage reference Band Gap threshold voltage reference ground Live insertion pre-bias pin Test Mode Select (optional, if not implemented then no-connect) Test Clock (optional, if not implemented then no-connect) Test Data In (optional, if not implemented then shorted to TDO) Test Data Out (optional, if not implemented then shorted to TDI) No Connect NAME AND FUNCTION
FUNCTION TABLE
MODE INPUTS AIn L AIn to Bn H L H Disable Bn outputs X X X Bn to AOn X X X Disable AOn outputs H** = B* = -- Bn* -- -- -- -- X X L H L H X OEB0 H H H H L X L X X L X OEB1 L L L L X H X H H X X OEA L L H H X X H H H H L Z Z L H X X H L H L Z OUTPUTS AOn Bn* H** L H** L H** H** Input Input Input Input X
Goes to level of pull-up voltage Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state.
1995 May 25
3
Philips Semiconductors
Product specification
8-bit Futurebus+ transceiver
FB2040A
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIK IOH IOL COB Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Output capacitance on B port Operating free-air temperature range 0 AO0 - AO7 AO0 - AO7 B0 - B7 Except B0-B7 B0 - B7 Except B0-B7 B0 - B7 PARAMETER LIMITS MIN 4.5 2.0 1.62 1.55 0.8 1.47 -18 -3 24 100 5 +70 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA pF C
1995 May 25
4
Philips Semiconductors
Product specification
8-bit Futurebus+ transceiver
FB2040A
LOGIC DIAGRAM FOR FB2040
OEB0 46
OEB1 OEA AI0 AO0
45
47 40 51 50 B0
38 AI1 AO1 2 52
B1
36 AI2 AO2 3 4
B2
34 AI3 8 6
B3
TTL Levels
AO3
BTL Levels
32 B4
AI4 AO4
9 10
30 AI5 AO5 14 12
B5
28 AI6 AO6 18 16
B6
26 AI7 AO7 24 20
B7
TMS TCK TDI TDO NC = LOGIC VCC = LOGIC GND = BUS VCC = BUS GND = BIAS V = = BG VCC BG GND =
42 44 22 21
(Future JTAG Boundary Scan option)
25 49 1, 5, 7, 11, 13, 15 23, 43 27, 29, 31, 33, 35, 37, 39, 41 48 17 19
SG00077
1995 May 25
5
Philips Semiconductors
Product specification
8-bit Futurebus+ transceiver
FB2040A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted. SYMBOL IOH IOFF VOH PARAMETER High level output current Power-off output current High-level output voltage B0 - B7 B0 - B7 AO0 - AO0 - VOL VIK II Low-level output voltage AO73 AO73 TEST CONDITIONS1 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V VCC = MIN, VIL = MAX, VIH = MIN, IOH = -3mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 24mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 80mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 100mA Input clamp voltage Input current at maximum input voltage High-level input current OEB0, OEB1, OEA, AI0-AI7 OEB0, OEB1, OEA, AI0-AI7 B0 - B7 IIL IOZH IOZL IOS Low-level input current Off-state output current Off-state output current Short-circuit output current4 OEB0, OEB1, OEA, AI0-AI7 B0 - B7 AO0 - AO7 AO0 - AO7 AO0 - AO7 only ICCZ (standby) ICCB, AIn to Bn ICC Supply current (total) ICCA, Bn to AOn ICCA, Bn to AOn VCC = MIN, II = IIK VCC = MAX, VI = GND or 5.5V VCC = MAX, VI = 2.7V VCC = MAX, VI = 2.1V VCC = MAX, VI = 0.5V VCC = MAX, VI = 0.75V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX, VO = 0.0V VCC = MAX VCC = MAX, outputs Low or High VCC = MAX, outputs Low VCC = MAX, outputs High -30 19 40 22 19 .75 2.5 2.85 0.33 1.0 0.5 1.10 1.15 -1.2 50 20 100 -20 -100 50 -50 -150 30 60 35 35 mA A A mA A V A A V LIMITS MIN TYP2 MAX 100 100 UNIT A A V
B0 - B7
IIH
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 5V, TA = 25C. 3. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 4. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS should be performed last.
1995 May 25
6
Philips Semiconductors
Product specification
8-bit Futurebus+ transceiver
FB2040A
AC ELECTRICAL CHARACTERISTICS
A PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C, VCC = 5V, CL = 50pF, RL = 500 MIN tPLH tPHL tPZH tPZL tPHZ tPLZ tTLH tTHL tSK(o) Propagation delay, Bn to AOn Output enable time, OEA to AOn Output disable time, OEA to AOn Transition time, AOn Port (10% to 90% or 90% to 10%) Output skew between receivers in same package1 Waveform 1, 2 Waveform 4, 5 Waveform 4, 5 Test Circuit and Waveforms Waveform 3 1.8 1.6 1.0 1.0 1.5 1.5 1.5 1.5 3.3 3.3 2.2 2.4 0.4 TYP 3.4 3.2 MAX 5.0 4.9 5.0 5.0 4.8 5.4 3.5 3.5 1.0 B PORT LIMITS SYMBOL PARAMETER TEST CONDITION Waveform 1, 2 Waveform 2 Waveform 1 Test Circuit and Waveforms Waveform 3 TEST CONDITION Waveform 1, 2 Waveform 2 Waveform 1 Test Circuit and Waveforms Waveform 3 3.0 1.7 3.0 2.0 3.1 1.8 1.0 0.5 Tamb = +25C, VCC = 5V, CD = 30pF, RU = 9 2.9 1.6 2.9 1.9 3.0 1.7 1.0 0.5 4.4 3.3 4.7 3.5 5.3 3.2 1.4 1.1 0.3 RU = 16.5 4.5 3.3 4.8 3.5 5.4 3.3 1.5 1.1 0.3 6.4 4.8 6.0 5.2 6.4 4.9 3.0 3.0 1.0 5.0 4.8 5.9 5.1 6.3 4.8 3.0 3.0 1.0 Tamb = 0 to 70C, VCC = 5V10%, CD = 30pF, RU = 9 2.3 1.5 2.6 1.8 2.7 1.5 1.0 0.5 5.5 5.1 7.8 5.7 8.0 5.7 3.0 3.0 1.0 RU = 16.5 2.3 1.6 2.7 1.9 2.8 1.6 1.0 0.5 6.9 5.1 7.9 5.7 8.1 5.7 3.0 3.0 1.0 UNIT Tamb = 0 to 70C, VCC = 5V10%, CL = 50pF, RL = 500 MIN 1.6 1.6 1.5 1.5 1.2 1.3 1.0 1.0 MAX 5.6 5.3 5.5 5.5 5.0 5.9 4.5 4.5 1.0 ns ns ns ns ns UNIT
tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tSK(o) SYMBOL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tSK(o)
Propagation delay, AIn to Bn Enable/disable time, OEB0 to Bn Enable/disable time, OEB1 to Bn Transition time, Bn Port (1.3V to 1.8V) Output skew between drivers in same package1 PARAMETER Propagation delay, AIn to Bn Enable/disable time, OEB0 to Bn Enable/disable time, OEB1 to Bn Transition time, Bn Port (1.3V to 1.8V) Output skew between drivers in same package1
ns ns ns ns ns UNIT ns ns ns ns ns
NOTES: 1. tPNactual - tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.).
1995 May 25
7
Philips Semiconductors
Product specification
8-bit Futurebus+ transceiver
FB2040A
AC WAVEFORMS
AIn, Bn OEB1 VM tPLH VM VM tPHL VM AOn, Bn AIn, Bn OEB0 VM tPHL VM VM tPLH VM
AOn, Bn
Waveform 1. Propagation Delay for Data or Output Enable to Output
Waveform 2. Propagation Delay for Data or Output Enable to Output
AIn, Bn
VM tSK(o)
AOn, Bn
VM
Waveform 3. Output Skews
OEA VM tPZH AOn VM VM tPHZ VOH -0.3V OV AOn OEA VM tPZL VM VM tPLZ VOL +0.3V
Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
SG00078
NOTE: VM = 1.55V for Bn, VM = 1.5V for all others.
1995 May 25
8
Philips Semiconductors
Product specification
8-bit Futurebus+ transceiver
FB2040A
TEST CIRCUIT AND WAVEFORMS
VCC BIAS V RL 7.0V NEGATIVE PULSE 90% VM 10% tTHL CL RL tW VM 10% LOW V tTLH AMP (V)
90%
VIN PULSE GENERATOR RT D.U.T.
VOUT
(tf) (tr)
90% VM tW
(tr) (tf)
AMP (V)
tTLH 90% POSITIVE PULSE VM 10%
tTHL
Test Circuit for 3-State Outputs on A Port
10%
LOW V
VM = 1.55V for Bn, VM = 1.5V for all others.
SWITCH POSITION TEST tPLZ, tPZL All other SWITCH closed open Family FB+
VCC BIAS V 2.0V (for RU = 9 ) 2.1V (for RU = 16.5 )
Input Pulse Definitions
INPUT PULSE REQUIREMENTS Amplitude 3.0V 2.0V Low V 0.0V 1.0V Rep. Rate 1MHz 1MHz tW tTLH tTHL 2.5ns 2.5ns
A Port B Port
500ns 2.5ns 500ns 2.5ns
VIN PULSE GENERATOR RT D.U.T.
VOUT
RU
CD
Test Circuit for Outputs on B Port
DEFINITIONS: RL = Load Resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. CD = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RU = Pull up resistor; see AC CHARACTERISTICS for value.
SG00059
1995 May 25
9

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