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74F552 Octal Registered Transceiver with Parity and Flags
April 1988 Revised March 2000
74F552 Octal Registered Transceiver with Parity and Flags
General Description
The 74F552 octal transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock pulse and clock enable input as well as a flag flip-flop that is set automatically as the register is loaded. The flag output will be reset when the output enable returns to HIGH after reading the output port. Each register has a separate output enable control for its 3-STATE buffer. The separate Clocks, Flags, and Enables provide considerable flexibility as I/O ports for demand-response data transfer. When data is transferred from the A Port to the B Port, a parity bit is generated. On the other hand, when data is transferred from the B Port to the A Port, the parity of input data on B0-B7 is checked.
Features
s 8-Bit bidirectional I/O Port with handshake s Register status flag flip-flops s Separate clock enable and output enable s Parity generation and parity check s B-outputs sink 64 mA s 3-STATE outputs
Ordering Code:
Order Number 74F552SC 74F552QC Package Number M28B V28A Package Description 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
Pin Assignments for SOIC Pin Assignments for PLCC
(c) 2000 Fairchild Semiconductor Corporation
DS009561
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74F552
Logic Symbols
IEEE/IEC
Unit Loading/Fan Out
Pin Names A0-A7 B0-B7 FR FS PARITY ERROR CER CES CPR CPS OEBR OEAS Description A-to-B Port Data Inputs or B-to-A 3-STATE B-to-A Transceiver Inputs or A-to-B 3-STATE Output B Port Flag Output A Port Flag Output Parity Bit Transceiver Input or Output Parity Check Output (Active LOW) R Registers Clock Enable Input (Active LOW) S Registers Clock Enable Input (Active LOW) R Registers Clock Pulse Input (Active Rising Edge) S Registers Clock Pulse Input (Active Rising Edge) B Port and PARITY Output Enable (Active LOW) and Clear FR Input (Active Rising Edge) A Port Output Enable (Active LOW) and Clear FS Input (Active Rising Edge) 1.0/2.0 20 A/-1.2 mA U.L. HIGH/LOW 3.5/1.083 150/40 (33.3) 3.5/1.083 50/33.3 50/33.3 3.5/1.083 50/33.3 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/2.0 Input IIH/IIL Output IOH/IOL 70 A/-0.65 mA -3 mA/24 mA (20 mA) 70 A/-0.65 mA -1 mA/20 mA -1 mA/20 mA 70 A/-0.65 mA -1 mA/20 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-1.2 mA
600/106.6 (80) -12 mA/64 mA (48 mA)
600/106.6 (50) -12 mA/64 mA (48 mA)
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74F552
Functional Description
Data applied to the A-inputs are entered and stored in the R register on the rising edge of the CPR Clock Pulse, provided that the Clock Enable (CER) is LOW; simultaneously, the status flip-flop is set and the flag (FR) output goes HIGH. As the Clock Enable (CER) returns to HIGH, the data will be held in the R register. These data entered from the A-inputs will appear at the B Port I/O pins after the Output Enable (OEBR) has gone LOW. When OEBR is LOW, a parity bit appears at the PARITY pin, which will be set HIGH when there is an even number of 1s or all 0s at the Q outputs of the R register. After the data is assimilated, the receiving system clears the flag FR by changing the signal at the OEBR pin from LOW-to-HIGH. Data flow from B-to-A proceeds in the same manner described for A-to-B flow. A LOW at the CES pin and a LOW-to-HIGH transition at CPS pin enters the B-input data and the parity-input data into the S registers and the parity register respectively and set the flag output FS to HIGH. A LOW signal at the OEAS pin enables the A Port I/O pins and a LOW-to-HIGH transition of the OEAS signal clears the FS flag. When OEAS is LOW, the parity check output ERROR will be HIGH if there is an odd number of 1s at the Q outputs of the S registers and the parity register. The flag FS can be cleared by a LOW-to-HIGH transition of the OEAS signal.
Register Function Table
(Applies to R or S Register) Inputs D X L H X CP CE H L L L Internal Function Q NC L H NC Hold Data Load Data Keep Old Data
Flag Flip-Flop Function Table
(Applies to R or S Flag Flip-Flop) Inputs Flag Function CE H L X CP OE Output NC H L Hold Flag Set Flag Clear Flag

X
X X
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= LOW-to-HIGH Transition = Not LOW-to-HIGH Transition NC = No Change
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= LOW-to-HIGH Transition = Not LOW-to-HIGH Transition NC = No Change
Output Control
OE H L L
H = HIGH Voltage Level L = LOW Voltage Level
Parity Generation Function
A or B Outputs Z L H Function Disable Output Enable Output Enable Output OEBR H L L
H = HIGH Voltage Level L = LOW Voltage Level
Internal Q X L H
Number of HIGHs in the Q Outputs of the R Register X 0, 2, 4, 6, 8 1, 3, 5, 7
X = Immaterial Z = High Impedance
Parity Output Z H L
X = Immaterial Z = High Impedance
Parity Check Function
OEAS H L L L L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Number of HIGHs in the Q Outputs of the S Register X 0, 2, 4, 6, 8 1, 3, 5, 7 0, 2, 4, 6, 8 1, 3, 5, 7
Parity Input X L L H H
ERROR Output H L H H L
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74F552
Block Diagram
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74F552
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +175C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage VOH Output HIGH Voltage 10% VCC 10% VCC 10% VCC 5% VCC 5% VCC VOL Output LOW Voltage IIH IBVI IBVIT ICEX VID IOD IIL IIH + IOZH IIL + IOZL IOS IZZ ICCH ICCL ICCZ Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown (I/O) Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current 4.75 3.75 -0.6 -1.2 Output Leakage Current Output Leakage Current Output ShortCircuit Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current 100 100 110 -60 -100 70 -650 -175 -250 500 150 150 165 10% VCC 10% VCC 10% VCC 2.5 2.4 2.0 2.7 2.7 0.5 0.5 0.55 5.0 A A mA A V A Max V Min V Min Min 2.0 0.8 -1.2 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA (CER, CES, CPR, CPS, OEBR, OEAS) IOH = -1 mA (FR, FS, ERROR, An) IOH = -3 mA (An, Bn PARITY) IOH = -15 mA (Bn, PARITY) IOH = -1 mA (FR, FS, ERROR, An) IOH = -3 mA (An, Bn, PARITY) IOL = 20 mA (FR, FS, ERROR) IOL = 24 mA (An) IOL = 64 mA (Bn, PARITY) VIN = 2.7V (CER, CES, CPR, CPS, OEBR, OEAS) VIN = 7.0V (CER, CES, CPR, CPS, OEBR, OEAS) VIN = 5.5V (An, Bn, PARITY) VOUT = VCC (FR, FS, ERROR, An, Bn, PARITY) IID = 1.9 A All other pins grounded VIOD = 150 mV All other pins grounded VIN = 0.5V (CER, CES, CPR, CPS) VIN = 0.5V (OEBR, OEAS) VOUT = 2.7V (An, B n, PARITY) VOUT = 0.5V (An, B n, PARITY) VOUT = 0V (FR, FS, ERROR, An) VOUT = 0V (Bn, PARITY) VOUT = 5.25V (An, Bn, PARITY) VO = HIGH VO = LOW VO = HIGH Z
7.0 0.5 50
Max Max Max 0.0 0.0
mA A A mA A mA mA mA
Max Max Max Max 0.0V Max Max Max
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74F552
AC Electrical Characteristics
TA = +25C Symbol Parameter Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Propagation Delay CPS or CPR to An or Bn Propagation Delay CPS or CPR to FS or FR Propagation Delay OEAS to FS Propagation Delay CPR to Parity Propagation Delay CPS to ERROR Propagation Delay OEAS to ERROR Enable Time OEAS or OEBR to Bn or An Disable Time OEAS or OEBR to Bn or An Enable Time OEBR to Parity Disable Time OEBR to Parity 3.5 4.0 3.0 3.5 8.0 8.5 8.0 7.5 3.5 3.0 3.0 3.5 3.0 3.0 3.0 3.5 3.0 3.0 VCC = +5.0V CL = 50 pF Typ 6.0 7.0 5.5 6.0 14.0 14.5 13.5 13.0 6.0 5.0 5.5 7.0 6.5 5.5 4.5 6.0 5.5 6.5 Max 8.0 9.5 7.5 8.0 18.0 18.5 17.5 16.5 8.0 7.0 7.5 9.5 8.5 7.5 7.5 9.5 8.5 7.5 TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 3.0 3.5 2.5 3.0 7.0 7.5 7.0 6.5 3.0 2.5 2.5 3.0 2.5 2.5 2.5 3.0 2.5 2.5 Max 9.0 10.5 8.5 9.0 20.0 20.5 19.5 18.5 9.0 8.0 8.5 10.5 9.5 8.5 8.5 10.5 9.5 8.5 ns ns ns ns ns ns ns Units
ns
AC Operating Requirements
TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW An or Bn or Parity to CPS or CPR Hold Time, HIGH or LOW An or Bn or Parity to CPS or CPR Setup, Time HIGH or LOW CES or CER to CPS or CPR Hold Time, HIGH or LOW CES or CER to CPS or CPR Pulse Width, HIGH or LOW CPS or CPR 6.0 10.0 0 0 4.0 6.0 7.0 11.5 0 0 4.5 7.0 ns ns 0 0 0 0 7.5 4.5 Max TA = 0C to +70C VCC = +5.0V Min 8.5 5.0 ns Max Units
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74F552
Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M28B
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74F552 Octal Registered Transceiver with Parity and Flags
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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