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STK11C48
2K x 8 nvSRAM QuantumTrapTM CMOS Nonvolatile Static RAM
Obsolete - Not Recommend for new Designs
FEATURES
* 25ns, 35ns and 45ns Access Times * STORE to Nonvolatile Elements Initiated by Software * RECALL to SRAM Initiated by Software or Power Restore * 10mA Typical ICC at 200ns Cycle Time * Unlimited READ, WRITE and RECALL Cycles * 1,000,000 STORE Cycles to Nonvolatile Elements * 100-Year Data Retention in Nonvolatile Elements * Commercial and Industrial Temperatures * 28-Pin 300 mil PDIP, 300 mil SOIC and 350 mil SOIC Packages
DESCRIPTION
The Simtek STK11C48 is a fast static RAM with a nonvolatile element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent, nonvolatile data resides in the Nonvolatile Elements. Data transfers from the SRAM to the Nonvolatile Elements (the STORE operation), or from Nonvolatile Elements to SRAM (the RECALL operation), take place using a software sequence. Transfers from the Nonvolatile Elements to the SRAM (the RECALL operation) also take place automatically on restoration of power.
BLOCK DIAGRAM
Quantum Trap 32 x 512
PIN CONFIGURATIONS
NC NC A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
A5 A6 A7 A8 A9
STORE STATIC RAM ARRAY 32 x 512 RECALL
STORE/ RECALL CONTROL
SOFTWARE DETECT DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 INPUT BUFFERS COLUMN I/O COLUMN DEC
A0 - A10
VCC W NC A8 A9 NC G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
ROW DECODER
28 - 300 PDIP 28 - 300 SOIC 28 - 350 SOIC
PIN NAMES
A0 - A10 W Address Inputs Write Enable Data In/Out Chip Enable Output Enable Power (+ 5V) Ground
A0 A1 A2 A3 A4 A10
G E W
DQ0 - DQ7 E G VCC VSS
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STK11C48
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to Ground . . . . . . . . . . . . . .-0.5V to 7.0V Voltage on Input Relative to VSS . . . . . . . . . . -0.6V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS
COMMERCIAL SYMBOL ICC1b PARAMETER MIN Average VCC Current MAX 85 75 65 3 10 25 21 18 750 1 5 2.2 VSS - .5 2.4 0.4 0 70 -40 VCC + .5 0.8 2.2 VSS - .5 2.4 0.4 85 MIN MAX 90 75 65 3 10 26 22 19 750 1 5 VCC + .5 0.8 mA mA mA mA mA mA mA mA A A A V V V V C INDUSTRIAL UNITS
(VCC = 5.0V 10%)
NOTES tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns All Inputs Don't Care, VCC = max W (V CC - 0.2V) All Others Cycling, CMOS Levels tAVAV = 25ns, E VIH tAVAV = 35ns, E VIH tAVAV = 45ns, E VIH E (V CC - 0.2V) All Others VIN 0.2V or (VCC - 0.2V) VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G VIH All Inputs All Inputs IOUT = - 4mA IOUT = 8mA
ICC2c ICC3
b
Average VCC Current during STORE Average VCC Current at tAVAV = 200ns 5V, 25C, Typical Average VCC Current (Standby, Cycling TTL Input Levels) VCC Standby Current (Standby, Stable CMOS Input Levels) Input Leakage Current Off-State Output Leakage Current Input Logic "1" Voltage Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Operating Temperature
ISB1d
ISB2d IILK IOLK VIH VIL VOH VOL TA
Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. Note c: ICC2 is the average current required for the duration of the STORE cycle (tSTORE ) . Note d: E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
5.0V
CAPACITANCEe
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance
480 Ohms
(TA = 25C, f = 1.0MHz)
OUTPUT
MAX 8 7 UNITS pF pF CONDITIONS V = 0 to 3V V = 0 to 3V
255 Ohms
30 pF INCLUDING SCOPE AND FIXTURE
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
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STK11C48 SRAM READ CYCLES #1 & #2
SYMBOLS NO. 1 2 3 4 5 6 7 8 9 10 11 PARAMETER #1, #2 tELQV tAVAVf tAVQVg tGLQV tAXQXg tELQX tEHQZh tGLQX tGHQZ
h
(VCC = 5.0V + 10%)
STK11C48-25 STK11C48-35 MIN MAX 35 35 25 10 5 5 10 0 10 0 25 0 35 0 13 0 45 5 5 13 0 15 35 15 5 5 15 45 45 20 STK11C48-45 UNITS MIN MAX 25 25 MIN MAX 45 ns ns ns ns ns ns ns ns ns ns ns
Alt. tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby
tELICCHe tEHICCL
d, e
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected. Note h: Measured 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
tAVAV ADDRESS
5 tAXQX 3 2
tAVQV
DATA VALID
DQ (DATA OUT)
SRAM READ CYCLE #2: E Controlledf
tAVAV ADDRESS tELQV E
6 tELQX 7 1 2
tEHICCL
11
tEHQZ
G tGLQV
4
tGHQZ
9
tGLQX DQ (DATA OUT)
10 tELICCH DATA VALID
8
ACTIVE
ICC
STANDBY
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STK11C48
SRAM WRITE CYCLES #1 & #2
SYMBOLS NO. #1 12 13 14 15 16 17 18 19 20 21 tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX tWLQZ
h, i
(VCC = 5.0V + 10%)
STK11C48-25 PARAMETER STK11C48-35 MIN 35 25 25 12 0 25 0 0 10 5 5 13 5 MAX STK11C48-45 UNITS MIN MAX MIN 45 30 30 15 0 30 0 0 15 MAX ns ns ns ns ns ns ns ns ns ns 25 20 20 10 0 20 0 0
#2 tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX
Alt. tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write
tWHQX
Note i: Note j:
If W is low when E goes low, the outputs remain in the high-impedance state. E or W must be VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledj
12 tAVAV ADDRESS 14 tELWH E 17 tAVWH 13 tWLWH 15 tDVWH DATA IN 20 tWLQZ DATA OUT
PREVIOUS DATA HIGH IMPEDANCE DATA VALID
19 tWHAX
18 tAVWL W
16 tWHDX
21 tWHQX
SRAM WRITE CYCLE #2: E Controlledj
12 tAVAV ADDRESS 18 tAVEL E 14 tELEH 19 tEHAX
17 tAVEH W
13 tWLEH 15 tDVEH 16 tEHDX
DATA VALID HIGH IMPEDANCE
DATA IN DATA OUT
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STK11C48
STORE INHIBIT/POWER-UP RECALL
SYMBOLS NO. Standard 22 23 24 25 tRESTORE tSTORE VSWITCH VRESET Power-up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level Low Voltage Reset Level 4.0 PARAMETER MIN MAX 550 10 4.5 3.6 s ms V V k
(VCC = 5.0V + 10%)
STK11C48 UNITS NOTES
Note k: tRESTORE starts from the time VCC rises above VSWITCH.
STORE INHIBIT/POWER-UP RECALL
VCC
5V 24 VSWITCH 25 VRESET
STORE INHIBIT
POWER-UP RECALL 22 tRESTORE DQ (DATA OUT)
POWER-UP RECALL
BROWN OUT STORE INHIBIT NO RECALL (VCC DID NOT GO BELOW VRESET)
BROWN OUT STORE INHIBIT NO RECALL (VCC DID NOT GO BELOW VRESET)
BROWN OUT STORE INHIBIT RECALL WHEN VCC RETURNS ABOVE VSWITCH
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STK11C48
SOFTWARE STORE/RECALL MODE SELECTION
E W A10 - A0 (hex) 000 555 2AA 7FF 0F0 70F 000 555 2AA 7FF 0F0 70E MODE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL I/O Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z NOTES
L
H
l
L
H
l
Note l:
The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
SOFTWARE STORE/RECALL CYCLEm, n
STK11C48-25 NO. 26 27 28 29 30 SYMBOLS tAVAV tAVEL
m
(VCC = 5.0V 10%)b
STK11C48-35 MIN 35 0 25 20 20 20 MAX STK11C48-45 UNITS MIN MAX MIN 45 0 30 20 20 MAX ns ns ns ns s 25 0 20 20
PARAMETER STORE/RECALL Initiation Cycle Time Address Set-up Time Clock Pulse Width Address Hold Time
tELEHm tELAXm tRECALL
m
RECALL Duration
Note m: The software sequence is clocked with E controlled reads. Note n: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (000, 555, 2AA, 7FF, 0F0, 70F) for a STORE cycle or (000, 555, 2AA, 7FF, 0F0, 70E) for a RECALL cycle. W must be high during all six consecutive cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlledn
tAVAV ADDRESS
27 ADDRESS #1 26
tAVAV
ADDRESS #6
26
tAVEL E
tELEH
28
tELAX
23 30 / tRECALL
29
tSTORE DQ (DATA OUT)
DATA VALID DATA VALID
HIGH IMPEDANCE
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STK11C48
DEVICE OPERATION
The STK11C48 is a versatile memory chip that provides several modes of operation. The STK11C48 can operate as a standard 8K x 8 SRAM. It has an 8K x 8 Nonvolatile Elements shadow to which the SRAM information can be copied or from which the SRAM can be updated in nonvolatile mode.
SOFTWARE NONVOLATILE STORE
The STK11C48 software STORE cycle is initiated by executing sequential READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 000 (hex) 555 (hex) 2AA (hex) 7FF (hex) 0F0 (hex) 70F (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle
NOISE CONSIDERATIONS
Note that the STK11C48 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1F connected between Vcc and Vss, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems.
SRAM READ
The STK11C48 performs a READ cycle whenever E and G are low and W is high. The address specified on pins A0-10 determines which of the 2,048 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high.
The software sequence must be clocked with E controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.
SRAM WRITE
A WRITE cycle is performed whenever E and W are low. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of READ operations must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 000 (hex) 555 (hex) 2AA (hex) 7FF (hex) 0F0 (hex) 70E (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle
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STK11C48
Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the Nonvolatile Element cells. The nonvolatile data can be recalled an unlimited number of times.
HARDWARE PROTECT
The STK11C48 offers hardware protection against inadvertent STORE operation during low-voltage conditions. When VCC < VSWITCH, all software STORE operations are inhibited.
LOW AVERAGE ACTIVE POWER
The STK11C48 draws significantly less current when it is cycled at times longer than 50ns. Figure 2 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Figure 3 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK11C48 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the Vcc level; and 7) I/ O loading.
100
POWER-UP RECALL
During power up, or after any low-power condition (VCC < VRESET), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the STK11C48 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected either between W and system VCC or between E and system VCC.
100
Average Active Current (mA)
80
Average Active Current (mA)
80
60
60 TTL CMOS 20
40 TTL 20 CMOS 0 50 100 150 Cycle Time (ns) 200
40
0 50 100 150 Cycle Time (ns) 200
Figure 2: ICC (max) Reads
Figure 3: ICC (max) Writes
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STK11C48 ORDERING INFORMATION
STK11C48 - P F 45 I Temperature Range
Blank = Commercial (0 to 70C) I = Industrial (-40 to 85C)
Access Time
25 = 25ns 35 = 35ns 45 = 45ns
Lead Finish
Blank = 85%Sn/15%Pb F = 100% Sn (Matte Tin)
Package
P = Plastic 28-pin 300 mil DIP N = Plastic 28-pin 300 mil SOIC S = Plastic 28-pin 350 mil SOIC
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STK11C48
Document Revision History
Revision 0.0 0.1 0.2
Date October 2002 September 2003 March 2006
Summary Removed 20 nsec device. Added lead-free lead finish Marked as Obsolete, Not recommended for new design.
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