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DATASHEET
AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
FEATURES
* * * * * * * * * * * * * * * * * * High Performance Technology AC'97 Rev 2.3 Complaint 20-bit Full Duplex Stereo ADC & DACs Independent Sample Rates for ADC & DACs 5-Wire AC-Link Protocol Compliance 20-Bit SPDIF Output Universal Jacks TM Full Stereo Microphone Pre-Amp Internal Jack Sensing on Headphone & Line_Out Internal Microphone Input Sensing Digital PC Beep Option Extended AC'97 2.3 Paging Registers General Purpose I/Os and Crystal Elimination Circuit Headphone Drive Capability (50 mW per channel) Switchable Headphone Out (pins 39/41 or 35/36) 0dB, 10dB, 20dB and 30dB Microphone Boost Capability +3.3 V (STAC9753A) and +5 V (STAC9752A) Analog Power Supply Options Pin Compatible with STAC9750/52/66 * Reference Designs
STAC9752A/9753A
DESCRIPTION
IDT's STAC9752A/9753A are general purpose 20-bit, full duplex, audio CODECs conforming to the analog component specification of AC'97 (Audio CODEC 97 Component Specification Rev. 2.3). The STAC9752A/9753A incorporates IDT's proprietary technology. The AC'97 CODEC is designed to achieve a DAC SNR in excess of 94dB. The DACs, ADCs, and mixer are integrated with analog I/Os, which include four analog line-level stereo inputs, two analog line-level mono inputs, two stereo outputs, and one mono output channel. The STAC9752A/9753A includes digital input/output capability for support of modern PC systems, with an output that supports the SPDIF format. The STAC9752A/9753A is a standard 2-channel stereo CODEC. With IDT's headphone drive capability, headphones can be driven with without an external amplifier. The STAC9752A/9753A may be used as a secondary CODEC, with the STAC9700/21/56/08/84/50/52 as the primary, in a multiple CODEC configuration conforming to the AC'97 Rev. 2.3 specification. This configuration can provide the true six-channel, AC-3 playback required for DVD applications. The STAC9752A/9753A communicates via the five-wire AC-Link to any digital component of AC'97, providing flexibility in the audio system design. Packaged in an AC'97 compliant 48-pin TQFP, the STAC9752A/9753A can be placed on a motherboard, daughter boards, PCI, AMR, CNR, MDC or ACR cards. The STAC9752A/9753A provides variable sample rate Digital-to-Analog (DA) and Analog-to-Digital (AD) conversion, mixing, and analog processing. Supported audio sample rates include 48KHz, 44.1KHz, 32KHz, 22.05KHz, 16KHz, 11.025KHz, and 8 KHz; additional rates are supported in the STAC9752A/9753A soft audio drivers. All ADCs and DACs operate at 20-bit resolu-
KEY SPECIFICATIONS
* * * * * * * Analog LINE_OUT SNR: 94dB Digital DAC SNR: 92dB Digital ADC SNR: 85dB Full-scale Total Harmonic Distortion: 0.002% Crosstalk Between Input Channels: -70dB Spurious Tone Rejection: 100dB Stereo Microphone Input
RELATED MATERIALS
* Data Sheet
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TABLE OF CONTENTS
1. PRODUCT BRIEF ...................................................................................................................... 6
1.1. Features ............................................................................................................................................ 6 1.2. Description ........................................................................................................................................ 6 1.3. STAC9752A/9753A Block Diagram ................................................................................................... 8 1.4. Key Specifications ............................................................................................................................. 9 1.5. Related Materials .............................................................................................................................. 9 1.6. Additional Support ............................................................................................................................. 9
2. CHARACTERISTICS AND SPECIFICATIONS .......................................................................10
2.1. Electrical Specifications ................................................................................................................... 10 2.2. AC Timing Characteristics ............................................................................................................... 16
3. TYPICAL CONNECTION AND POWER DIAGRAMS .............................................................21
3.1. STAC9752A/9753A Typical Connection Diagram for 48-pin LQFP ................................................ 21 3.2. STAC9752A/9753A Typical Connection Diagram for 32-pad QFN ................................................. 22 3.3. Split Independent Power Supply Operation .................................................................................... 23 3.4. Split Independent Power Supply Operation for the 32-pad QFP Package ......................................24
4. CONTROLLER, CODEC, AND AC-LINK ................................................................................25
4.1. AC-Link Physical interface ............................................................................................................... 25 4.2. Controller to Single CODEC ............................................................................................................ 25 4.3. Controller to Multiple CODECs ........................................................................................................ 26 4.4. Clocking for Multiple CODEC Implementations ............................................................................... 27 4.5. STAC9752A/9753A as a Primary CODEC ...................................................................................... 28 4.6. AC-Link Power Management ........................................................................................................... 28
5. AC-LINK DIGITAL INTERFACE ..............................................................................................31
5.1. Overview ......................................................................................................................................... 31 5.2. AC-Link Serial Interface Protocol .................................................................................................... 32 5.3. AC-Link Output Frame (SDATA_OUT) ............................................................................................ 35 5.4. AC-Link Input Frame (SDATA_IN) .................................................................................................. 38 5.5. AC-Link Interoperability Requirements and Recommendations ...................................................... 42 5.6. Slot Assignments for Audio ............................................................................................................. 43
6. STAC9752A/9753A FUNCTIONAL BLOCKS .........................................................................46
6.1. STAC9752A/9753A Mixer Description ............................................................................................ 46 6.2. SPDIF Digital Mux ...........................................................................................................................48 6.3. PC Beep Implementation ................................................................................................................ 48
7. PROGRAMMING REGISTERS ................................................................................................50
7.1. Register Descriptions ...................................................................................................................... 51 7.2. General Purpose Input & Outputs ................................................................................................... 68 7.3. Extended CODEC Registers Page Structure Definition .................................................................. 72 7.4. STAC9752A/9753A Paging Registers ............................................................................................. 72 7.5. Vendor ID1 and ID2 (Index 7Ch and 7Eh) ...................................................................................... 84
8. LOW POWER MODES ............................................................................................................85 9. MULTIPLE CODEC SUPPORT ...............................................................................................87
9.1. Primary/Secondary CODEC Selection ............................................................................................ 87 9.2. Secondary CODEC Register Access Definitions ............................................................................. 88
10. TESTABILITY ........................................................................................................................89
10.1. ATE Test Mode ............................................................................................................................. 89
11. STAC9752A/9753A PIN DESCRIPTION ...............................................................................90
11.1. Pin Description for the 48-pin LQFP Package ............................................................................... 90 11.2. Pinout List 48-pin LQFP Package ................................................................................................ 91 11.3. Pin Description for the 32-pad QFN Package ............................................................................... 92 11.4. Pinout List 32-pad QFN Package ................................................................................................. 93 11.5. STAC9752A/9753A Digital I/O ...................................................................................................... 93 11.6. STAC9752A/9753A Analog I/O ..................................................................................................... 94
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11.7. STAC9752A/9753A Filter/References ........................................................................................... 95 11.8. STAC9752A/9753A Power and Ground Signals ........................................................................... 96 11.9. STAC9752A/9753A No Connects ................................................................................................. 96
12. ORDERING INFORMATION ..................................................................................................97 13. PACKAGE DRAWINGS AND PC BOARD LAYOUT INFORMATION .................................98
13.1. 48-Pin LQFP .................................................................................................................................. 98 13.2. 32-Pad QFN .................................................................................................................................. 99 13.3. PC Board Recommendations for 32-pad QFN Package ............................................................. 100
14. SOLDER REFLOW PROFILE ............................................................................................. 101
14.1. Standard Reflow Profile Data ...................................................................................................... 101 14.2. Pb Free Process - Package Classification Reflow Temperatures .............................................. 102
15. APPENDIX A: PROGRAMMING REGISTERS ................................................................... 103 16. REVISION HISTORY ........................................................................................................... 105
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LIST OF FIGURES
Figure 1. STAC9752A/9753A Block Diagram ................................................................................................. 8 Figure 2. Cold Reset Timing .......................................................................................................................... 16 Figure 3. Warm Reset Timing ........................................................................................................................16 Figure 4. Clocks Timing ................................................................................................................................. 17 Figure 5. Data Setup and Hold Timing ........................................................................................................ 18 Figure 6. Signal Rise and Fall Times Timing ............................................................................................... 19 Figure 7. AC-Link Low Power Mode Timing .................................................................................................. 19 Figure 8. ATE Test Mode Timing ................................................................................................................... 20 Figure 9. STAC9752A/9753A Typical Connection Diagram 48-pin LQFP .................................................... 21 Figure 10. STAC9752A/9753A Typical Connection Diagram 32-pad QFN ................................................. 22 Figure 11. Split Connection Diagram 32-pad QFN ....................................................................................... 24 Figure 12. AC-Link to its Companion Controller ........................................................................................... 25 Figure 13. STAC9752A/9753A Powerdown Timing ...................................................................................... 29 Figure 14. Bi-directional AC-Link Frame with Slot assignments ................................................................... 31 Figure 15. AC-Link Audio Output Frame ...................................................................................................... 35 Figure 16. Start of an Audio Output Frame ................................................................................................... 35 Figure 17. STAC9752A/9753A Audio Input Frame ....................................................................................... 38 Figure 18. Start of an Audio Input Frame ..................................................................................................... 39 Figure 19. Bi-directional AC-Link Frame with Slot assignments ....................................................................43 Figure 20. AC-Link Input Slots Dedicated To CODEC .................................................................................. 44 Figure 21. STAC9752A/9753A 2-Channel Mixer Functional Diagram .......................................................... 47 Figure 22. Example of STAC9752A/9753A Powerdown/Powerup Flow ....................................................... 85 Figure 23. Powerdown/Powerup Flow With Analog Still Alive ..................................................................... 86 Figure 24. Pin Description Drawing .............................................................................................................. 90 Figure 25. STAC9752A/9753A 32 pad QFN Pin Description Drawing ......................................................... 92 Figure 26. Package Drawing - 48-pin LQFP .................................................................................................. 98 Figure 27. Package Drawing - 32-pad QFN .................................................................................................. 99 Figure 28. Recommended PCB Layout for 32-pad QFN Package .............................................................. 100 Figure 29. Reflow Profile ............................................................................................................................ 101
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LIST OF TABLES
Table 1. Clock mode configuration ................................................................................................................ 17 Table 2. Common Clocks and Sources ......................................................................................................... 18 Table 3. Recommended CODEC ID strapping .............................................................................................. 27 Table 4. AC-Link Output Slots (transmitted from the Controller) ................................................................... 31 Table 5. The AC-Link Input Slots (transmitted from the CODEC) .................................................................32 Table 6. VRA Behavior .................................................................................................................................. 33 Table 7. Output Slot 0 Bit Definitions ............................................................................................................. 36 Table 8. Command Address Port Bit Assignments ........................................................................................ 37 Table 9. Status Address Port Bit Assignments .............................................................................................. 40 Table 10. Status Data Port Bit Assignments .................................................................................................. 41 Table 11. Primary CODEC Addressing: Slot 0 Tag Bits ................................................................................ 42 Table 12. Secondary CODEC Addressing: Slot 0 tag bits ............................................................................. 43 Table 13. AC-Link Output Slots Dedicated To CODEC ................................................................................. 43 Table 14. AC-Link Output Slots Dedicated To Audio ..................................................................................... 44 Table 15. AC-Link Input Slots Dedicated To Audio ....................................................................................... 44 Table 16. Audio Interrupt Slot Definitions ...................................................................................................... 45 Table 17. Digital PC Beep Examples ............................................................................................................. 49 Table 18. Programming Registers ................................................................................................................. 50 Table 19. Extended Audio ID Register Functions .......................................................................................... 64 Table 20. AMAP compliant ............................................................................................................................ 66 Table 21. Hardware Supported Sample Rates .............................................................................................. 67 Table 22. Supported Jack and Mic Sense Functions .................................................................................... 75 Table 23. Reg 68h Default Values ................................................................................................................. 77 Table 24. Gain or Attenuation Examples ....................................................................................................... 77 Table 25. Register 68h/Page 01h Bit Overview ............................................................................................. 77 Table 26. Sensed Bits (Outputs) ................................................................................................................... 79 Table 27. Sensed Bits (Inputs) ...................................................................................................................... 79 Table 28. Low Power Modes ......................................................................................................................... 85 Table 29. CODEC ID Selection .....................................................................................................................87 Table 30. Secondary CODEC Register Access Slot 0 Bit Definitions ...........................................................88 Table 31. Test Mode Activation .....................................................................................................................89 Table 32. ATE Test Mode Operation ............................................................................................................. 89 Table 33. STAC9752A/9753A 48 Pin LQFP Pin List ..................................................................................... 91 Table 34. STAC9752A/9753A 32 Pad QFN Pin List ...................................................................................... 93 Table 35. STAC9752A/9753A Digital Connection Signals ............................................................................ 93 Table 36. STAC9752A/9753A Analog Connection Signals ........................................................................... 94 Table 37. STAC9752A/9753A Filtering and Voltage References .................................................................. 95 Table 38. STAC9752A/9753A Power and Ground Signals ........................................................................... 96 Table 39. STAC9752A/9753A No Connects .................................................................................................. 96
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1. PRODUCT BRIEF 1.1. Features
* * * * * * * * * * * * * * * * * * * * * * * * High performance technology AC'97 Rev 2.3 Complaint, 20-bit, full duplex stereo ADCs & DACs Independent sample rates for ADCs & DACs 5-Wire AC-Link protocol compliance 20-Bit SPDIF Output Universal JacksTM Full Stereo Microphone Pre-Amp Internal Jack Sensing on Headphone & Line_Out Internal Microphone Input Sensing Digital PC Beep Option Extended AC'97 2.3 Paging Registers Digital-ready status General purpose I/Os Crystal Elimination Circuit Headphone drive capability (50 mW per channel) Switchable Headphone Out (pins 39/41 or 35/36) 0, 10db, 20db, and 30 dB microphone boost capability +3.3 V (STAC9753A) and +5 V (STAC9752A) analog power supply options Pin compatible with STAC9700/21/56 100% compatible with STAC9750/52/66 IDT Surround (SS3D) Stereo Enhancement Energy saving dynamic power modes Multi-CODEC option (Intel AC'97 rev 2.3) 94dB SNR LINE-LINE
1.2.
Description
IDT's STAC9752A/9753A are general purpose 20-bit, full duplex, audio CODECs conforming to the analog component specification of AC'97 (Audio Codec 97 Component Specification Rev. 2.3). The STAC9752A/9753A incorporates IDT's proprietary technology to achieve a DAC SNR in excess of 92dB. The DACs, ADCs and mixer are integrated with analog I/Os, which include four analog line-level stereo inputs, two analog line-level mono inputs, two stereo outputs, and one mono output channel. The STAC9752A/9753A include digital output capability for support of modern PC systems with an output that supports the SPDIF format.
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The STAC9752A/9753A are standard 2-channel stereo CODEC. With IDT's headphone drive capability, headphones can be driven without an external amplifier. The STAC9700/21/44/56/08/84/50/66 may be used as a secondary or tertiary CODEC, with the STAC9752A/9753A as the primary, in a multiple CODEC configuration conforming to the AC'97 Rev. 2.3 specification. This configuration can provide the true six-channel, AC-3 playback required for DVD applications. The STAC9752A/9753A communicates via the five wire AC-Link to any digital component of AC'97, providing flexibility in the audio system design. Packaged in an AC'97 compliant 48-pin LQFP or in the 32-pad/pin QFN, the STAC9752A/9753A can be placed on motherboards, daughter boards, PCI, AMR, CNR, MDC or ACR cards. The STAC9752A/9753A block diagram is illustrated in Figure 1. The STAC9752A/9753A provides variable sample rate Digital-to-Analog (DA) and Analog-to-Digital (AD) conversion, mixing, and analog processing. Supported audio sample rates include 48KHz, 44.1KHz, 32KHz, 22.05KHz, 16KHz, 11.025KHz, and 8KHz; additional rates are supported in the STAC9752A/9753A soft audio drivers All ADC's and DAC's operate at 20-bit resolution. Two 20-Bit DACs convert the digital stereo PCM_OUT content to audio. The MIXER block combines the PCM_OUT with any analog sources to drive the LINE_OUT and HP_OUT outputs. The MONO_OUT delivers either mic only, or a mono mix of sources from the MIXER. The stereo, variable-sample-rate, 20-bit ADCs provide record capability for any mix of mono or stereo sources, and deliver a digital stereo PCM-in signal back to the AC-Link. The microphone input in mono mode and the mono mix input can be recorded simultaneously, thus allowing for an all digital output in support of the digital-ready initiative. For a digital-ready record path, the microphone is connected to the left channel ADC while the mono output of the stereo mixer is connected to right channel ADC. The STAC9752A/9753A includes full Stereo Microphone Pre-Amp support and can be used with the 10, 20 and 30dB Microphone Boost options. This integration allows for additional cost savings and options. The STAC9752A/9753A also includes IDT's Universal JacksTM functionality for jack interchangeability. The STAC9752A/9753A includes internal jack sensing using proprietary current- and impedance-sensing techniques. The impedance load on any of the inputs or outputs, including the Headphone and Line Outputs, can be detected. This enables jack sensing on the Headphone and Line_Out. The STAC9752A/9753A jack sense can detect the presence of devices on the Headphone and Line Outputs and on both Mic inputs. The STAC9752A/9753A implementation of jack sense uses the Extended Paging Registers defined by the AC'97 2.3 Specification. This allows for additional registry space to hold the identification information about the CODEC, the jack sensing details and results, and the external surroundings of the CODEC. The information within the Extended Paging Registers will allow for the automatic configuration of the audio subsystem without end-user intervention. For example, the BIOS can populate the Extended Paging Registers with valuable information for both the audio driver and the operating system such as gain and attenuation stages, input population and input phase. With this input information, the IDT driver will automatically provide to the Volume Control Panel only the vol-
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ume sliders that are implemented in the system, thus improving the end-user's experience with the PC. The information in the Extended Paging Registers will also allow for automatic configuration of microphone inputs, the ability to switch between SPDIF and analog outputs, the routing of the master volume slider to the proper physical output, and SoftEQ configurations. The fully parametric IDT SoftEQ can be initiated upon jack insertion and sensed impedance levels. The STAC9752A/9753A also offers two styles of PC BEEP, Analog and Digital. The digital PC BEEP is a new feature added to the AC'97 Specification Rev 2.3. The STAC9752A/9753A is designed primarily to support stereo (2-speaker) audio. True AC-3 playback can be achieved for 6-speaker applications by taking advantage of the multi-CODEC option available in the AC'97 architecture and supported by the STAC9752A/9753A. Additionally, the STAC9752A/9753A provides for a stereo enhancement feature, IDT Surround 3D (SS3D). SS3D provides the listener with several options for improved speaker separation beyond the normal 2- or 4-speaker arrangements. The STAC9752A/9753A can be SoundBlaster (R) and Windows Sound System (R) compatible when used with IDT's WDM driver for Windows 98/2K/ME/XP or with Intel/Microsoft driver included with Windows 2K/ME/XP. SoundBlaster is a registered trademark of Creative Labs. Windows is a registered trademark of Microsoft Corporation.
1.3.
STAC9752A/9753A Block Diagram
Figure 1. STAC9752A/9753A Block Diagram
M U X
Power Management PCM out DACs
Mic Boost 0,10, 20, or 30 dB Line In
Mic Sensing
Left or Right Channel Stereo or Mono Mic Left or Right Channel Stereo or Mono Mic
PC_BEEP
PHONE
Video
AUX
CD
M U X
AC-link
SYNC BIT_CLK SDATA_OUT SDATA_IN RESET#
DAC
Digital Interface
Registers 64x16 bits
DAC
MIXER
ADC ADC PCM in ADCs Analog mixing and Gain Control
Universal JacksTM Jack Sharing Internal Jack Sense
MONO_OUT
HP_OUT LINE_OUT
Multi-Codec
CID0 CID1
Variable Sample Rate 20-Bit DACs and 20-Bit ADCs
Digital PCBEEP SPDIF Output
Stereo Mono
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1.4.
Key Specifications
* * * * * * * Analog LINE_OUT SNR: 94 dB Digital DAC SNR: 92 dB Digital ADC SNR: 85 dB Full-scale Total Harmonic Distortion: 0.002% Crosstalk between Input Channels: -70 dB Spurious Tone Rejection: 100 dB Stereo Microphone Input
1.5.
Related Materials
* * * Product Brief Reference Designs for MB, AMR, CNR, and ACR applications Audio Precision Performance Plots
1.6.
Additional Support
Additional product and company information can be obtained by going to the IDT web site at: www.IDT.com
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2. CHARACTERISTICS AND SPECIFICATIONS 2.1. Electrical Specifications
2.1.1. Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the STAC9752A/9753A. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Analog maximum supply voltage Digital maximum supply voltage VREFOUT output current Voltage on any pin relative to ground Operating temperature Storage temperature Soldering temperature
Pin
AVdd DVdd 6 Volts 5.5 Volts 5 mA
Maximum Rating
Vss - 0.3 V to Vdd + 0.3 V 0o C to +70o C -55 o C to +125 o C 260 o C for 10 seconds * Soldering temperature information for all available packages begins on page 101.
2.1.2.
Recommended Operation Conditions Parameter Min.
Digital - 3.3 V Analog - 5 V Analog - 3.3 V 3.135 4.75 3.135 0 Tcase (48-LQFP)
Typ.
3.3 5 3.3
Max.
3.465 5.25 3.465 +70 +90
Units
V V V C C
Power Supply Voltage
Ambient Operating Temperature Case Temperature
ESD: The STAC9752A/9753A is an ESD (electrostatic discharge) sensitive device. The human body and test
equipment can accumulate and discharge electrostatic charges up to 4000 Volts without detection. Even though the STAC9752A/9753A implements internal ESD protection circuitry, proper ESD precautions should be followed to avoid damaging the functionality or performance.
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2.1.3.
Power Consumption
Parameter Digital Supply Current + 3.3 V Digital Analog Supply Current + 5 V Analog + 3.3 V Analog Power Down Status PR0 Supply Current PR1 Supply Current PR2 Supply Current PR3 Supply Current PR4 Supply Current PR5 Supply Current PR6 Supply Current Min Typ 35 80 70 TBD TBD TBD TBD TBD TBD TBD Max Unit mA mA mA mA mA mA mA mA mA mA
2.1.4.
AC-Link Static Digital Specifications
(T ambient = 25 C, DVdd = 3.3 V 5%, AVss = DVss = 0 V; 50 pF external load)
Parameter Input Voltage Range Low level input range High level input voltage High level output voltage Low level output voltage Input Leakage Current (AC-Link inputs) Output Leakage Current (Hi-Z AC-Link outputs) Output buffer drive current Symbol Vin Vil Vih Voh Vol Min Typ -0.30 0.65 x DVdd 0.90 x DVdd -10 -10 4 Max DVdd + 0.30 0.35 x DVdd 0.1 x DVdd 10 10 Unit V V V V V A A mA
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2.1.5.
STAC9752A Analog Performance Characteristics
(Tambient = 25C, AVdd = 5.0V5%, DVdd = 3.3V5%, AVss = DVss = 0V; 1KHzinputsinewave; SampleFrequency = 48KHz; 0dB = 1Vrms, 10K / 50pFload, Testbench Characterization BW:20Hz-20KHz, 0dB settings on all gain stages) Parameter Min Typ Max Unit Full Scale Input Voltage: All Analog Inputs except Mic Mic Inputs (Note 1) Full Scale Output: Line Output PCM (DAC) to LINE_OUT MONO_OUT HEADPHONE_OUT (32 load) (peak) Analog S/N: (Note 2) CD to LINE_OUT Other to LINE_OUT D/A to LINE_OUT LINE_IN to A/D with High pass filter enabled Analog Frequency Response (Note 3) Total Harmonic Distortion: (Note 4) CD to LINE_OUT Other to LINE_OUT D/A to LINE_OUT (full scale) LINE_IN to A/D with High pass filter enabled HEADPHONE_OUT A/D & D/A Digital Filter Pass Band (Note 5) A/D & D/A Digital Filter Transition Band A/D & D/A Digital Filter Stop Band A/D & D/A Digital Filter Stop Band Rejection (Note 6) DAC Out-of-Band Rejection (Note 7) Group Delay (48KHz sample rate) Any Analog Input to LINE_OUT Crosstalk (10KHz Signal Frequency) Any Analog Input to LINE_OUT Crosstalk (1KHz Signal Frequency) Spurious Tone Rejection Attenuation, Gain Step Size Input Impedance (Note 8) Input Capacitance VREFout Interchannel Gain Mismatch ADC Interchannel Gain Mismatch DAC Note: 1. 2. 3. 4. 5. 6. 20 84 74 20 19,200 28,800 100 55 70 1.0 0.03 1.0 1.0 1.0 50 94 94 92 85 95 95 84 80 100 100 1.5 50 15 0.5 x AVdd 20,000 19,200 28,800 1 0.5 0.5 Vrms Vrms Vrms Vrms Vrms mW dB dB dB dB Hz dB dB dB dB dB Hz Hz Hz dB dB ms dB dB dB dB
K
pF V dB dB
With +30 dB Boost on, 1.0 Vrms with Boost off Ratio of Full Scale signal to idle channel noise output is measured "A weighted" over a 20 Hz to a 20 KHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio). 1dB limits for Line Output & 0dB gain Ratio of Full Scale signal to THD+N output with -3dB signal, measured "A weighted" over a 20 KHz BW, 48 KHz Sample Frequency 0.25dB limits Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise.
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7. 8.
The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8 to 100 KHz, with respect to a 1 Vrms DAC output. For all inputs except PC BEEP.
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2.1.6.
STAC9753A Analog Performance Characteristics
(Tambient = 25C, AVdd = 5.0V5%, DVdd = 3.3V5%, AVss = DVss = 0V; 1KHzinputsinewave; SampleFrequency = 48KHz; 0dB = 1Vrms, 10K / 50pFload, Testbench Characterization BW:20Hz-20KHz, 0dB settings on all gain stages) Parameter Full Scale Input Voltage: All Analog Inputs except Mic Mic Inputs (Note 1) Full Scale Output: Line Output PCM (DAC) to LINE_OUT MONO_OUT HEADPHONE_OUT (32 load) (peak) Analog S/N: (Note 2) CD to LINE_OUT Other to LINE_OUT D/A to LINE_OUT LINE_IN to A/D with High pass filter enabled Analog Frequency Response (Note 3) Total Harmonic Distortion: (Note 4) CD to LINE_OUT Other to LINE_OUT D/A to LINE_OUT (full scale) LINE_IN to A/D with High pass filter enabled HEADPHONE_OUT A/D & D/A Digital Filter Pass Band (Note 5) A/D & D/A Digital Filter Transition Band A/D & D/A Digital Filter Stop Band A/D & D/A Digital Filter Stop Band Rejection (Note 6) DAC Out-of-Band Rejection (Note 7) Group Delay (48KHz sample rate) Any Analog Input to LINE_OUT Crosstalk (10KHz Signal Frequency) Any Analog Input to LINE_OUT Crosstalk (1KHz Signal Frequency) Spurious Tone Rejection Attenuation, Gain Step Size Input Impedance (Note 8) Input Capacitance VREFout Interchannel Gain Mismatch ADC Interchannel Gain Mismatch DAC Gain Drift Note: 1. 2. Min 20 Typ 1.0 0.03 0.5 0.5 0.5 12.5 93 93 91 85 Max 20,000 Unit Vrms Vrms Vrms Vrms Vrms mW dB dB dB dB Hz
93 dB 93 dB 84 dB 84 dB 74 80 dB 20 19,200 Hz 19,200 28,800 Hz 28,800 Hz 100 dB 55 dB 1 ms 70 dB 100 dB 100 dB 1.5 dB 50 K 15 pF 0.5 x AVdd V 0.5 dB 0.5 dB 100 ppm/C
3.
With +30 dB Boost on, 1.0Vrms with Boost off Ratio of Full Scale signal to idle channel noise output is measured "A weighted" over a 20 Hz to a 20 KHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio).0 dB gain, 20 KHz BW, 48 KHz Sample Frequency 1 dB limits 1dB limits for Line Output & 0 dB gain
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4. 5. 6. 7. 8.
Ratio of Full Scale signal to THD+N output with -3dB signal, measured "A weighted" over a,20 KHz BW, 48 KHz Sample Frequency 0.25dB limits Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8 to 100 KHz, with respect to a 1 Vrms DAC output. For all inputs except PC BEEP.
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2.2.
AC Timing Characteristics
(T ambient = 25 C, AVdd = 3.3V or 5V 5%, DVdd = 3.3V 5%, AVss = DVss = 0V; 75pF external load for BIT_CLK and 60pF external load for SDATA_IN)
2.2.1.
Cold Reset
Figure 2. Cold Reset Timing
Trst2clk Tres_low RESET# Ttri2actv BIT_CLK Ttri2actv SDATA_IN
Parameter RESET# active low pulse width RESET# inactive to SDATA_IN or BIT_CLK active delay RESET# inactive to BIT_CLK startup delay BIT_CLK active to RESET# asserted (Not shown in diagram)
Symbol Tres_low Tri2actv Trst2clk Tclk2rst
Min 1.0 .01628 0.416
Typ -
Max 25 400 -
Units s ns s s
Note: BIT_CLK and SDATA_IN are in a high impedance state during reset.
2.2.2.
Warm Reset
Figure 3. Warm Reset Timing
Tsync_high Tsync_2clk SYNC
BIT_CLK
Parameter SYNC active high pulse width SYNC inactive to BIT_CLK startup delay
Symbol Tsync_high Tsync2clk
Min 1.0 162.8
Typ 1.3 -
Max -
Units s ns
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2.2.3.
Clocks
Figure 4. Clocks Timing
Tclk_low BIT_CLK Tclk_high Tclk_period Tsync_low Tsync_high SYNC Tsync_period
Parameter BIT_CLK frequency BIT_CLK period BIT_CLK output jitter BLT_CLK high pulse width (Note 1) BIT_CLK low pulse width (Note 1) SYNC frequency SYNC period SYNC high pulse width SYNC low pulse width Note: 1. Worst case duty cycle restricted to 45/55.
Symbol Tclk_period Tclk_high Tclk_low Tsync_period Tsync_high Tsync_low
Min 36 36 -
Typ 12.288 81.4 750 40.7 40.7 48.0 20.8 1.3 19.5
Max 45 45 -
Units MHz ns ps ns ns KHz s s s
2.2.4.
STAC9752A/9753A Crystal Elimination Circuit and Clock Frequencies
The STAC9752A/9753A supports several clock frequency inputs as described in the following table. In general, when a 24.576MHz crystal is not used, the XTALOUT pin should be tied to ground. This short to ground configures the part into an alternate clock mode and enables an on board PLL. CODEC Modes: P = The STAC9752A/9753A as a Primary CODEC S = The STAC9752A/9753A as a Secondary CODEC.
Table 1. Clock mode configuration XTL_OUT Pin Config XTAL XTAL or open XTAL or open XTAL or open short to ground short to ground CID1 Pin Config float float pulldown pulldown float float CID0 pin config float pulldown float pulldown float pulldown Clock Source Input 24.576MHz xtal 12.288MHz bit clk 12.288MHz bit clk 12.288MHz bit clk 14.31818MHz source 27MHz source CODEC Mode P S S S P P CODEC ID 0 1 2 3 0 0
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Table 1. Clock mode configuration XTL_OUT Pin Config short to ground short to ground CID1 Pin Config pulldown pulldown CID0 pin config float pulldown Clock Source Input 48MHz source 24.576MHz source CODEC Mode P P CODEC ID 0 0
Table 2. Common Clocks and Sources Clock Source XTAL BIT_CLK VGA Digital Video USB Clock Frequency 24.576MHz 12.288MHz 14.31818MHz 27MHz 48MHz
2.2.5.
Data Setup and Hold
(50pF external load)
Figure 5. Data Setup and Hold Timing
tco BIT_CLK SDATA_OUT SDATA_IN SYNC V ih
Voh Vo l
T setup V il
T hold
Parameter Symbol Min Typ Setup to falling edge of BIT_CLK Tsetup 10 Hold from falling edge of BIT_CLK Thold 10 Output Valid Data from rising edge of BIT_CLK tco Note: Setup and hold time parameters for SDATA_IN are with respect to the AC'97 controller. Max 15 Units ns ns ns
2.2.6.
Signal Rise and Fall Times
(BIT_CLK: 75pF external load; from 10% to 90% of Vdd) (SDATA_IN: 60pF external load; from 10% to 90% of Vdd)
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Figure 6. Signal Rise and Fall Times Timing
BIT_CLK Triseclk Tfallclk
SDATA_IN Trisedin
Parameter BIT_CLK rise time BIT_CLK fall time SDATA_IN rise time SDATA_IN fall time Symbol Triseclk Tfallclk Trisedin Tfalldin
Tfalldin
Min Typ Max 6 6 6 6 Units ns ns ns ns
2.2.7.
AC-Link Low Power Mode Timing
Figure 7. AC-Link Low Power Mode Timing
Slot 1 Slot 2
SYNC BIT_CLK SDATA_OUT SDATA_IN
Write to 0x20
Data PR4
Don't care Ts2_pdown
Note: BIT_CLK not to scale
Parameter End of Slot 2 to BIT_CLK, SDATA_IN low
Symbol Ts2_pdown
Min -
Typ -
Max 1.0
Units s
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2.2.8.
ATE Test Mode
Figure 8. ATE Test Mode Timing
RESET# SDATA_OUT
Tsetup2rst
SDATA_IN, BIT_CLK
Toff
Hi-Z
Parameter Setup to trailing edge of RESET# (also applies to SYNC) Rising edge of RESET# to Hi-Z delay Note: 1.
Symbol Tsetup2rst Toff
Min 15.0 -
Typ -
Max 25.0
Units ns ns
2. 3.
All AC-Link signals are normally low through the trailing edge of RESET#. Bringing SDATA_OUT high for the trailing edge of RESET# causes the STAC9752A/9753A AC-Link outputs to go high impedance, which is suitable for ATE in-circuit testing. Once the test mode has been entered, the STAC9752A/9753A must be issued another RESET# with all AC-Link signals low to return to the normal operating mode. # denotes active low.
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3. TYPICAL CONNECTION AND POWER DIAGRAMS 3.1. STAC9752A/9753A Typical Connection Diagram for 48-pin LQFP
Figure 9. STAC9752A/9753A Typical Connection Diagram 48-pin LQFP
*OPTIONAL
2 *
Ferrite Bead 3.3V 5%
0.1 F
1 F
0.1 F
0.1 F
1 F
0.1 F
(Near Clk source) CLOCK_IN*
OPTIONAL
25 AVdd1
38 AVdd2
1 DVdd1
9 DVdd2 XTL_IN 2 27 pF
24.576 MHz
*Add resistive divider when using 5V clock.
12 PC_BEEP 13 PHONE 14 AUX_L 15 AUX_R 16 VIDEO_L 17 VIDEO_R 18 CD_L 19 CD_GND 20 CD_R VREF 21 MIC1 22 MIC2 23 LINE_IN_L 24 LINE_IN_R GPIO1 32 0.1 F CAP2 GPIO0 LINE_OUT_L LINE_OUT_R 820 pF 29 AFILT1 MONO_OUT HP_OUT_L AFILT2 HP_COMM AVss1 26 AVss2 42 DVss1 4 DVss2 7 HP_OUT_R 40 41 NC NC NC SPDIF 31 33 34 48 44 43 35 36 37 39 RESET# CID0 CID1 EAPD SDATA_OUT BIT_CLK SDATA_IN SYNC 5 6 8 10 11 45 46 47 28 27 XTL_OUT 3 0
27 pF
22
EMI Filter
27 pF TUNE TO LAYOUT
STAC9753
VREFOUT
1 F
1 F*
*OPTIONAL
820 pF
30
HP_COMM should be tied to ground at the headphone pin.
*Terminate ground plane as close to codec as possible
Analog Ground
Digital Ground
Note: Pin 48: To Disable SPDIF, use an 1K - 1 0 K external pullup resistor. Note: The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at about 2.5V. The name of the pin in the AC'97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to ground will change the internal bias of the entire CODEC, and cause significant distortion. If there is no analog CD input, then this pin can be No-Connect.
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3.2.
STAC9752A/9753A Typical Connection Diagram for 32-pad QFN
Figure 10. STAC9752A/9753A Typical Connection Diagram 32-pad QFN
*OPTIONAL
2 *
Ferrite Bead 3.3V 5%
10 F
0.1 F
1 F
0.1 F
26 AVdd2 1 XTL_IN
9 DVdd2
2 EMI Filter 22
SDATA_OUT BIT_CLK
GPIO EAPD/GPIO SPDIF_OUT
30 31 32
3
27 pF TUNE TO LAYOUT
5 7 8
SDATA_IN SYNC RESET#
SPDIF and GPIO PINS
LINK PINS
STAC9753A (3.3V Analog) in 32-pad QFN
VREFOUT VREF
19 18 1 F
22
CAP2
1 F*
*OPTIONAL
0.1 F
VREF PINS
20 AFILT1 MIC1 MIC2 AFILT2 LINE_IN_L LINE_IN_R PHONE CD_L CD_GND CD_R MONO_OUT AVss1 17 LINE_OUT_L LINE_OUT_R HP_OUT_L 13 14 15 16 23 24 27 28
820 pF
820 pF
21
FILTER PINS
9 10 11
STANDARD ANALOG I/O
12 25
AVss2 29
DVss1 4
DVss2 7
HP_OUT_R
UNIVERSAL JACKSTM PINS
*Terminate ground plane as close to codec as possible
Analog Ground
Digital Ground
Note: Pin 48: To Disable SPDIF, use an 1K - 1 0 K external pullup resistor. Note: The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at about 2.5V. The name of the pin in the AC'97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to ground will change the internal bias of the entire CODEC, and cause bad distortion. If there is no analog CD input, then this pin can be No-Connect.
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3.3.
Split Independent Power Supply Operation
In PC applications, one power supply input to the STAC9752A/9753A may be derived from a supply regulator and the other directly from the PCI power supply bus. When power is applied to the PC, the regulated supply input to the IC will be applied some time delay after the PCI power supply. Without proper on-chip partitioning of the analog and digital circuitry, some manufacturer's CODECs would be subject to on-chip SCR type latch-up. IDT's STAC9752A/9753A specifically allows power-up sequencing delays between the analog (AVddx) and digital (VDddx) supply pins. These two power supplies can power-up independently and at different rates with no adverse effects to the CODEC. The IC is designed with independent analog and digital circuitry that prevents on-chip SCR type latch-up. However, the STAC9752A/9753A is not designed to operate for extended periods with only the analog supply active.
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3.4.
Split Independent Power Supply Operation for the 32-pad QFP Package
Figure 11. Split Connection Diagram 32-pad QFN
3.3V or 5V 5% 3.3V 5%
10 F
0.1 F
10 F
0.1 F
26 AVdd2 1 XTL_IN
9 DVdd2
2 EMI Filter 22 3
GPIO SDATA_OUT EAPD/GPI0 BIT_CLK SPDIF_OUT
30 31 32
27 pF TUNE TO LAYOUT
5 7 8
SDATA_IN SYNC RESET#
LINK PINS
22 0.1 F
CAP2
STAC9752A (5V Analog) or STAC9753A (3.3V Analog) in 32-pad QFN
SPDIF and GPIO PINS
VREFOUT VREF
19 18 1 F
1 F*
*OPTIONAL
VREF PINS
MIC1 MIC2 LINE_IN_L 13 14 15 16 23 24 27 28
820 pF
20
AFILT1
820 pF
21 AFILT2
FILTER PINS
9 10 11
PHONE CD_L CD_GND
LINE_IN_R LINE_OUT_L LINE_OUT_R
STANDARD ANALOG I/O
12 25
CD_R HP_OUT_L MONO_OUT HP_OUT_R AVss1 17 AVss2 29 DVss1 4 DVss2 7
UNIVERSAL JACKSTM PINS
*Terminate ground plane as close to codec as possible
Analog Ground
Digital Ground
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4. CONTROLLER, CODEC, AND AC-LINK
This section describes the physical and high-level functional aspects of the AC`97 Controller to CODEC interface, referred to as the AC-Link.
4.1.
AC-Link Physical interface
The STAC9752A/9753A communicates with its companion Digital Controller via the AC-Link digital serial interface. AC-Link has been defined to support connections between a single Controller and up to four CODECs. All digital audio, modem and handset data streams, as well as all control (command/status) information are communicated over this serial interconnect, which consists of a clock (BIT_CLK), frame synchronization (SYNC), serial data in (SDATA_IN), serial data out (SDATA_OUT), and a reset (RESET#).
4.2.
Controller to Single CODEC
The simplest and most common AC`97 system configuration is a point-to-point AC-Link connection between Controller and the STAC9752A/9753A, as illustrated in Figure 12.
Figure 12. AC-Link to its Companion Controller
SYNC BIT_CLK Digital DC'97 Controller SDATA_OUT SDATA_IN RESET# AC'97 Codec
XTAL_IN
XTAL_OUT
A primary CODEC may act as either a source or a consumer of the BIT_CLK, depending on the configuration. While RESET# is asserted, if a clock is present at the BIT_CLK pin for at least five cycles before RESET# is de-asserted, then the CODEC is a consumer of BIT_CLK, and must not drive BIT_CLK when RESET# is de-asserted. The clock is being provided by other than the primary CODEC, for instance by the controller or an independent clock chip. In this case the primary CODEC must act as a consumer of the BIT_CLK signal as if it were a secondary CODEC. This clock source detection must be done each time the RESET# line is asserted. In the case of a warm reset, where the clock is halted but RESET# is not asserted, the CODEC must remember the clock source, and not begin generating the clock on the assertion of SYNC if the CODEC had previously determined that it was a consumer of BIT_CLK. The STAC9752A/9753A uses the XTAL_OUT pin (Pin 3) and the CID0 and CID1 pins (Pins 45 & 46) to determine its alternate clock frequencies. See section2.2.4: page 17 for additional information on Crystal Elimination and for supported clock frequencies.
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If, when the RESET# signal has been de-asserted, the CODEC has not detected a signal on BIT_CLK as defined in the previous paragraph then the AC`97 CODEC derives its clock internally from an externally attached 24.576MHz crystal or oscillator, or optionally from an external 14.318MHz oscillator, and drives a buffered 12.288MHz clock to its digital Controller over AC-Link under the signal name "BIT_CLK". Clock jitter at the DACs and ADCs is a fundamental impediment to high quality output, and the internally generated clock will provide AC`97 components with a clean clock that is independent of the physical proximity of AC`97's Digital Controller (henceforth referred to as "the Controller"). If BIT_CLK begins toggling while the RESET# signal is still asserted, the clock is being provided by other than the primary CODEC, for instance by the controller or by a discrete clock source. In this case, the primary CODEC must act as a consumer of the BIT_CLK signal as if it were a secondary CODEC. The beginning of all audio sample packets, or Audio Frames, transferred over AC-Link is synchronized to the rising edge of the SYNC signal. SYNC is driven by the Controller. The Controller generates SYNC by dividing BIT_CLK by 256 and applying some conditioning to tailor its duty cycle. This yields a 48 KHz SYNC signal whose period defines an audio frame. Data is transitioned on AC-Link on every rising edge of BIT_CLK, and subsequently sampled by the receiving device on the receiving side of AC-Link on each immediately following falling edge of BIT_CLK.
4.3.
Controller to Multiple CODECs
Several vendor specific methods of supporting multiple CODEC configurations on AC-Link have been implemented or proposed, including CODECs with selective AC-Link pass-through and controllers with duplicate AC-Links. Potential implementations include: * * * 6-channel audio using 3 x 2-channel CODECs Separate CODECs for independent audio and modem AFE Docking stations, where one CODEC is in the laptop and another is in the dock
This specification defines support for up to four CODECs on the AC-Link. By definition there can be one Primary CODEC (ID 00) and up to three Secondary CODECs (IDs 01,10, and 11). The CODEC ID functions as a chip select. Secondary devices therefore have completely orthogonal register sets; each is individually accessible and they do not share registers. Multiple CODEC AC-Link implementations must run off a common BIT_CLK. They can potentially save Controller pins by sharing SYNC, SDATA_OUT, and RESET# from the AC`97 Digital Controller. Each device requires its own SDATA_IN pin back to the Controller. This prevents contention of multiple devices on one serial input line. Support for multiple CODEC operation necessitates a specially designed Controller. An AC`97 Digital Controller that supports multiple CODEC configurations implements multiple SDATA_IN inputs, supporting one Primary CODEC and up to three Secondary CODECs.
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4.3.1.
Primary CODEC Addressing
Primary AC`97 CODECs respond to register read and write commands directed to CODEC ID 00 (see Section 4 for details of the Primary and Secondary CODEC addressing protocols). Primary devices must be configurable (by hardwiring, strap pin(s), or other methods) as CODEC ID 00, and reflect this in the two-bit CODEC ID field(s) of the Extended Audio and/or Extended Modem ID Register(s). The Primary CODEC may either drive the BIT_CLK signal or consume a signal provided by the Digital Controller or other clock generator.
4.3.2.
Secondary CODEC Addressing
Secondary AC`97 CODECs respond to register read and write commands directed to CODEC IDs 01, 10, or 11. Secondary devices must be configurable (via hardwiring, strap pin(s), or other methods) as CODEC IDs 01, 10, or 11 in the two-bit field(s) of the Extended Audio and/or Extended Modem ID Register(s). CODECs configured as Secondary must power up with the BIT_CLK pin configured as an input. Using the provided BIT_CLK signal is necessary to ensure that everything on the AC-Link is synchronous. BIT_CLK is the clock source (multiplied by 2 so that the internal rate is 24.576MHz).
4.3.3.
CODEC ID Strapping
Audio CODECs in the 48-pin package use pins 45 and 46 (defined as ID0# and ID1#) as strapping (i.e. configuration) pins to configure the CODEC ID. The ID0# and ID1# strapping bits adopt inverted polarity and default to 00 = Primary (via a weak internal pullup) when left floating. This eliminates the need for external resistors for CODECs configured as Primary, and maintains backward compatibility with existing layouts that treat pins 45 and 46 as "no connect" or a capacitor connected to ground. Pulldowns are typically 0-10 K and connected to Digital (not Analog) Ground.
Table 3. Recommended CODEC ID strapping CID1 (pin 46) NC NC pulldown pulldown CID0 (pin 45) NC pulldown NC pulldown Configuration Primary ID 00 Secondary ID 01 Secondary ID 10 Secondary ID 11
4.4.
Clocking for Multiple CODEC Implementations
To keep the system synchronous, all Primary and Secondary CODEC clocking must be derived from the same clock source, so they are operating on the same time base. In addition, all AC-Link protocol timing must be based on the BIT_CLK signal, to ensure that everything on the AC-Link will be synchronous.
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The following are potential 24.576MHz clock options available to a Secondary CODEC: * * * Using an external 24.576 MHz signal source (external oscillator or AC`97 Digital Controller) Using the Primary's crystal out Using the Primary's BIT_CLK output to derive 24.576MHz See section 2.2.4: page17 for clock frequencies supported and configurations.
4.5.
STAC9752A/9753A as a Primary CODEC
Primary devices are required to support correctly either of the following clocking options: * * * 24.576MHz crystal attached to XTAL_IN and XTAL_OUT 24.576MHz external oscillator provided to XTAL_IN 12.288MHz oscillator provided to the BIT_CLK input
The Primary device may also optionally support the following clocking option: * 14.318MHz external oscillator provided to XTAL_IN See section 2.2.4: page17 for clock frequencies supported and configurations.
4.5.1.
STAC9752A/9753A as a Secondary CODEC
Secondary devices are required to function correctly using one or more of the following clocking options: * * 24.576MHz external oscillator provided to XTAL_IN (synchronous and in phase with Primary 24.576MHz clock) BIT_CLK input provided by the Primary. In this mode, a clock at XTAL_IN (Pin 2) is ignored. See section 2.2.4: page17 for clock frequencies supported and configurations.
4.6.
AC-Link Power Management
Powering down the AC-Link
The AC-Link signals can be placed in a low power mode. When AC`97's Powerdown Register (26h) is programmed to the appropriate value, both BIT_CLK and SDATA_IN are brought to and held at a logic low voltage level. After signaling a reset to AC`97, the AC`97 Controller should not attempt to play or capture audio data until it has sampled a CODEC Ready indication from AC`97.
4.6.1.
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Figure 13. STAC9752A/9753A Powerdown Timing
SYNC BIT_CLK SDATA_OUT SDATA_IN
Note: BIT_CLK not to scale
slot 2 per frame
TAG
Write to 0x20
DATA PR4
slot 2 per frame
TAG
BIT_CLK and SDATA_IN are transitioned low immediately following decode of the write to the Powerdown Register (26h) with PR4. When the AC`97 Controller driver is at the point where it is ready to program the AC-Link into its low power mode, slots 1 and 2 are assumed to be the only valid stream in the audio output frame. After programming the AC`97 device to this low power, halted mode, the AC`97 Controller is required to drive and keep SYNC and SDATA_OUT low. Once the AC`97 CODEC has been instructed to halt BIT_CLK, a special "wake-up" protocol must be used to bring the AC-Link to the active mode since normal audio output and input frames can not be communicated in the absence of BIT_CLK.
4.6.2.
Waking up the AC-Link
There are two methods for bringing the AC-Link out of a low power, halted mode. Regardless of the method, it is the AC`97 Controller that performs the wake-up task.
4.6.2.1.
Controller Initiates Wake-up
AC-Link protocol provides for a "Cold AC`97 Reset", and a "Warm AC`97 Reset". The current powerdown state would ultimately dictate which form of AC`97 reset is appropriate. Unless a "cold" or "register" reset (a write to the Reset Register) is performed, wherein the AC`97 registers are initialized to their default values, registers are required to keep state during all powerdown modes. Once powered down, re-activation of the AC-Link via re-assertion of the SYNC signal must not occur for a minimum of four audio frame times following the frame in which the powerdown was triggered. When AC-Link powers up the CODEC indicates readiness via the CODEC Ready bit (input slot 0, bit 15).
4.6.2.2.
CODEC Initiates Wake-up
The STAC9752A/9753A (running off Vaux) can trigger a wake event (PME#) by transitioning SDATA_IN from low to high and holding it high until either a warm or cold reset is observed on the
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AC-Link. This functionality is typically implemented in modem CODECs that detect ring, Caller ID, etc. Note that when the AC-Link is either programmed to the low power mode or shut off completely, BIT_CLK may stop if the primary CODEC is supplying the clock, which shuts down the AC-Link clock to the Secondary CODEC1. In order for a Secondary CODEC to react to an external event (phone ringing), it must support an independent clocking scheme for any PME# associated logic that must be kept alive when the AC-Link is down. This includes logic to asynchronously drive SDATA_IN to a logic high-level, which signals a wake request to the AC`97 Digital Controller.
4.6.3.
CODEC Reset
There are three types of AC`97 reset: * * * a cold reset where all AC`97 logic (most registers included) is initialized to its default state a warm reset where the contents of the AC`97 register set are left unaltered a register reset which only initializes the AC`97 registers to their default states
4.6.3.1.
Cold AC`97 Reset
A cold reset is achieved by asserting RESET# low for the minimum specified time, then subsequently de-asserting RESET# high. BIT_CLK and SDATA_IN will be activated, or re-activated as the case may be, and all AC`97 control registers will be initialized to their default power on reset values. RESET# is an asynchronous AC`97 input.
4.6.3.2.
Warm AC`97 Reset
A warm AC`97 reset will re-activate the AC-Link without altering the current AC`97 register values. A warm reset is signaled by driving SYNC high for a minimum of 1 s in the absence of BIT_CLK. Within normal audio frames SYNC is a synchronous AC`97 input. However, in the absence of BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to AC`97. AC`97 MUST NOT respond with the activation of BIT_CLK until SYNC has been sampled low again by AC`97. This will preclude the false detection of a new audio frame.
4.6.3.3.
Register AC`97 Reset
Most registers in an AC97 device can be restored to their default values by performing a write (any value) to the Reset Register, 00h.
1.
Secondary CODEC always configures its BIT_CLK pin as an input.
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5. AC-LINK DIGITAL INTERFACE 5.1. Overview
AC-Link is the 5-pin digital serial interface that links AC`97 CODEC to the Controller. The AC-Link protocol is a bi-directional, fixed clock rate, serial digital stream. AC-Link handles multiple input and output PCM audio streams, as well as control register accesses employing a time division multiplexed (TDM) scheme that divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. The STAC9752A/9753A DACs, ADCs, and SPDIF can be assigned to slots 3&4, 6&9, 7&8 or 10&11.
Figure 14. Bi-directional AC-Link Frame with Slot assignments
SLOTS SYNC OUTGOING STREAMS
(Controller output - SDATA_OUT)
0
1
2
3
4
5
6
7
8
9
10
11
12
TAG
CMD ADDR
CMD DATA
PCM LEFT
PCM RT
NA
PCM CTR
PCM LSURR
PCM RSURR
PCM LFE
SPDIF
SPDIF
IO CTRL
TAG
INCOMING STREAMS
(codec output - SDATA_IN)
STATUS ADDR
STATUS DATA
PCM LEFT
PCM RT
LINE1 ADC
PCM MIC
Vendor RSVD
Vendor RSVD
Vendor RSVD
LINE2 ADC
HSET ADC
IO STATUS
TAG PHASE
DATA PHASE
Slot 12 can be used by the AC'97 Codec if a Modem Codec is not present.
Table 4. AC-Link Output Slots (transmitted from the Controller) Slot 0 1 2 3, 4 5 Name SDATA_OUT TAG Control CMD ADDR write port Control DATA write port PCM L&R DAC playback Modem Line 1 DAC Description MSBs indicate which slots contain valid data; LSBs convey CODEC ID Read/write command bit plus 7-bit CODEC register address 16-bit command register write data 20-bit PCM data for Left and Right channels 16-bit modem data for modem Line 1 output
6, 7, 8, 9 PCM Center, Surround L&R, LFE 20-bit PCM data for Center, Surround L&R, LFE channels 10 Modem Line 2 DAC 16-bit modem data for modem Line 2 output 11 Modem handset DAC 16-bit modem data for modem Handset output
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Table 4. AC-Link Output Slots (transmitted from the Controller) Slot 12 12 10-11 10-12 Name Modem IO control CODEC IRQ SPDIF Out Double Rate Audio Description GPIO write port for modem Control Can be used by CODEC if a modem CODEC is not present. Optional AC-Link bandwidth for SPDIF output Optional AC-Link bandwidth for 88.2 or 96KHz on L, C, R channels
Table 5. The AC-Link Input Slots (transmitted from the CODEC) Slot 0 1 2 3, 4 5 6-11 12 Name SDATA_IN TAG STATUS ADDR read port STATUS DATA read port PCM L&R ADC record Modem Line 1 ADC PCM ADC Record GPIO Status Description MSBs indicate which slots contain valid data MSBs echo register address; LSBs indicate which slots request data 16-bit command register read data 20-bit PCM data from Left and Right inputs 16-bit modem data from modem Line1 input 20-bit PCM data - Alternative Slots for Input GPIO read port and interrupt status
5.2.
AC-Link Serial Interface Protocol
The AC`97 Controller signals synchronization of all AC-Link data transactions. The AC`97 CODEC, Controller, or external clock source drives the serial bit clock onto AC-Link, which the AC`97 Controller then qualifies with a synchronization signal to construct audio frames. SYNC, fixed at 48KHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz, provides the necessary clocking granularity to support twelve 20-bit outgoing and incoming time slots. AC-Link serial data is transitioned on each rising edge of BIT_CLK. The receiver of AC-Link data (CODEC for outgoing data and Controller for incoming data) samples each serial bit on the falling edges of BIT_CLK. The AC-Link protocol provides for a special 16-bit time slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. If a slot is tagged invalid, it is the responsibility of the source of the data, (AC`97 CODEC for the input stream, AC`97 Controller for the output stream), to stuff all bit positions with 0s during that slot's active time. SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The portion of the audio frame where SYNC is high is defined as the "Tag Phase". The remainder of the audio frame where SYNC is low is defined as the "Data Phase". Additionally, for power savings, all clock, sync, and data signals can be halted. This requires that an AC`97 CODEC be implemented as a static design to allow its register contents to remain intact when entering a power savings mode.
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5.2.1.
AC-Link Variable Sample Rate Operation
The AC-Link serial interconnect defines a digital data and control pipe between the Controller and the CODEC. The AC-Link supports twelve 20-bit slots at 48KHz on SDATA_IN and SDATA_OUT. The time division multiplexed (TDM) "slot-based" architecture supports a per-slot valid tag infrastructure that the source of each slot's data sets or clears to indicate the validity of the slot data within the current audio frame. This tag infrastructure can be used to support transfers between Controller and CODEC at any sample rate.
5.2.2.
Variable Sample Rate Signaling Protocol
AC-Link's tag infrastructure imposes FIFO requirements on both sides of the AC-Link. For example, in passing a 44.1KHz stream across the AC-Link, for every 480 audio output frames that are sent across, 441 of them must contain valid sample data. Does the AC`97 Digital Controller pass all 441 PCM samples followed by 39 invalid slots? Or does the AC`97 Digital Controller evenly interleave valid and non-valid slots? Each possible method brings with it different FIFO requirements. To achieve interoperability between AC`97 Digital Controllers and CODECs designed by different manufacturers, it is necessary to standardize the scheme for at least one side of the AC-Link so that the FIFO requirements will be common to all designs. The CODEC side of the AC-Link is the focus of this standardization. The new standard approach calls for the addition of "on demand" slot request flags. These flags are passed from the CODEC to the AC`97 Digital Controller during every audio input frame. Each time the AC`97 Digital Controller sees one or more of the newly-defined slot request flags set active (low) in a given audio input frame, it knows that it must pass along the next PCM sample for the corresponding slot(s) in the AC-Link output frame that immediately follows. The VRA (Variable Rate Audio) bit in the Extended Audio Status and Control Register must be set to 1 to enable variable sample rate audio operation. Setting the VRA = 1 has two functions: 1. 2. Enables PCM DAC/ADC conversions at variable sample rates by write enabling Sample Rate Registers 2C-34h. Enables the on demand CODEC-to-Controller signaling protocol using SLOTREQ bits that becomes necessary when a DAC's sample rate varies from the 48KHz AC-Link serial frame rate.
The table below summarizes the behavior:
Table 6. VRA Behavior AC`97 Functionality SLOTREQ bits sample rate registers VRA = 0 always 0 (data each frame) forced to 48KHz VRA = 1 0 or 1 (data on demand) writable
Note: If more than one CODEC is being used with the SAME controller DMA engine, VRA should NOT be used.
For variable sample rate output, the CODEC examines its sample rate control registers, the state of its FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each AC-Link output frame to determine which SLOTREQ bits to set active (low). SLOTREQ bits asserted during the current
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AC-Link input frame signal which active output slots require data from the AC`97 Digital Controller in the next audio output frame. An active output slot is defined as any slot supported by the CODEC that is not in a power-down state. For fixed 48KHz operation the SLOTREQ bits are always set active (low) and a sample is transferred in each frame. For variable sample rate input, the tag bit for each input slot indicates whether valid data is present or not. Thus, even in variable sample rate mode, the CODEC is always the master: for SDATA_IN (CODEC to Controller), the CODEC sets the TAG bit; for SDATA_OUT (Controller to CODEC), the CODEC sets the SLOTREQ bit and then checks for the TAG bit in the next frame. The VRM (Variable Rate Mic Audio) bit in the Extended Audio Status and Control Register controls the optional MIC ADC input behavior in the same way that VRA = 1 controls the PCM ADC.
5.2.2.1.
SLOTREQ Behavior and Power Management
SLOTREQ bits for fixed rate, powered down, and all unsupported Slots should be driven with 0s for maximum compatibility with the original AC '97 Component Specification. When a DAC channel is powered down, it disappears completely from the serial frame: output tag and slot are ignored, and the SLOTREQ bit is absent (forced to zero). When the Controller wants to power-down a channel, all it needs to do is: 1. 2. Disable source of DAC samples in Controller Set PR bit for DAC channel in Registers 26h, 2Ah, or 3Eh
When it wants to power up the channel, all it needs to do is: 1. 2. Clear PR bit for DAC channel in Registers 26h, 2Ah, or 3Eh Enable source of DAC samples in Controller
5.2.3.
Primary and Secondary CODEC Register Addressing
The 2-bit CODEC ID field in the LSBs of Output Slot 0 is an addition to the original AC-Link protocol that enables an AC`97 Digital Controller to independently access Primary and Secondary CODEC registers. For Primary CODEC access, the AC`97 Digital Controller: 1. 2. 3. 4. Sets the AC-Link Frame valid bit (Slot 0, bit 15). Validates the tag bits for Slot 1 and 2 Command Address and Data (Slot 0, bits 14 and 13). Sets a zero value (00) into the CODEC ID field (Slot 0, bits 1 and 0). Transmits the desired Primary CODEC Command Address and Command Data in Slots 1 and 2.
For Secondary CODEC access, the AC`97 Digital Controller: 1. Sets the AC-Link Frame valid bit (Slot 0, bit 15).
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2. 3.
Places a non-zero value (01, 10, or 11) into the CODEC ID field (Slot 0, bits 1 and 0). Transmits the desired Secondary CODEC Command Address and Command Data in Slots 1 and 2.
Secondary CODECs disregard the Command Address and Command Data (Slot 0, bits 14 and 13) tag bits. In a sense the Secondary CODEC ID field functions as an alternative Valid Command Address (for Secondary reads and writes) and Command Data (for Secondary writes) tag indicator. Secondary CODECs must monitor the Frame Valid bit, and ignore the frame (regardless of the state of the Secondary CODEC ID bits) if it is not valid. AC`97 Digital Controllers should set the frame valid bit for a frame with a Secondary register access, even if no other bits in the output tag slot except the Secondary CODEC ID bits are set.
5.3.
AC-Link Output Frame (SDATA_OUT)
The AC-Link output frame data streams correspond to the multiplexed bundles of all digital output data targeting AC`97's DAC inputs, and control registers. As mentioned earlier, each AC-Link output frame supports up to twelve 20-bit outgoing data time slots. Slot 0 is a special reserved time slot containing 16-bits which are used for AC-Link protocol infrastructure. Figure 15 illustrates the time slot based AC-Link protocol.
Figure 15. AC-Link Audio Output Frame
Data Phase Tag Phase 20.8 uS (48 kHZ)
SYNC BIT_CLK SDATA_OUT
12.288 MHz
valid Frame
slot1
slot2
slot(12)
"0"
CID1
CID0
19
"0"
19
"0"
19
"0"
19
"0"
End of previous audio frame Time Slot "Valid" Bits ("1" = time slot contains valid PCM data) Slot 1 Slot 2 Slot 3 Slot 12
A new AC-Link output frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AC`97 CODEC samples the assertion of SYNC. This falling edge marks the time when both sides of AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC`97 Controller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the AC`97 CODEC on the following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned.
Figure 16. Start of an Audio Output Frame
SDATA_OUT's composite stream is MSB justified (MSB first) with all non-valid slots' bit positions stuffed with 0s by the AC`97 Controller. If there are less than 20 valid bits within an assigned and
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SYNC asserted
SYNC detected by codec
first SDATA_OUT bit of frame
SYNC B IT _ C L K SDATA_OUT
End of previous audio frame
valid Frame
slot1
slot2
valid time slot, the AC`97 Controller always stuffs all trailing non-valid bit positions of the 20-bit slot with 0s. As an example, consider an 8-bit sample stream that is being played out to one of the STAC9752A/ 9753A DACs. The first 8-bit positions are presented to the DAC (MSB justified) followed by the next 12 bit-positions which are stuffed with 0s by the AC`97 Controller. This ensures that regardless of the resolution of the implemented DAC (16, 18 or 20-bit), no DC biasing will be introduced by the least significant bits. When mono audio sample streams are output from the AC`97 Controller it is necessary that BOTH left and right sample stream time slots be filled with the same data.
5.3.1.
Slot 0: TAG / CODEC ID
Table 7. Output Slot 0 Bit Definitions Bit 15 14 13 12-3 12 11 10 9 8 7 6 5 4 3 2 1-0 Description Frame Valid Slot 1 Primary CODEC Valid Command Address bit (Primary CODEC only) Slot 2 Primary CODEC Valid Command Data bit (Primary CODEC only) Slot 3-12 Valid Data bits Slot 3: PCM Left channel Slot 4: PCM Right channel Slot 5: Modem Line 1 (not used on STAC9752A/9753A) Slot 6: Alternative PCM1 Left Slot 7: Alternative PCM2 Left Slot 8: Alternative PCM2 Right Slot 9: Alternative PCM1 Right Slot 10: SPDIF Left Slot 11: SPDIF Right Slot 12: Audio GPIO Reserved (Set to 0) 2-bit CODEC ID field (00 reserved for Primary; 01, 10, 11 indicate Secondary)
Note: The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
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Within slot 0 the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the entire audio frame. If the "Valid Frame" bit is a 1, this indicates that the current audio frame contains at least one time slot of valid data. The next 12 bit positions sampled by AC`97 indicate which of the corresponding 12 time slots contain valid data. In this way data streams of differing sample rates can be transmitted across AC-Link at its fixed 48 KHz audio frame rate. The two LSBs of Slot 0 transmit the CODEC ID used to distinguish Primary and Secondary CODEC register access.
5.3.2.
Slot 1: Command Address Port
The command port is used to control features, and monitor status (see AC-Link input frame Slots 1 and 2) for AC`97 CODEC functions including, but not limited to, mixer settings, and power management (refer to the control register section of this specification). The control interface architecture supports up to 64 16-bit read/write registers, addressable on even byte boundaries. Only the even registers (00h, 02h, etc.) are currently defined, odd register (01h, 03h, etc.) accesses are reserved for future expansion. Note that shadowing of the control register file on the AC`97 Controller is an option left open to the implementation of the AC`97 Controller. The AC`97 CODEC's control register file is nonetheless required to be readable as well as writeable to provide more robust testability. AC-Link output frame slot 1 communicates control register address, and write/read command information to the STAC9752A/9753A.
Table 8. Command Address Port Bit Assignments Bit 19 18:12 11:0 Description Read/Write command Control Register Index Reserved Comments 1 = read, 0 = write sixty-four 16-bit locations, addressed on even byte boundaries Stuffed with 0s
The first bit (MSB) sampled by AC`97 indicates whether the current control transaction is a read or a write operation. The following 7 bit positions communicate the targeted control register address. The trailing 12 bit positions within the slot are reserved and must be stuffed with 0s by the AC`97 Controller.
5.3.3.
Slot 2: Command Data Port
The command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle. (as indicated by Slot 1, bit 19) * * Bit(19:4) Control Register Write Data (Stuffed with 0s if current operation is a read) Bit(3:0) Reserved (Stuffed with 0s)
If the current command port operation is a read then the entire slot time must be stuffed with 0s by the AC`97 Controller.
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5.3.4.
Slot 3: PCM Playback Left Channel
AC-Link output frame slot 3 is the composite digital audio left playback stream. In a typical "Games Compatible" PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the AC`97 Controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20-bits is transferred, the AC`97 Controller must stuff all trailing non-valid bit positions within this time slot with 0s. The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
5.3.5.
Slot 4: PCM Playback Right Channel
AC-Link output frame slot 4 is the composite digital audio right playback stream. In a typical "Games Compatible" PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the AC`97 Controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20-bits is transferred, the AC`97 Controller must stuff all trailing non-valid bit positions within this time slot with 0s. The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
5.3.6.
Slot 5: NOT USED (Modem Line 1 Output Channel)
Audio output frame slot 5 is reserved for modem operation and is not used by the STAC9752A/ 9753A .
5.3.7.
Slot 6 -11: DAC
The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
5.3.8.
Slot 12: Audio GPIO Control Channel
AC-Link output frame slot 12 contains the audio GPIO control outputs.
5.4.
AC-Link Input Frame (SDATA_IN)
The AC-Link input frame data streams correspond to the multiplexed bundles of all digital input data targeting the AC`97 Controller. As is the case for an audio output frame, each AC-Link input frame consists of twelve 20-bit time slots. Slot 0 is a special reserved time slot containing 16-bits which are used for AC-Link protocol infrastructure. The following diagram illustrates the time slot-based AC-Link protocol.
Figure 17. STAC9752A/9753A Audio Input Frame
A new AC-Link input frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AC`97 CODEC samples the assertion of SYNC. This falling edge marks the time when both sides of
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Data Phase Tag Phase 20.8 uS (48 kHZ)
SYNC BIT_CLK SDATA_IN
12.288 MHz
valid Frame
slot1
slot2
slot(12)
"0"
"0"
"0"
19
"0"
19
"0"
19
"0"
19
"0"
End of previous audio frame Time Slot "Valid" Bits ("1" = time slot contains valid PCM data) Slot 1 Slot 2 Slot 3 Slot 12
AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC`97 CODEC transitions SDATA_IN into the first bit position of slot 0 ("CODEC Ready" bit). Each new bit position is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the AC`97 Controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned.
Figure 18. Start of an Audio Input Frame
SYNC detected first SDATA_OUT bit of frame
SYNC BIT_CLK SDATA_IN
End of previous audio frame
Codec Ready
slot1
slot2
SDATA_IN's composite stream is MSB justified (MSB first) with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0s by the AC`97 CODEC. SDATA_IN data is sampled on the falling edges of BIT_CLK.
5.4.1.
Slot 0: TAG
Within slot 0, the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the AC`97 CODEC is in the "CODEC Ready" state or not. If the "CODEC Ready" bit is a 0, this indicates that the AC`97 CODEC is not ready for normal operation. This condition is normal following the deassertion of power on reset for example, while the AC`97 CODEC's voltage references settle. When the AC-Link "CODEC Ready" indicator bit is a 1 it indicates that the AC-Link and AC`97 CODEC control and status registers are in a fully operational state. CODEC must assert "CODEC Ready" within 400 s after it starts receiving valid SYNC pulses from the controller, to provide indication of connection to the link and Control/Status registers are available for access. The AC'97 Controller and related software must wait until all of the lower four bits of the Control/Status Register, 26h, are set
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before attempting any register writes, or attempting to enable any audio stream, to avoid undesirable audio artifacts. Prior to any attempts at putting an AC`97 CODEC into operation, the AC`97 Controller should poll the first bit in the AC-Link input frame (SDATA_IN slot 0, bit 15) for an indication that CODEC has gone "CODEC Ready". Once an AC`97 CODEC is sampled "CODEC Ready" 1 then the next 12 bit positions sampled by the AC`97 Controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data.
5.4.2.
Slot 1: Status Address Port / SLOTREQ Signaling Bits 5.4.2.1. Status Address Port
The status port is used to monitor status for the STAC9752A/9753A functions including, but not limited to, mixer settings and power management. AC-Link input frame slot 1's stream echoes the control register index, for historical reference, for the data to be returned in slot 2. (Assuming that slots 1 and 2 had been tagged "valid" by the AC`97 CODEC during slot 0.
Table 9. Status Address Port Bit Assignments Bit 19 18:12 11:2 1:0 Description Reserved Control Register Index SLOTREQ Reserved Comments Stuffed with 0s Echo of register index for which data is being returned See Section5.4.2.2: page40 Stuffed with 0s
The first bit (MSB) generated by AC`97 is always stuffed with a 0. The following 7 bit positions communicate the associated control register address, the next 10 bits support AC`97's variable sample rate signaling protocol, and the trailing 2 bit positions are stuffed with 0s by AC`97.
5.4.2.2.
SLOTREQ signaling bits
AC-Link input frame Slot #1, the Status Address Port, now delivers CODEC control register read address and variable sample rate slot request flags for all output slots. Ten of the formerly reserved least significant bits have been defined as data request flags for output slots 3-12. The AC-Link input frame Slot 1 tag bit is independent of the bit 11-2 slot request field, and ONLY indicates valid Status Address Port data (Control Register Index). The CODEC should only set SDATA_IN tag bits for Slot 1 (Address) and Slot 2 (Data) to 1 when returning valid data from a previous register read. They should otherwise be set to 0. SLOTREQ bits have validity independent of the Slot 1 tag bit.
1. There are several subsections within an AC`97 CODEC that can independently go busy/ready. It is the responsibility of the AC'97 Controller to probe more deeply into the AC`97 CODEC's register file to determine which subsections are actually ready.
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SLOTREQ bits are always 0 in the following cases * * Fixed rate mode (VRA = 0) Inactive (powered down) ADC channel
SLOTREQ bits are only set to 1 by the CODEC in the following case * Variable rate audio mode (VRA = 1) AND active (power ready) ADC AND a non-48KHz ADC sample rate and CODEC does not need a sample
5.4.3.
Slot 2: Status Data Port
The status data port delivers 16-bit control register read data.
Table 10. Status Data Port Bit Assignments Bit 19:4 3:0 Description Control Register Read Data Reserved Comments Stuffed with 0s if tagged "invalid" Stuffed with 0s
If Slot 2 is tagged invalid by AC`97, then the entire slot will be stuffed with 0s by AC`97.
5.4.4.
Slot 3: PCM Record Left Channel
Audio input frame slot 3 is the left channel output of STAC9752A/9753A input MUX, post-ADC. STAC9752A/9753A ADCs are implemented to support 20-bit resolution. NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
5.4.5.
Slot 4: PCM Record Right Channel
Audio input frame slot 4 is the right channel output of STAC9752A/9753A input MUX, post-ADC. STAC9752A/9753A ADCs are implemented to support 20-bit resolution. NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
5.4.6.
Slot 5: NOT USED (Modem Line 1 ADC)
Audio input frame slot 5 is not used by the STAC9752A/9753A and is always stuffed with 0s.
5.4.7.
Slot 6-9: ADC
The left and right ADC channels of the STAC9752A/9753A may be assigned to slots 6&9 by Register 6Eh. NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
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5.4.8.
Slots 7-8: Vendor Reserved
The left and right ADC channels of the STAC9752A/9753A may be assigned to slots 7&8 by Register 6Eh. NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
5.4.9.
Slot 10 & 11: ADC
The left and right ADC channels of the STAC9752A/9753A may be assigned to slots 10&11 by Register 6Eh. NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
5.4.10.
Slot 12: Reserved
AC-Link input frame slot 12 contains the GPIO status inputs and allows for audio interrupts. Slot 12 can be used by the AC'97 CODEC is a modem CODEC is not present.
5.5.
AC-Link Interoperability Requirements and Recommendations
"Atomic slot" Treatment of Slot 1 Address and Slot 2 Data
Command or Status Address and Data cannot be split across multiple AC-Link frames. The following transactions require that valid Slot 1 Address and valid Slot 2 Data be treated as "atomic" (inseparable) with Slot 0 Tag bits for Address and Data set accordingly (that is, both valid): 1. 2. AC`97 Digital Controller write commands to Primary CODECs AC`97 CODEC status responses
5.5.1.
Whenever the AC`97 Digital Controller addresses a Primary CODEC or an AC`97 CODEC responds to a read command, Slot 0 Tag bits should always be set to indicate actual Slot 1 and Slot 2 data validity.
Table 11. Primary CODEC Addressing: Slot 0 Tag Bits Function AC`97 Digital Controller Primary Read Frame N, SDATA_OUT AC`97 Digital Controller Primary Write Frame N, SDATA_OUT AC`97 CODEC Status Frame N+1, SDATA_IN Slot 0, bit 15 Slot 0, bit 14 Slot 0, bit 13 Slot 0, Bits 1-0 (Valid Frame) (Valid Slot 1 Address) (Valid Slot 2 Data) (CODEC ID) 1 1 0 00
1 1
1 1
1 1
00 00
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When the AC`97 Digital Controller addresses a Secondary CODEC, the Slot 0 Tag bits for Address and Data must be 0. A non-zero, 2-bit CODEC ID in the LSBs of Slot 0 indicates a valid Read or Write Address in Slot 1, and the Slot 1 R/W bit indicates presence or absence of valid Data in Slot 2.
Table 12. Secondary CODEC Addressing: Slot 0 tag bits Function AC`97 Digital Controller Secondary Read Frame N, SDATA_OUT AC`97 Digital Controller Secondary Write Frame N, SDATA_OUT AC`97 CODEC Status Frame N+1, SDATA_IN Slot 0, bit 15 Slot 0, bit 14 Slot 0, bit 13 Slot 0, Bits 1-0 (Valid Frame) (Valid Slot 1 Address) (Valid Slot 2 Data) (CODEC ID) 1 0 0 01, 10, or 11
1 1
0 1
0 1
01, 10, or 11 00
5.6.
Slot Assignments for Audio
Figure 19. Bi-directional AC-Link Frame with Slot assignments
SLOTS SYNC OUTGOING STREAMS
(Controller output - SDATA_OUT) CMD ADDR CMD DATA PCM LEFT PCM RT PCM CTR PCM LSURR
PCM RSURR
0
1
2
3
4
5
6
7
8
9
10
11
12
TAG
NA
PCM LFE
SPDIF
SPDIF
IO CTRL
TAG
INCOMING STREAMS
(codec output - SDATA_IN)
STATUS ADDR
STATUS DATA
PCM LEFT
PCM RT
LINE1 ADC
PCM MIC
Vendor RSVD
Vendor RSVD
Vendor RSVD
LINE2 ADC
HSET ADC
IO STATUS
TAG PHASE
DATA PHASE
Slot 12 can be used by the AC'97 Codec if a Modem Codec is not present.
The AC-link output slots (transmitted to the Codec) are defined as follows:
Table 13. AC-Link Output Slots Dedicated To CODEC Slot 0 1 2 3,4 5 6,7,8,9 Name Description
SDATA_OUT TAG MSBs indicate which slots contain valid data; LSBs convey Codec ID Control CMD ADDR write port Read/write command bit plus 7-bit Codec register address Control DATA write port PCM L & R DAC playback Modem Line 1 DAC PCM Center, Rear, LFE 16-bit command register write data 16, 18, or 20-bit PCM data for left and right channels 16-bit modem data for modem line 1 output 16, 18, or 20-bit PCM data for Center, L & R Rear, LFE channels
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Table 13. AC-Link Output Slots Dedicated To CODEC Slot 10 11 12 10-12 Name Modem Line 2 DAC Modem handset DAC Modem IO control Double rate audio Description 16-bit modem data for modem line 2 output 16-bit modem data for modem handset output GPIO write port for modem control Optional AC-link bandwidth for 88.2 or 96 kHz on L, C, R channels
The AC-link input slots (transmitted from the Codec) are defined as follows:
Figure 20. AC-Link Input Slots Dedicated To CODEC Slot 0 1 2 3,4 5 Name SDATA_IN TAG STATUS ADDR read port STATUS DATA read port PCM L & R ADC record Modem Line 1 ADC Description MSBs indicate which slots contain valid data MSBs echo register address; LSBs indicate which slots request data 16-bit command register read data 16-bit PCM data from left and right inputs 16-bit modem data from modem line 1 input 16-bit PCM data from optional 3rd ADC input Vendor specific (enhanced input for docking, array mic, etc) 16-bit modem data from modem line 2 input 16-bit modem data for modem handset input GPIO read port for modem control
6 Dedicated Microphone ADC 7,8,9 Vendor reserved 10 11 12 Modem Line 2 ADC Modem handset input Modem IO status
Note: The DAC & ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11. The AC-Link output slots dedicated to audio are defined as follows:
Table 14. AC-Link Output Slots Dedicated To Audio Slot 3 4 6 7 8 9 10:11 12 Name PCM L DAC playback PCM R DAC playback PCM Center PCM L Surround PCM R Surround PCM LFE SPDIF Out Reserved Description 20-bit PCM data for left channel 20-bit PCM data for right channel 20-bit PCM data for Center channel 20-bit PCM data for L Surround channel 20-bit PCM data for R Surround channel 20-bit PCM data for LFE channel 20-bit SPDIF Output Reserved
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The AC-Link input slots dedicated to audio are defined as follows:
Table 15. AC-Link Input Slots Dedicated To Audio Slot 3 4 6 7 8 9 12 Name PCM L ADC record PCM R ADC record Dedicated Microphone ADC Vendor reserved Vendor reserved Vendor reserved Audio Interrupt Description 20-bit PCM data from left input 20-bit PCM data from right inputs 20-bit PCM data from optional 3rd ADC input Vendor specific (enhanced input for docking, array mic, etc.) Vendor specific (enhanced input for docking, array mic, etc.) Vendor specific (enhanced input for docking, array mic, etc.) Provides optional interrupt capability for Audio CODEC (not usable when a modem is present)
Note: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
Table 16. Audio Interrupt Slot Definitions Bit 19-1 0 Description Reserved (Audio CODEC will return zeros in bits 19-1) Optional: Assertion = 1 will cause interrupt to be propagated to Audio controller system interrupt. See register 24h definition for enabling mechanism.
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6. STAC9752A/9753A FUNCTIONAL BLOCKS 6.1. STAC9752A/9753A Mixer Description
The STAC9752A/9753A includes an analog mixer for maximum flexibility. The analog mixer is designed to the AC'97 specification to manage the record and playback of all digital and analog audio sources in the PC environment. The analog mixer also includes several extensions of the AC'97 specification to support "all analog record" capability as well as "POP BYPASS" mode for all digital playback. The analog sources include: * * * * * * * System Audio : digital PCM input and output for business, games & multimedia CD/DVD: analog CD/DVD-ROM audio with internal connections to CODEC mixer Stereo or Mono microphone: choice of desktop mic, with programmable boost and gain Speakerphone: use of system mic and speakers for telephone, DSVD, and video conferencing Video: TV tuner or video capture card with internal connections to CODEC mixer AUX/synth: analog FM or wavetable synthesizer, or other internal source Line in: external analog line-level source from consumer audio, video camera, etc.
Source PC_BEEP PHONE MIC1 MIC2 LINE_IN CD VIDEO AUX PCM out Destination HP_OUT LINE_OUT MONO_OUT PCM in SPDIF Function PC BEEP pass through to LINE_OUT MONO input desktop microphone second microphone external audio source audio from CD-ROM audio from TV tuner or video camera upgrade synth or other external source digital audio output from AC'97 Controller Function stereo mix of all sources stereo mix of all sources mic or MONO Analog mixer output digital data from the CODEC to the AC'97 Controller SPDIF digital audio output Connection from PC_BEEP output from telephony subsystem from stereo or mono mic jack from stereo or second mono mic jack from line-in jack cable from CD-ROM cable from TV or VidCap card internal connector AC-Link Connection To headphone out jack To output jack to telephony subsystem AC-Link To SPDIF output connector
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6.1.1.
Mixer Functional Diagrams
Figure 21. STAC9752A/9753A 2-Channel Mixer Functional Diagram
39/41
PINS 39/41
traditionally HP_OUT
MUX
vol
mute
HP
SEL
04h
78h D4 & 20h D15
78h D15:D14
MUX
35/36
PINS 35/36
traditionally LINE_OUT
MUX
SEL
28h: D5-D4
vol
02h
mute
LO
Slot Select
20h:D13 22h:D2-D3
3D
DAC 1 (FRONT) vol
18h
If both are selected, HP will be on and Line Out is Off 23/24
78h D3 & 20h D15
78h D13:D12
PINS 23/24
traditionally Line In L/R
mute
MUX
Mic Mux
78h D9:D8
PINS 21/22
traditionally Mic 1/2
0Ah
PC_BEEP PHONE
L L R R L R
1 2 1 3
vol
mute mute
0Ch Left Ch. Mic 78h D7 & 20h D8 Right Ch. Mic
-6dB
78h D11:D10
vol
0Eh:D6 & 6Eh:D2 30 dB
MUX MUX
-6dB 06h
0Eh
Analog Audio Input Sources
vol vol
12h
mute mute mute mute mute
3D
-6dB
-6dB -6dB
MUX
Digital PCBeep
Line In Mux
MUX
vol
mute
37 +0 dB
MONO_OUT
10h
CD AUX VIDEO
18,20 14,15 16,17
vol vol
14h
20h:D13 22h:D2-D3
20h:D9,D15
MUX
6Eh:D12 -6dB 1Ch AC Link SDATA_OUT Slots 6Eh : D4-5 3&4, 7&8, 6&9, 10&11
16h
vol
vol
mute
+22 dB
STEREO ADC Slot Select
48
Slot Select PCMIn SPDIF_OUT
MUX
2Ah:D5-D4
6.1.2.
Mixer Analog Input
The mixer provides recording and playback of any audio sources or output mix of all sources. The STAC9752A/9753A supports the following input sources: * * * Any mono or stereo source Mono or stereo mix of all sources Two-channel input w/mono output reference (mic or stereo mix)
Note: All unused inputs should be tied together and connected to ground through a capacitor (0.1 F suggested). Note: The MIC inputs should be tied to ground through a separate capacitor (0.1 F suggested).
6.1.3.
Mixer Analog Output
The mixer generates three distinct outputs: * * * A stereo mix of all sources for output to the LINE_OUT A stereo mix of all sources for output to HP_OUT A mono, mic only or mix of all sources for MONO_OUT
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6.2.
SPDIF Digital Mux
The STAC9752A/9753A incorporates a digital output that supports SPDIF formats. A multiplexer determines which of two digital input streams are used for the digital output conversion process. These two streams include the PCM OUT data from the audio controller and the ADC recorded output. The normal analog LINE_OUT signal can be converted to the SPDIF formats by using the internal ADC to record the "MIX" output, which is the combination of all analog and all digital sources. In the case of digital controllers with support for four or more channels, the SPDIF output mode can be used to support compressed 6-channel output streams for delivery to home theater systems. These can be routed on alternate AC-Link slots to the SPDIF output, while the standard 2-channel output is delivered as selected by bits D5 and D4 in Register 6E. If the digital controller supports six channels, a SPDIF output with four analog channels can also be configured. If the Digital Controller has independent DMA engines, SPDIF and Analog can be used simultaneously and independently.
6.3.
PC Beep Implementation
The STAC9752A/9753A offers two styles of PC BEEP, Analog and Digital. The digital PC BEEP is a new feature added to the AC'97 Specification Rev 2.3. This style of PC BEEP will eventually replace the Analog style, thus eliminating the need for a PC BEEP pin. Until this feature is widely accepted, IDT will provide BOTH styles of PC BEEP. Both PC BEEP styles use Reg 0Ah. Additional information about Reg0Ah can be found in Section7.1.5: page53.
6.3.1.
Analog PC Beep
PC Beep is active on power up and defaults to an un-muted state. The PC_BEEP input is routed directly to the MONO_OUT, LINE_OUT and HP_OUT pins of the CODEC. Because the PC_BEEP input drive is often a full scale digital signal, some resistive attenuation of the PC_BEEP input is recommended to keep the beep tone within reasonable volume levels. The user should mute this input before using any other mixer input because the PC Beep input can contribute noise to the lineout during normal operation. This style of PC BEEP is related to the AC'97 Specification Rev 2.2. To use the analog PC BEEP, write a value of 00h to bits F[7:0](D[12:5]) to disable the Digital PC Beep generation. PV[3:0] (D[4:1]) controls the volume level from 0 to 45dB of attenuation in 3dB steps.
6.3.2.
Digital PC Beep
The Digital PC Beep uses the identical register as the Analog style, Reg 0Ah. This register controls the level and frequency for the PC BEEP. The beep frequency is the result of dividing the 48 KHz clock by 2 times the number specified in F[7:0] +2, allowing tones from 94Hz to 12KHz. A value of 00h written to bits F[7:0] disables the digital PC Beep generation and enables the analog style PC BEEP . The volume control bits, PV[3:0] operate identically to the analog PC BEEP mode. Applying a signal to the PC BEEP pin, pin 12, may cause the digital PC BEEP signal to become distorted or inaudible. When using the digital PC BEEP feature, it is recommended to leave the PC BEEP input pin unconnected or connected to analog ground through a capacitor. Connecting a capacitor from the PC BEEP input pin to ground will create a more pleasing sound by changing the digital output to a more sinusoidal signal.
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Table 17. Digital PC Beep Examples Value 1 10 25 50 100 127 255 Reg 0Ah 0x01 0x0A 0x19 0x32 0x64 0x0F 0xFF Frequency 12,000Hz 1200Hz 480Hz 240Hz 120Hz 94.48Hz 47.05Hz
This will be programmed directly by the BIOS.
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7. PROGRAMMING REGISTERS
Table 18. Programming Registers Address 00h 02h 04h 06h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 20h 22h 24h 26h 28h 2Ah 2Ch 32h 3Ah 3Eh 4Ch 4Eh 50h 52h 54h Name Reset Master Volume HP_OUT Mixer Volume Master Volume MONO PC Beep Mixer Volume Phone Mixer Volume Mic Mixer Volume Line In Mixer Volume CD Mixer Volume Video Mixer Volume Aux Mixer Volume PCM Out Mixer Volume Record Select Record Gain General Purpose 3D Control Audio Int. & Paging Powerdown Ctrl/Stat Extended Audio ID Extended Audio Control/Status PCM DAC Rate PCM LR ADC Rate SPDIF Control Extended Modem Stat/Ctl GPIO Pin Configuration GPIO Pin Polarity/Type GPIO Pin Sticky GPIO Wake-up GPIO Pin Status Default 6A90h 8000h 8000h 8000h 0000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 0000h 000Fh 0A05h 0400h* BB80h BB80h 2000h 0100h 0003h FFFFh 0000h 0000h 0000h 1201h FFFFh FFFFh 0000h xxxxh 0000h NA xxxxh 0000h 1000h Location 7.1.1; page51 7.1.2; page52 7.1.3; page52 7.1.4; page53 7.1.5; page53 7.1.6; page54 7.1.7; page54 7.1.8; page55 7.1.9; page56 7.1.10; page56 7.1.11; page57 7.1.12; page57 7.1.13; page58 7.1.14; page59 7.1.15; page59 7.1.16; page60 7.1.17: page61 7.1.18; page62 7.1.19; page63 7.1.20; page64 7.1.22; page67 7.1.23; page67 7.1.24; page68 7.2.4; page69 7.2.5; page70 7.2.6; page70 7.2.7; page70 7.2.8; page71 7.2.9; page71 7.3; page72 7.4.2; page73 7.4.3; page74 7.4.4; page74 7.4.5; page75 7.4.6; page77 7.4.7: page78 7.4.7; page78 NA 7.4.9: page80
60h CODEC Class/Rev 62h (Page 01h) PCI SVID 64h (Page 01h) PCI SSID 66h (Page 01h) Function Select 68h (Page 01h) Function Information 6Ah Digital Audio Control 6Ah (Page01h) Sense Details 6Ch Revision Code 6Ch (Page01h) Reserved 6Eh Analog Special
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Table 18. Programming Registers Address 6Eh (Page01h) Reserved 70h 72h 74h 76h 78h 7Ah 7Ch 7Eh Enable Register Analog Current Adjust EAPD Access Register 78h Enable High Pass Filter Bypass Universal JacksTM Selection Vendor ID1 Vendor ID2 Name Default 0000h 0000h 0000h 0800h 0000h 0000h 0000h 8384h 7652h Location NA NA 7.4.10; page81 7.4.11; page82 7.4.11; page82 7.4.11; page82 7.4.11; page82 7.5.1; page84 7.5.2; page84
Note: * depends upon CODECID
7.1.
Register Descriptions
Reset (00h)
Default: 6A90h
D15 RSRVD D7 ID7 D14 SE4 D6 ID6 D13 SE3 D5 ID5 D12 SE2 D4 ID4 D11 SE1 D3 ID3 D10 SE0 D2 ID2 D9 ID9 D1 ID1 D8 ID8 D0 ID0
7.1.1.
Writing any value to this register performs a register reset, which causes all registers to revert to their default values. This register reset also resets all the digital block. Reading this register returns the ID code of the part.
Bit(s) 15 14:10 9 8 7 6 5 4 3 2 1 0 Reset Value 0 11010 1 0 1 0 0 1 0 0 0 0 Name Reserved SE4:SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Description Bit not used, should read back 0 IDT ID for SS3D 20 Bit ADC Resolution (Supported) 18 Bit ADC Resolution 20 Bit DAC Resolution (Supported) 18 Bit DAC Resolution Loudness (Bass Boost) Headphone Out (Supported) Simulated Stereo ( Mono To Stereo ) Bass & Treble Control Reserved Dedicated Mic PCM IN Channel
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7.1.2.
Master Volume Registers (02h)
Default: 8000h
D15 Mute D7 Reserved Bit(s) 15 14 13 Reset Value 1 0 0 D14 RSRVD D6 D13 ML5 D5 MR5 Name Mute Reserved ML5 D12 ML4 D4 MR4 D11 ML3 D3 MR3 D10 ML2 D2 MR2 D9 ML1 D1 MR1 D8 ML0 D0 MR0
12:8
0
ML<4:0>
7:6 5
0 0
Reserved MR5
4:0
0
MR<4:0>
Description 0 = No mute 1 = Mutes both left & right channels Bit not used, should read back 0 0 = Lineout attenuation is a function of bits12-8 1 = Forces register bits 12-8 to be 11111 Always reads back 0 Left Lineout Volume Control 00000 = 0dB attenuation 00001 = 1.5dB attenuation ..... 11111 = 46.5dB attenuation Bits not used, should read back 0 0 = Lineout attenuation is a function of bits 4-0 1 = Forces register bits 4-0 to be 11111 Always reads back 0 Right Channel Lineout Volume Control 00000 = 0dB attenuation 00001 = 1.5dB attenuation ..... 11111 = 46.5dB attenuation
7.1.3.
Headphone Volume Registers (04h)
Default: 8000h
D15 Mute D7 Reserved Bit(s) 15 14 13 Reset Value 1 0 0 D14 RSRVD D6 D13 HPL5 D5 HPR5 Name Mute Reserved ML5 D12 HPL4 D4 HPR4 D11 HPL3 D3 HPR3 D10 HPL2 D2 HPR2 D9 HPL1 D1 HPR1 D8 HPL0 D0 HPR0
12:8
0
ML<4:0>
Description 0 = No mute 1 = Mutes both left & right channels Bit not used, should read back 0 0 = Headphone attenuation is a function of bits12-8 1 = Forces register bits 12-8 to be 11111 Always reads back 0 Left Headphone Volume Control 00000 = 0dB attenuation 00001 = 1.5dB attenuation ..... 11111 = 46.5dB attenuation
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Bit(s) 7:6 5
Reset Value 0 0
Name Reserved MR5
4:0
0
MR<4:0>
Description Bits not used, should read back 0 0 = Headphone attenuation is a function of bits 4-0 1 = Forces register bits 4-0 to be 11111 Always reads back 0 Right Channel Headphone Volume Control 00000 = 0dB attenuation 00001 = 1.5dB attenuation ..... 11111 = 46.5dB attenuation
7.1.4.
Master Volume MONO (06h)
Default: 8000h
D15 Mute D7 Reserved Bit(s) 15 14:6 5 Reset Value 1 0 0 D14 D6 D13 D5 MM5 Name Mute Reserved MM5 D12 D4 MM4 D11 Reserved D3 MM3 D10 D2 MM2 D9 D1 MM1 D8 D0 MM0
4:0
0
MM<4:0>
Description 0 = no mute 1 = mute mono Bit not used, should read back 0 0 = Mono attenuation is a function of bits 4-0 1 = Forces register bits 4-0 to be 11111 Always reads back 0 Mono Volume Control 00000 = 0dB attenuation 00001 = 1.5dB attenuation ..... 11111 = 46.5dB attenuation
7.1.5.
PC BEEP Volume (0Ah)
Default: 0000h Additional information on the PC Beep can be found in Section 6.3: page48.
D15 Mute D7 F2 Bit(s) 15 14:13 D14 Reserved D6 F1 Reset Value 1 0 D5 F0 Name Mute Reserved D13 D12 F7 D4 PV3 D11 F6 D3 PV2 D10 F5 D2 PV1 D9 F4 D1 PV0 D8 F3 D0 RSRVD
Description 0 = No mute 1 = Mute PC BEEP Bit not used, should read back 0
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Bit(s)
Reset Value
Name
Description The Beep frequency is the result of dividing the 48KHz clock by 4 times the number specified in F[7:0] allowing tones from 47Hz to 12KHz. A value of 00h in bits F[7:0] disables internal PC BEEP generation and enables external PC BEEP input if available. PCBEEP Volume Control 0000 = 0dB attenuation 0001 = 3dB attenuation ..... 1111 = 45dB attenuation Bit not used, should read back 0
12:5
00h
F[7:0]
4:1
0
PV(3:0)
0
0
Reserved
7.1.6.
Phone Volume (Index 0Ch)
Default: 8008h.
D15 Mute D7 D6 Reserved Reset Value 1 0 D5 D4 GN4 D14 D13 D12 D11 Reserved D3 GN3 D2 GN2 D1 GN1 D0 GN0 D10 D9 D8
Bit(s) 15 14:5
Name Mute Reserved
4:0
0
GN<4:0>
Description 0 = No mute 1 = Mute phone Bit not used, should read back 0 Phone Volume Control 00000 = 12dB gain 00001 = 10.5dB gain ..... 01000 = 0dB gain ..... 11111 = -34.5dB gain
7.1.7.
Stereo or Mic Volume (Index 0Eh)
To enable Stereo Mic, Register 78h (unlocked), bit D6 must be enabled. In Stereo mode, the left and right volume is controlled by GN4:GN0. Default: 8008h.
D15 Mute D7 Reserved Bit(s) 15 14:7 D14 D6 BOOSTEN D13 D5 Reserved Name Mute Reserved D12 D4 GN4 D11 Reserved D3 GN3 D10 D2 GN2 D9 D1 GN1 D8 D0 GN0
Reset Value 1 0
Description 0 = no mute 1 = mute phone Bit not used, should read back 0
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
Bit(s)
Reset Value
Name
6
0
BOOSTEN
Description Works with MICGAINVAL (Register 6Eh Bit D2) BOOSTEN MICGAINVAL = Mic Gain Boost 0 0 = 0 dB 0 1 = 10 dB 1 0 = 20 dB 1 1 = 30 dB Phone Volume Control 00000 = 12dB gain 00001 = 10.5dB gain ..... 01000 = 0dB gain ..... 11111 = -34.5dB gain
5
0
Reserved
4:0
0
GN<4:0>
7.1.8.
LineIn Volume (Index 10h)
Default: 8808h.
D15 Mute D7 D14 Reserved D6 Reserved Reset Value 1 0 D5 D13 D12 GL4 D4 GR4 D11 GL3 D3 GR3 D10 GL2 D2 GR2 D9 GL1 D1 GR1 D8 GR0 D0 GR0
Bit(s) 15 14:13
Name Mute Reserved
12:8
0
GL<4:0>
7:5
0
Reserved
4:0
0
GR<4:0>
Description 0 = no mute 1 = mute linein Bit not used, should read back 0 Left LineIn Volume Control 00000 = 12dB gain 00001 = 10.5dB gain ..... 01000 = 0dB gain ..... 11111 = -34.5dB gain Bit not used, should read back 0 Right LineIn Volume Control 00000 = 12dB gain 00001 = 10.5dB gain ..... 01000 = 0dB gain ..... 11111 = -34.5dB gain
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
7.1.9.
CD Volume (Index 12h)
Default: 8808h.
D15 Mute D7 D14 Reserved D6 Reserved Bit(s) 15 14:13 Reset Value 1 0 Name Mute Reserved D5 D13 D12 GL4 D4 GR4 D11 GL3 D3 GR3 D10 GL2 D2 GR2 D9 GL1 D1 GR1 D8 GR0 D0 GR0
12:8
0
GL<4:0>
7:5
0
Reserved
4:0
0
GR<4:0>
Description 0 = no mute 1 = mute CD Bit not used, should read back 0 Left CD Volume Control 00000 = 12dB gain 00001 = 10.5dB gain ..... 01000 = 0dB gain ..... 11111 = -34.5dB gain Bit not used, should read back 0 right CD Volume Control 00000 = 12dB gain 00001 = 10.5dB gain ..... 01000 = 0dB gain ..... 11111 = -34.5dB gain
7.1.10.
Video Volume (Index 14h)
Default: 8808h.
D15 Mute D7 D14 Reserved D6 Reserved Bit(s) 15 14:13 Reset Value 1 0 Name Mute Reserved D5 D13 D12 GL4 D4 GR4 D11 GL3 D3 GR3 D10 GL2 D2 GR2 Description 0 = no mute 1 = mute video Bit not used, should read back 0 Left Video Volume Control 00000 = 12dB gain 00001 = 10.5dB gain ..... 01000 = 0dB gain ..... 11111 = -34.5dB gain D9 GL1 D1 GR1 D8 GR0 D0 GR0
12:8
0
GL<4:0>
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
Bit(s) 7:5
Reset Value 0
Name Reserved
4:0
0
GR<4:0>
Description Bit not used, should read back 0 Right video Volume Control 00000 = 12dB gain 00001 = 10.5dB gain ..... 01000 = 0dB gain ..... 11111 = -34.5dB gain
7.1.11.
Aux Volume (Index 16h)
Default: 8808h.
D15 Mute D7 D14 Reserved D6 Reserved Bit(s) 15 14:13 Reset Value 1 0 Name Mute Reserved D5 D13 D12 GL4 D4 GR4 D11 GL3 D3 GR3 D10 GL2 D2 GR2 D9 GL1 D1 GR1 D8 GR0 D0 GR0
12:8
0
GL<4:0>
7:5
0
Reserved
4:0
0
GR<4:0>
Description 0 = no mute 1 = mute aux Bit not used, should read back 0 Left Aux Volume Control 00000 = 12dB gain 00001 = 10.5dB gain ..... 01000 = 0dB gain ..... 11111 = -34.5dB gain Bit not used, should read back 0 Right Aux Volume Control 00000 = 12dB gain 00001 = 10.5dB gain ..... 01000 = 0dB gain ..... 11111 = -34.5dB gain
7.1.12.
PCMOut Volume (Index 18h)
Default: 8808h.
D15 Mute D7 D14 Reserved D6 Reserved D5 D13 D12 GL4 D4 GR4 D11 GL3 D3 GR3 D10 GL2 D2 GR2 D9 GL1 D1 GR1 D8 GR0 D0 GR0
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
Bit(s) 15 14:13
Reset Value 1 0
Name Mute Reserved
12:8
0
GL<4:0>
7:5
0
Reserved
4:0
0
GR<4:0>
Description 0 = no mute 1 = mute PCM out Bit not used, should read back 0 Left PCM Volume Control 00000 = 12dB gain 00001 = 10.5dB gain ..... 01000 = 0dB gain ..... 11111 = -34.5dB gain Bit not used, should read back 0 Right PCM Volume Control 00000 = 12dB gain 00001 = 10.5dB gain ..... 01000 = 0dB gain ..... 11111 = -34.5dB gain
7.1.13.
Record Select (1Ah)
Default: 0000h (corresponding to Mic in) Used to select the record source independently for right and left.
D15 D7 D14 D6 D13 Reserved D5 Reserved Name Reserved D4 D3 D12 D11 D10 SL2 D2 SR2 D9 SL1 D1 SR1 D8 SL0 D0 SR0
Bit(s) 15:11
Reset Value 0
10:8
0
SL2:SL0
Description Bits not used, should read back 0 Left Channel Input Select 000 = Mic 001 = CD In (left) 010 = Video In (left) 011 = Aux In (left) 100 = Line In (left) 101 = Stereo Mix (left) 110 = Mono Mix 111 = Phone
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
Bit(s) 7:3
Reset Value 0
Name Reserved
2:0
0
SR2:SR0
Description Bits not used, should read back 0 Right Channel Input Select 000 = Mic 001 = CD In (right) 010 = Video In (right) 011 = Aux In (right) 100 = Line In (right) 101 = Stereo Mix (right) 110 = Mono Mix 111 = Phone
7.1.14.
Record Gain (1Ch)
Default: 8000h (corresponding to 0 dB gain with mute on)
D15 Mute D7 D14 D6 D13 Reserved D5 Reserved Bit(s) 15 14:12 Reset Value 1 0 Name MUTE Reserved D12 D4 D11 GL3 D3 GR3 D10 GL2 D2 GR2 Description MUTES RECORD GAIN Bits not used, should read back 0 Left Channel Volume Control 0000 = 0dB gain 0001 = 1.5dB gain .... 1111 = 22.5dB gain Bits not used, should read back 0 Right Channel Volume Control 0000 = 0dB gain 0001 = 1.5dB gain .... 1111 = 22.5dB gain D9 GL1 D1 GR1 D8 GL0 D0 GR0
11:8
0
GL<3:0>
7:4
0
Reserved
3:0
0
GR<3:0>
7.1.15.
General Purpose (20h)
Default: 0000h
D15 POP BYP D7 LOOPBACK D14 Reserved D6 D13 3D D5 D12 D4 D11 Reserved D3 Reserved D10 D2 D9 MIX D1 D8 MS D0
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
Bit(s) 15 14 13 12:10 9 8 7 6:0
Reset Value 0 0 0 0 0 0 0 0
Name POP BYPASS Reserved 3D Reserved MIX MS LOOPBACK Reserved
Description 0 = Normal 1 = DAC bypasses mixer and connects directly to Line Out, Headphone Out and Mono Out. Bit not used, should read back 0 0 = 3D effect disabled 1 = 3D effect enabled Bit not used, should read back 0 Mono Output select (0 = Mix, 1 = Mic) Mic select (0 = Mic1, 1 = Mic2) 1 = Enables ADC to DAC Loop Back Test 0 = Loopback Disabled Do not send in conflicting data on AC-Link while running this. Bit not used, should read back 0
7.1.16.
3D Control (22h)
Default: 0000h
D15 D7 D14 D6 Reserved Bit(s) 15:4 Reset Value 0 Name Reserved D13 D5 D12 Reserved D4 D3 DP3 D2 DP2 D1 Reserved D0 D11 D10 D9 D8
3:2
0
DP3,DP2
1:0
0
Reserved
Description Bits not used, should read back 0 LINE_OUT SEPARATION RATIO DP3 DP2 effect 0 0 0 ( OFF ) 0 1 3 ( LOW ) 1 0 4.5 ( MED ) 1 1 6 ( HIGH ) Bits not used, should read back 0
This register is used to control the 3D stereo enhancement function, IDT Surround 3D (SS3D), built into the AC'97 component. Note that register bits DP3-DP2 are used to control the separation ratios in the 3D control for LINE_OUT. SS3D provides for a wider soundstage, extending beyond the normal 2-speaker arrangement. Note that the 3D bit in the general purpose register (20h) must be set to 1 to enable SS3D functionality, which allow the bits in register 22h to take effect. The three separation ratios are implemented. The separation ratio defines a series of equations that determine the amount of depth difference (High, Medium and Low) perceived during two-channel playback. The ratios provide for options to narrow or widen the soundstage.
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
60
STAC9752A/9753A
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
7.1.17.
Audio Interrupt and Paging (24h)
Default: 0000h
D15 I4 D7 D14 I3 D6 Reserved Bit(s) Reset Value Access Name D13 I2 D5 D12 I1 D4 D11 I0 D3 PG3 D10 D2 PG2 D9 Reserved D1 PG1 D8 D0 PG0
15
0
Read / Write
I4
14-13
0
Read Only
I3-I2
12
0
Read / Write
I1
11
0
Read / Write
I0
Description 0 = Interrupt is clear 1 = interrupt is set Interrupt event is cleared by writing a 1 to this bit. The interrupt bit will change regardless of condition of interrupt enable (I0) status. An interrupt in the GPI in slot 12 in the ACLink will follow this bit change when interrupt enable (I0) is unmasked. Interrupt Cause 00 = Reserved 01 = Sense Cycle Complete, sense info available. 10 = Change in GPIO input status 11 = Sense Cycle Complete and Change in GPIO input status. These bits will reflect the general cause of the first interrupt event generated. It should be read after interrupt status has been confirmed as interrupting. The information should be used to scan possible interrupting events in proper pages. Sense Cycle 0 = Sense Cycle not in Progress 1 = Sense Cycle Start. Writing a 1 to this bit causes a sense cycle start if supported. If sense cycle is not supported this bit is read only. Interrupt Enable 0 = Interrupt generation is masked. 1 = Interrupt generation is un-masked. The driver should not un-mask the interrupt unless ensured by the AC`97 controller that no conflict is possible with modem slot 12 GPI functionality. Some AC'97 2.2 compliant controllers will not likely support audio CODEC interrupt infrastructure. In either case, Software should poll the interrupt status after initiating a sense cycle and wait for Sense Cycle Max Delay to determine if an interrupting event has occurred.
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
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V 1.5 1206
STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
Bit(s) Reset Value 10:4 0
Access Read Only
Name Reserved
3:0
0
Read / Write
PG3:PG0
Description Bits not used, should read back 0 Page Selector 0h = Vendor Specific 1h = Page ID 01 (See Section 7.4 for additional information on the Paging Registers) ......... Fh = Reserved Pages This register is used to select a descriptor of 16 word pages between registers 60h to 6Fh. Value 0h is used to select vendor specific space to maintain compatibility with AC'97 2.2 vendor specific registers. System Software determines implemented pages by writing the page number and reading the value back. All implemented pages must be consecutive. (i.e., page 2h cannot be implemented without page 1h). These registers are not reset on RESET#.
7.1.18.
Powerdown Ctrl/Stat (26h)
Default: 000Fh
D15 EAPD D7 D14 PR6 D6 Reserved Bit(s) 15 14 13 12 11 10 9 8 7:4 3 2 Reset Value 0 0 0 0 0 0 0 0 0 1 1 Name EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 Reserved REF ANL D13 PR5 D5 D12 PR4 D4 D11 PR3 D3 REF D10 PR2 D2 ANL D9 PR1 D1 DAC D8 PR0 D0 ADC
Description 1 = Forces EAPD pad to Vdd 0 = Forces EAPD pad to GND 0 = Headphone Amp powered up 1 = Headphone Amp powered down 0 = Digital Clk active 1 = Digital Clk disable. 0 = Digital active 1 = Powerdown: PLL, AC-Link, Xtal oscillator; 0 = VREF and VREFOUT are active 1 = VREF and VREFOUT are powered down, and PR2 is asserted in analog block 0 = Analog active 1 = All signal path analog is powered down 0 = DAC powered up 1 = DAC powered down 0 = ADC powered up 1 = ADC powered down Bit not used, should read back 0 Read Only --- VREF status 1 = VREF'S enabled Read Only ---- ANALOG MIXERS, etc. Status 1 = analog mixers ready.
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
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STAC9752A/9753A
V 1.5 1206
STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
Bit(s) 1 0
Reset Value 1 1
Name DAC ADC Read Only ---- DAC Status 1 = DAC ready to playback Read Only ---- ADC Status 1 = ADC ready to record
Description
7.1.18.1.
Ready Status
The lower half of this register is read only status, a 1 indicating that each subsection is ready. Ready is defined as the subsection's ability to perform in its nominal state. When this register is written, the bit values that come in on AC-Link will have no effect on read-only bits 0-7. When the AC-Link "CODEC Ready" indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the AC-Link and AC'97 control and status registers are in a fully operational state. The AC'97 controller must further probe this PowerdownControl/Status Register to determine exactly which subsections, if any, are ready. When this register is written, the bit values that come in on AC-Link will have no effect on read-only bits 0-7.
7.1.18.2.
Powerdown Controls
The STAC9752A/9753A is capable of operating at reduced power when no activity is required. The power-down state is controlled by the Powerdown Register (26h). See the section "Low Power Modes" for more information.
7.1.18.3.
External Amplifier Power Down Control Output
The EAPD bit (bit 15 of the Powerdown Control/Status Register (Index 26h)), directly controls the EAPD output, pin 45, and produces a logical 1 when this bit is set to logic high. This function is used to control an external audio amplifier power-down. EAPD= 0 places approximately 0V on the output pin, enabling an external audio amplifier. EAPD=1 places approximately DVdd on the output pin, disabling the external audio amplifier. Audio amplifiers that operate with reverse polarity will likely require an external inverter to maintain software driver compatibility. EAPD can also act as a GPIO. See Section 7.4.11: page82. The GPIO controls in Section 7.2: page68 have no effect on EAPD.
7.1.19.
Extended Audio ID (28h)
Default: 0A05h
D15 ID1 D7 Reserved D14 ID0 D6 D13 D5 DSA1 D12 Reserved D4 DSA0 D3 RESVD D2 SPDIF D11 D10 D9 AMAP D1 RSVD D8 RSVD D0 VRA
The Extended Audio ID register is a read-only register except for bits D4 and D5. ID1 and ID0 echo the configuration of the CODEC as defined by the programming of pins 45 and 46 externally. "00" returned defines the CODEC as the primary CODEC, while any other code identifies the CODEC as
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
one of three secondary CODECs. The AMAP bit, D9, will return a 1 indicating that the CODEC supports the optional "AC'97 2.3 Compliant AC-Link Slot to Audio DAC Mappings". The default condition assumes that 00 is loaded in the DSA0 and DSA1 bits of the Extended Audio ID (Index 28h). With 00 in the DSA1 and DSA0 bits, the CODEC slot assignments are as per the AC'97 specification recommendations. If the DSA1 and DSA0 bits do not contain 00, the slot assignments are as per the table in the section describing the Extended Audio ID (Index 28h). The VRA bit, D0, will return a 1 indicating that the CODEC supports the optional variable sample rate conversion as defined by the AC'97 specification.
Table 19. Extended Audio ID Register Functions Bit 15:14 13:12 11:10 9:6 Name ID [1,0] Reserved REV[1:0] RSVD Access Read only Read only Read only Read only Reset Value variable 00 10 0 Function 00 = XTAL_OUT grounded (Note Note:) CID1#,CID0# = XTAL_OUT crystal or floating Bits not used, should read back 00 Indicates CODEC is AC'97 Rev 2.3 compliant Reserved DAC slot assignment If CID[1:0] = 00 then DSA[1:0] resets to 00 If CID[1:0] = 01 then DSA[1:0] resets to 01 If CID[1:0] = 10 then DSA[1:0] resets to 01 If CID[1:0] = 11 then DSA[1:0] resets to 10 00 = left slot 3, right slot 4 01 = left slot 7, right slot 8 10 = left slot 6, right slot 9 11 = left slot 10, right slot 11 3 2 1 0 RSVD SPDIF RSVD VRA Read only Read only Read only Read only 0 1 0 1 Reserved 0 = SPDIF pulled high on reset, SPDIF disabled 1 = default, SPDIF enabled (Note Note:) Reserved Variable sample rates supported (Always = 1)
5:4
DSA [1,0]
Read/Write
00
Note: 1) External CID pin status (from analog), these bits are the logical inversion of the pin polarity (pin 45-46). These bits are zero if XTAL_OUT is grounded with an alternate external clock source (in primary mode only). Secondary mode can either be through BIT CLK driven or 24MHz clock driver, with XTAL_OUT floating. Note: 2) If pin 48 is held high at powerup, this bit will be held to zero, to indicate the SPDIF is not available. To disable SPDIF, use an 1K - 1 0 K external pullup resistor.
7.1.20.
Extended Audio Control/Status (2Ah)
Default: 0400h* (*default depends on CODEC ID)
D15 VCFG D7 Reserved D6 D14 D13 Reserved D5 SPSA1 D4 SPSA0 D3 RSRVD D12 D11 D10 SPCV D2 SPDIF D9 Reserved D1 RSRVD D0 VRA enable D8
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
Bit(s) Reset Value
Name
15
VCFG
14-11 10 9:6 0 0
Reserved SPCV Reserved
Description Determines the SPDIF transmitter behavior when data is not being transmitted. When asserted, this bit forces the deassertion of the SPDIF "Validity" flag, which is bit 28 transmitted by the SPDIF sub-frame. The "V" bit is defined in the SPDIF Control Register (Reg 3Ah). If "V" = 1 and "VCFG" = 0, then for each S/PDIF sub-frame (Left & Right), bit<28> "Validity" flag reflects whether or not an internal CODEC transmission error has occurred. Specifically an internal CODEC error should result in the "Validity" flag being set to 1. If "V" = 0 and "VCFG" = 1, In the case where the S/PDIF transmitter does not receive a valid sample from the AC'97 controller, (Left or Right), the S/PDIF transmitter should set the "Validity" flag to 0 and pad the "Audio Sample Word" with 0s for sub-frame in question. If a valid sample (Left or Right) was received and successfully transmitted, the "Validity" flag should be 0 for that sub-frame. Default state, coming out of reset, for "V" and "VCFG" should be 0 and 0. These bits are set-able via driver .inf options. Reserved 0 = invalid SPDIF configuration 1 = valid SPDIF configuration Bit not used, should read back 0 SPDIF slot assignment
5:4
0
If CID[1:0] = 00 then SPSA[1:0] resets to 01 If CID[1:0] = 01 then SPSA[1:0] resets to 10 If CID[1:0] = 10 then SPSA[1:0] resets to 10 SPSA1:SPSA0 If CID[1:0] = 11 then SPSA[1:0] resets to 11 00 = left slot 3, right slot 4 01 = left slot 7, right slot 8 10 = left slot 6, right slot 9 11 = left slot 10, right slot 11 Reserved 0 = disables SPDIF (SPDIF_OUT is high-Z ) (Note 1) 1 = enable SPDIF SPDIF is a control register for Reg 3Ah, this bit must be set low (i.e. SPDIF disabled) in order to write to Reg 3Ah Bits D15, D13:D0. Bit not used, should read back 0 0 = VRA disabled, DAC and ADC set to 48KHz (Registers 2Ch and 32h loaded with the value BB80h) 1 = VRA enabled, Reg. 2Ch & 32h control sample rate
3 2 1 0 0 0 0
Reserved SPDIF Reserved VRA Enable
7.1.20.1.
Variable Rate Sampling Enable
The Extended Audio Status Control register also contains one active bit to enable or disable the Variable Sampling Rate capabilities of the DACs and ADCs. If the VRA bit D0 is 1, the variable sample rate control registers (2Ch and 32h) are active, and "on-demand" slot data required transfers are allowed. If the VRA bit is 0, the DACs and ADCs will operate at the default 48KHz data rate. The STAC9752A/9753A supports "on-demand" slot request flags. These flags are passed from the CODEC to the AC'97 controller in every audio input frame. Each time a slot request flag is set (active
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65
STAC9752A/9753A
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
low) in a given audio frame, the controller will pass the next PCM sample for the corresponding slot in the audio frame that immediately follows. The VRA enable bit must be set to 1 to enable "on-demand" data transfers. If the VRA enable bit is not set, the CODEC will default to 48 KHz transfers and every audio frame will include an active slot request flag and data is transferred every frame. For variable sample rate output, the CODEC examines its sample rate control registers, the state of the FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to determine which SLOTREQ bits to set active (low). SLOTREQ bits are asserted during the current audio input frame for active output slots, which will require data in the next audio output frame. For variable sample rate input, the tag bit for each input slot indicates whether valid data is present or not. Thus, even in variable sample rate mode, the CODEC is always the master: for SDATA_IN (CODEC to controller), the CODEC sets the TAG bit; for SDATA_OUT (controller to CODEC), the CODEC sets the SLOTREQ bit and then checks for the TAG bit in the next frame. Whenever VRA is set to 0, the PCM rate registers (2Ch and 32h) are overwritten with BB80h (48 KHz).
7.1.20.2.
SPDIF
The SPDIF bit in the Extended Audio Status Control Register is used to enable and disable the SPDIF functionality within the STAC9752A/9753A. If the SPDIF is set to a 1, then the function is enabled. When set to a 0, it is disabled.
7.1.20.3.
SPCV (SPDIF Configuration Valid)
The SPCV bit is read only and indicates whether or not the SPDIF system is set up correctly. When SPCV is a 0, it indicates the system configuration is invalid. When SPCV is a 1, it indicates the system configuration is valid.
7.1.20.4.
SPSA1, SPSA0 (SPDIF Slot Assignment)
SPSA1 and SPSA0 combine to provide the slot assignments for the SPDIF data. The following details the slot assignment relationship between SPSA1 and SPSA0. The STAC9752A/9753A are AMAP compliant with the following table.
Table 20. AMAP compliant CODEC ID 00 01 10 11 Function 2-ch Primary with SPDIF 2-ch Dock CODEC with SPDIF +2-ch Surr w/ SPDIF +2-ch Cntr/LFE with SPDIF SPSA=00 SPSA=01 SPSA=10 SPSA=11 Slot Assignment Slot Assignment Slot Assignment Slot Assignment 3&4 3&4 3&4 3&4 7&8 * 7&8 7&8 7&8 6&9 6&9* 6&9* 6&9 10 & 11 10 & 11 10 & 11 10 & 11 *
Note:* is the default slot assignment
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
66
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
7.1.21.
PCM DAC Rate Registers (2Ch and 32h)
The internal sample rate for the DACs and ADCs are controlled by the value in these read/write registers that contain a 16-bit unsigned value between 0 and 65535 representing the conversion rate in Hertz (Hz). In VRA mode (register 2Ah, bit D0= 1), if the value written to these registers is supported, that value will be echoed back when read, otherwise the closest (higher in the case of a tie) sample rate is supported and returned. Per PC 99/PC2001 specification, independent sample rates are supported for record and playback. Whenever VRA is set to 0 the PCM rate registers (2Ch and 32h) will be loaded with BB80h (48KHz). If VRA is set to a 0, any write to this address will be ignored and the rate remains at 48KHz.
Table 21. Hardware Supported Sample Rates Sample Rate 8 KHz 11.025 KHz 16 KHz 22.05 KHz 32 KHz 44.1 KHz 48 KHz SR15-SR0 Value 1F40h 2B11h 3E80h 5622h 7D00h AC44h BB80h
7.1.22.
PCM DAC Rate (2Ch)
Default: BB80h (see table21: page67)
D15 SR15 D7 SR7 D14 SR14 D6 SR6 D13 SR13 D5 SR5 D12 SR12 D4 SR4 D11 SR11 D3 SR3 D10 SR10 D2 SR2 D9 SR9 D1 SR1 D8 SR8 D0 SR0
7.1.23.
PCM LR ADC Rate (32h)
Default: BB80h (see table21: page67)
D15 SR15 D7 SR7 D14 SR14 D6 SR6 D13 SR13 D5 SR5 D12 SR12 D4 SR4 D11 SR11 D3 SR3 D10 SR10 D2 SR2 D9 SR9 D1 SR1 D8 SR8 D0 SR0
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
67
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
7.1.24.
SPDIF Control (3Ah)
Default: 2000h
D15 V D7 CC3 Bit(s) D14 DRS D6 CC2 Reset Value D13 SPSR1 D5 CC1 Access Name D12 SPSR2 D4 CC0 D11 L D3 PRE D10 CC6 D2 COPY D9 CC5 D1 /AUDIO D8 CC4 D0 PRO
15 in 2.3
V
Description (note 1-2) Validity: This bit affects the "Validity" flag, bit<28>, transmitted in each S/PDIF subframe, and enables the S/PDIF transmitter to maintain connection during error or mute conditions. Subframe bit<28>=0 indicates that data is valid for conversion at the receiver, 1 indicates invalid data (not suitable for conversion at the receiver).
14
0
13:12
10
11 10:4 3 2 1 0
0 0 0 0 0 0
If "V" = 1, then each S/PDIF subframe (Left & Right) should have bit<28> "Validity" flag = 1 or set based on the assertion or de-assertion of the AC '97 "VFORCE" bit within the Extended Audio Status and Control Register (D15, register 2Ah). Read Only DRS 1 = Double Rate SPDIF support (always = 0) SPDIF Sample Rate. 00 - 44.1 KHz Rate Read & Write SPSR[1,0] 01 - Reserved 10 - 48 KHz Rate (default) 11 - 32 KHz Rate Generation Level is defined by the IEC standard, or as Read & Write L appropriate. Category Code is defined by the IEC standard or as appropriate Read & Write CC[6, 0] by media. 0 = 0 sec Pre-emphasis Read & Write PRE 1 = Pre-emphasis is 50/15 sec 0 = Copyright not asserted Read & Write COPY 1 = Copyright is asserted 0 = PCM data Read & Write /AUDIO 1 = Non-Audio or non-PCM format 0 = Consumer use of the channel Read & Write PRO 1 = Professional use of the channel
7.2.
General Purpose Input & Outputs
EAPD
EAPD can act as a GPIO, but is unaffected by the following registers. To use EAPD as a GPIO, use Register 74h, the EAPD Access Register. Information about this register is located in Section 7.4.11: page82. Additional information about EAPD can also be found in Section 7.1.18.3: page63.
7.2.1.
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7.2.2.
GPIO Pin Definitions
GPIO pins are programmable to have input/output functionality. The data values (status) for these pins are all in one register with input/output configuration in a separate register. Control of GPIO pins configured for output is achieved by setting the corresponding bit in output slot 12; status of GPIO pins configured for input is returned on input slot 12. The CODEC must constantly set the GPIO pins that are configured for output, based upon the value of the corresponding bit position of the control slot 12. The CODEC should ignore output slot 12 bits that correspond to GPIO control pins configured as inputs. The CODEC must constantly update status on input slot 12, based upon the logic level detected at each GPIO pin configured for input. A GPIO output pin value that is written via slot 12 in the current frame won't affect the GPIO status that is returned in that particular write frame. This slot-12 based control/status protocol minimizes the latency and complexity, especially for host-based Controllers and host data pump software, and provides high speed monitoring and control, above what could be achieved with command/status slots. For host-based implementations, most AC`97 registers can be shadowed by the driver in order to provide immediate response when read by the processor, and GPIO pins configured as inputs should be capable of triggering an interrupt upon a change of status. The AC-Link request for GPIO pin status is always delayed by at least one frame time. Read-Modify-Writes across the AC-Link will thus incur latency issues and must be accounted for by the software driver or AC`97 Digital Controller firmware. PCI re-tries should be kept to a minimum wherever possible.
7.2.3.
GPIO Pin Implementation
The GPIOs are set to a high impedance state on power-on or a cold reset. It is up to the AC`97 Digital Controller to first enable the output after setting it to the desired state.
7.2.4.
Extended Modem Status and Control Register (3Eh) Default: 0100h
D15 D7 D14 D6 D13 D5 D12 Reserved D4 Reserved Name Reserved PRA Reserved GPIO D3 D2 D1 D11 D10 D9 D8 PRA D0 GPIO
Bit(s) 15:9 8 7:1 0
Access Read Only Read / Write Read Only Read Only
Reset Value 0 1 0 0
Description Bit not used, should read back 0 0 = GPIO powered up / enabled 1 = GPIO powered down / disabled Bit not used, should read back 0 0 = GPIO not ready (powered down) 1 = GPIO ready (powered up)
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7.2.5.
GPIO Pin Configuration Register (4Ch) Default: 0003h
D15 D7 D14 D6 D13 D5 Reserved Bit(s) 15:2 1 0 Access Read Only Read / Write Read / Write Reset Value 0 1 1 Name Reserved GC1 GC0 D12 Reserved D4 D3 D2 D1 GC1 (GPIO1) Description Bit not used, should read back 0 0 = GPIO1 configured as output 1 = GPIO1 configured as input 0 = GPIO0 configured as output 1 = GPIO0 configured as input D0 GC0 (GPIO0) D11 D10 D9 D8
7.2.6.
GPIO Pin Polarity/Type Register (4Eh) Default: FFFFh
D15 D7 D14 D6 D13 D5 Reserved Bit(s) 15:2 1 0 Access Read Only Read / Write Read / Write Reset Value 0 1 1 D12 Reserved D4 D3 D2 D1 GP1 (GPIO1) D0 GP0 (GPIO0) D11 D10 D9 D8
Name Description Reserved Bit not used, should read back 0 0 = GPIO1 Input Polarity Inverted, CMOS output drive. GP1 1 = GPIO1 Input Polarity Non-inverted, Open-Drain output drive. 0 = GPIO0 Input Polarity Inverted, CMOS output drive. GP0 1 = GPIO0 Input Polarity Non-inverted, Open-Drain output drive.
7.2.7.
GPIO Pin Sticky Register (50h)
Default: 0000h
D15 D7 D14 D6 D13 D5 Reserved Bit(s) 15:2 Access Read Only Reset Value 0 Name Reserved D12 D4 D11 Reserved D3 D10 D2 D9 D1 D8 D0
GS1 (GPIO1) GS0 (GPIO0) Description Bit not used, should read back 0
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Bit(s) 1 0
Access Read / Write Read / Write
Reset Value 0 0
Name GS1 GS0
Description 0 = GPIO1 Non Sticky configuration. 1 = GPIO1 Sticky configuration. 0 = GPIO0 Non Sticky configuration. 1 = GPIO0 Sticky configuration.
7.2.8.
GPIO Pin Mask Register (52h)
Default: 0000h
D15 D7 D14 D6 D13 D5 Reserved Bit(s) 15:2 1 0 Access Read Only Read / Write Read / Write Reset Value 0 0 0 Name Reserved GW1 GW0 D12 D11 D10 D2 D9 D1 D8 D0
Reserved D4 D3
GW1 (GPIO1) GW0 (GPIO0) Description Bit not used, should read back 0 0 = GPIO1 interrupt not passed to GPIO_INT slot 12. 1 = GPIO1 interrupt is passed to GPIO_INT slot 12. 0 = GPIO0 interrupt not passed to GPIO_INT slot 12. 1 = GPIO0 interrupt is passed to GPIO_INT slot 12.
7.2.9.
GPIO Pin Status Register (54h)
Default: 0000h
D15 D7 D14 D6 D13 D5 Reserved Bit(s) 15:2 Access D12 D4 D11 Reserved D3 D2 D1 GI1 (GPIO1) D0 GI0 (GPIO0) D10 D9 D8
1
0
Reset Name Description Value ReadOnly 0 Rsvd Bit not used, should read back 0 When GPIO1 is configured as output and Register h74 bit[0] = 0 (default), the value of this register will be placed on the GPIO1 pad. When GPIO1 is configured as output and Register h74 bit[0] = 1, the GPIO1 pad Read / will get its value from slot12. x GI1 Write When GPIO1 is configured as input and configured as a sticky writing a 1 does nothing, writing a 0 clears this bit. When GPIO1 is configured as input this register reflects the value on the GPIO1 pad after interpretation of the polarity and sticky configurations. When GPIO0 is configured as output and Register h74 bit[0] = 0 (default), the value of this register will be placed on the GPIO0 pad. When GPIO0 is configured as output and Register h74 bit[0] = 1, the GPIO0 pad Read / will get its value from slot12. x GI0 Write When GPIO0 is configured as input and configured as a sticky writing a 1 does nothing, writing a 0 clears this bit. When GPIO0 is configured as input this register reflects the value on the GPIO0 pad after interpretation of the polarity and sticky configurations.
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7.3.
Extended CODEC Registers Page Structure Definition
Registers 60h-68h are the Extended CODEC Registers: These registers allow for the definition of further capabilities. These bits provide a paged address space for extended CODEC information. The Page Selector bits in the Audio Interrupt and Paging register (Register 24h bits 3:0) control the page of information viewed through this page window.
7.3.1.
Extended Registers Page 00
Page 00 of the Extended CODEC Registers is reserved for vendor specific use. Driver writers should not access these registers unless the Vendor ID register has been checked first to ensure that the vendor of the AC '97 component has been identified and the usage of the vendor defined registers understood.
7.3.2.
Extended Registers Page 01
The usage of Page 01 of the Extended CODEC Registers is defined in Register 24h found in Section7.1.17: page61.
7.3.3.
Extended Registers Page 02, 03
Pages 02 and 03 of the Extended CODEC Registers are reserved for future use.
7.4.
STAC9752A/9753A Paging Registers
The AC'97 Specification Rev 2.3 uses a paging mechanism in order to increase the number of registers. The registers currently used in the paging are 60h to 6Eh. Additional information about the Extended CODEC Registers, please refer to Section 7.3: page72. One of two pages can be made active at any time, set in Register 24h. Register 24h is the Audio Interrupt and Paging Register. Additional details about Register 24h is located in Section 7.1.17: page61. If page 00h is active, registers 60h to 6Eh are Vendor Specific. If page 01h is active, registers 60h to 6Eh have the following functionality:
Reg NAME FUNCTION Provides the CODEC Class and a Vendor specified revision identifier. Allows for population by the system BIOS to identify the PCI Sub System Vendor ID. Allows for population by the system BIOS to identify the PCI Sub System ID. Provides the type of audio function being selected and which jack conductor the selected value is measured from. Location 7.4.1: page73 7.4.2: page73 Note:: page74 Note:: page74
60h CODECClass/Revision 62h 64h 66h PCI SVID PCI SSID Function Select
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Reg 68h 6Ah 6Ch 6Eh
NAME Function Information Sense Register
FUNCTION Includes information about Gain, Inversion, Buffer delays, Information Validity, and Function Information presence. Includes information about the connector/jack location, Input verses Output sensing, the Order of the sense results, and the IDT specific sense results. Reserved Reserved
Location 7.4.5: page75 7.4.7: page78
7.4.1.
CODEC Class/Rev (60h Page 01h)
Register 24h must be set to Page 01h to access this register. Default: 12xxh
D15 D7 RV7 Bit(s) 15-13 D14 Reserved D6 RV6 Reset Value D5 RV5 Name Reserved D13 D12 CL4 D4 RV4 D11 CL3 D3 RV3 D10 CL2 D2 RV2 D9 CL1 D1 RV1 D8 CL0 D0 RV0
12-8
CL4:CL0
7-0
RV7:RV0
Description Reserved -NOT DEFINED CODEC Compatibility Class (RO) This is a CODEC vendor specific field to define software compatibility for the CODEC. Software reads this field, together with CODEC vendor ID (reg 7C-7Eh), to determine vendor specific programming interface compatibility. Software can rely on vendor specific register behavior to be compatible among vendor CODECs of the same class. 00h - Field not implemented 01h-1Fh - Vendor specific compatibility class code Equals Vendor ID2(Reg 7Eh) bits D7 to D0 Revision ID: (RO) This register specifies a device specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. This field should be viewed as a vendor defined extension to the CODEC ID. This number changes with new CODEC stepping of the same CODEC ID.
7.4.2.
PCI SVID (62h Page 01h)
Register 24h must be set to Page 01h to access this register. Default: FFFFh
D15 PVI15 D7 PVI7 D14 PVI14 D6 PVI6 D13 PVI13 D5 PVI5 D12 PVI12 D4 PVI4 D11 PVI11 D3 PVI3 D10 PVI10 D2 PVI2 D9 PVI9 D1 PVI1 D8 PVI8 D0 PVI0
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Bit(s) Reset Value
15-0
Description PCI Sub System Vendor ID: This field provides the PCI Sub System Vendor ID of the Audio or Modem Sub PVI15:PVI0 Assembly Vendor (i.e., CNR manufacturer, Motherboard Vendor). This is NOT the CODEC vendor PCI Vendor ID, nor the AC '97 controller PCI Vendor ID. If data is not available, returns FFFFh. Note: This register is populated by the BIOS and does not reset on RESET#.
Name
7.4.3.
PCI SSID (64h Page 01h)
Register 24h must be set to Page 01h to access this register. Default: FFFFh
D15 PI15 D7 PI7 D14 PI14 D6 PI6 Name D13 PI13 D5 PI5 D12 PI12 D4 PI4 D11 PI11 D3 PI3 D10 PI10 D2 PI2 D9 PI9 D1 PI1 D8 PI8 D0 PI0
Bit(s) Reset Value
15-0
Description PCI Sub System ID: This field provides the PCI Sub System ID of the Audio or Modem Sub Assembly (i.e., CNR Model, Motherboard SKU). This is NOT the CODEC vendor PCI ID, nor PI15:PVI0 the AC '97 controller PCI ID. Information in this field must be available for AC '97 controller reads when CODEC ready is asserted in AC link.If data is not available, returns FFFFh.
Note: This register is populated by the BIOS and does not reset on RESET#.
7.4.4.
Function Select (66h Page 01h)
Register 24h must be set to Page 01h to access this register. Default: 0000h
D15 D7 D14 D6 Reserved D13 D5 D12 Reserved D4 FC3 D3 FC2 D2 FC1 D1 FC0 D0 T/R D11 D10 D9 D8
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Bit(s) Reset Value Name Description 15-5 Reserved Reserved Function Code bits: 00h - Line Out (Master Out) 01h - Head Phone Out (AUX Out) Setting the T/R bit to 0 = Left, 1 = Right 02h - DAC 3 (C/LFE) - Not Supported 03h - SPDIF out 04h - Phone In 05h - Mic1 (Mic select = 0) 06h - Mic2 (Mic select = 1) 07h - Line In 08h - CD In 09h - Video In 4-1 00h FC3:FC0 0Ah - Aux In 0Bh - Mono Out 0C-0Fh - Reserved For supported Jack and Mic Sense Functions, see Table22: page75. The Function Code Bits are used to read Register 68h (Page 01h) and Register 6Ah (Page 01h). Mono I/O should report relevant sense and function information on Tip, and report not supported on Ring. Setting the function code to unsupported values will return a 0 when accessing the Information Valid Bit in page 01 register 68h bit 5. Tip or Ring selection Bit.This bit sets which jack conductor the sense value is measured from. Software will program the corresponding the Ring/Tip selector bit together with the I/O number in bits FC[3:0]. 0 - Tip (Left) 1 - Ring (Right)
0
0
T/R
Note: This register does not reset on RESET#. Table 22. Supported Jack and Mic Sense Functions Function Code 00h 01h 05h 06h I/O Line_Out Headphone_Out Mic1 Mic2 Sense Capability Jack Sense Jack Sense Mic Sense Mic Sense
7.4.5.
Function Information (68h Page 01h)
Register 24h must be set to Page 01h to access this register.
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Default: 00xxh, see table 23: page77.
D15 G4 D7 DL2 D14 G3 D6 DL1 Name D13 G2 D5 DL0 D12 G1 D4 IV D11 G0 D3 D10 INV D2 Reserved D9 DL4 D1 D8 DL3 D0 FIP
Bit(s) Reset Value
15
0
G4
14-11
0
G3:G0
10
INV
9-5
DL4:DL0
Description Gain Sign Bit: The CODEC updates this bit with the sign of the gain value present in G[3:0]. The BIOS updates this to take into consideration external amplifiers or other external logic when relevant. G[4] indicates whether the value is a gain or attenuation. Gain in the G4 bit is in terms of dB. This bit is Read/Write and only reset on POR and not by RESET#. Gain Bits: The CODEC updates these bits with the gain value (dB relative to level-out) in 1.5dBV increments. The BIOS updates these to take into consideration external amplifiers or other external logic when relevant. G[0:3] indicates the magnitude of the gain. G[4] indicates whether the value is a gain or attenuation. For Gain/Attenuation settings, see Table 24: page77. These bits are read/write and are not reset on RESET#. Inversion bit: Indicates that the CODEC presents a 180 degree phase shift to the signal. 0h - No inversion reported 1h - Inverted This bit is read/write and is not reset on RESET#. BIOS should invert for each inverting gain stage. Buffer delays: CODEC will provide number a delay measurement for the input and output channels. Software will use this value to accurately calculate audio stream position with respect to what is been reproduced or recorded. These values are in 20.83 sec (1/48000 second) units. For output channels, this timing is from the end of AC Link frame in which the sample is provided, until the time the analog signal appears at the output pin. For input streams, this is from when the analog signal is presented at the pin until the representative sample is provided on the AC Link. Analog in and out paths are not considered as part of this delay. The measurement is a 'typical' measurement, at a 48KHz sample rate, with minimal in-CODEC processing (i.e., 3D effects are turned off.) 00h - Information not provided 01h...1Eh - Buffer delay in 20.83 sec units 1Fh - reserved These bits are read/write and are not reset on RESET#. The default value is the delay internal to the CODEC. The BIOS may add to this value the known delays external to the CODEC, such as for an external amplifier.
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Bit(s) Reset Value
Name
4
1
IV
3-1 0
0 NA
Reserved FIP
Description Information Valid Bit: Indicates whether a sensing method is provided by the CODEC and if information field is valid. This field is updated by the CODEC. 0h--After CODEC RESET# de-assertion, it indicates the CODEC does NOT provides sensing logic and this bit will be Read Only. After a sense cycle is completed indicates that no information is provided on the sensing method. 1h--After CODEC RESET# de-assertion, it indicates the CODEC provides sensing logic for this I/O and this bit is Read/Write. After clearing this bit by writing1, when a sense cycle is completed the assertion of this bit indicates that there is valid information in the remaining descriptor bits. Writing 0 to this bit has no effect. BIOS should NOT write this bit, as it is reset on RESET#. Bit not used, should read back 0 Function Information Present This bit is set to a 1 indicates that the G[4:0], INV, DL[4:0](Register 68h, Page 01h) and ST[2:0](register 6Ah, Page 01h) are supported and R/W capable. This bit is Read Only. Table 23. Reg 68h Default Values
Reg 66h Function Code 00h Line Out 01h Headphone Out 05h Mic1 06h Mic2
Reg 68h Default Value 0010h 0010h 0010h 0010h
All other Function Codes 0000h For RESET#: Reg 68h default value is 0000h. Table 24. Gain or Attenuation Examples G[4:0] 00000 00001 01111 10001 11111 Gain or Attenuation (dB relative to level-out) 0 dBV +1.5 dBV +24 dBV -1.5 dBV -24 dBV Table 25. Register 68h/Page 01h Bit Overview Bit D5:D15 D4 D3:1 D0 Bit R/W Overview Read/Write and only reset on POR (Power on Reset) and not by RESET#. Read/Write and should NOT be set by the BIOS Reserved Read Only.
7.4.6.
Digital Audio Control (6Ah, Page 00h)
To access Register 6Ah, Page 00h must be selected in Register 24h.
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Default: 0000h
D15 D7 D14 D6 D13 D5 Reserved Name Reserved SPOR D12 Reserved D4 D3 D2 SPOR D1 DO1 D0 RSVD D11 D10 D9 D8
Bit(s) Reset Value 15:3 0 2 0
1 0
0 0
DO1 Reserved
Description Bits not used, should read back 0 Over-ride Register 2Ah, D12 write-lock when SPDIF_EN = 1. All bits except SPDIF sample-rate are affected (D13-D12). Allows for sub-code changing on-the-fly. SPDIF Digital Output Source Selection: DO1 = 0; PCM data from the AC-Link to SPDIF DO1 = 1; ADC record data to SPDIF Bits not used, should read back 0
7.4.7.
Sense Details (6Ah Page 01h)
Register 24h must be set to Page 01h to access this register. Default: NA
D15 ST2 D7 OR1 D14 ST1 D6 OR0 Name D13 ST0 D5 SR5 D12 S4 D4 SR4 D11 S3 D3 SR3 D10 S2 D2 SR2 D9 S1 D1 SR1 D8 S0 D0 SR1
Bit(s) Reset Value
15-13
12-8
Description Connector/Jack location bits This field describes the location of the jack in the system. 0h - Rear I/O Panel 1h - Front Panel ST2:ST0 2h - Motherboard 3h - Dock/External 4h:6h - Reserved 7h - No Connection/unused I/O These bits are Read/Write. Sensed bits meaning relates to the I/O being sense as output or inputs. Sensed bits (outputs): See Table 26: page79. This field allows for the reporting of the type of output peripheral/device plugged in the jack. Values specified below should be interrogated in conjunction with the SR[5:0] and OR[1:0] bits for accurate reporting. S4:S0 Sensed bits (inputs): See Table 27: page79. This field allows for the reporting of the type of input peripheral/device plugged in the jack. Values specified below should be interrogated in conjunction with the SR[5:0] and OR[1:0] bits for accurate reporting. This field is Read Only.
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Bit(s) Reset Value
Name
7-6
OR1:0
Description Order Bits. These bits indicate the order the sense result bits SR[5:0] are using. 00 - 100 (i.e., Ohms) 01 - 101 (i.e., 10 Ohms) 10 - 102 (i.e., 100 Ohms) 11 - 103 (i.e., 1K Ohms) Sense Result bits These bits are used to report a vendor specific fingerprint or value. (Resistance, impedance, reactance, ect). This field is Read Only. Table 26. Sensed Bits (Outputs)
5-0
SR5:SR0
Reported Value 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh-Eh Fh
Output Peripheral/Device Data not valid. Indicates that the reported value(s) is invalid. No connection. Indicates that there are no connected devices. Fingerprint. Indicates a specific fingerprint value for devices that are not specified or unknown. Speakers (8 ohms) Speakers (4 ohms) Powered Speakers Stereo Headphone Reserved Reserved Headset (mono speaker left channel and mic.) Other. Allows a vendor to report sensing other type of devices/peripherals. SR[5:0] together with OR[1:0] provide information regarding the type of device sensed. Reserved Unknown (use fingerprint) Table 27. Sensed Bits (Inputs)
Reported Value 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh-Eh Fh
Input Peripheral/Device Data not valid. Indicates that the reported value(s) is invalid. No connection. Indicates that there are no connected devices. Fingerprint. Indicates a specific fingerprint value for devices that are not specified. Microphone (mono) Reserved Stereo Line In (CE device attached) Reserved Reserved Reserved Headset (mono speaker left channel and mic.) Other. Allows a vendor to report sensing other type of devices/peripherals. SR[5:0] together with OR[1:0] provide information regarding the type of device sensed. Reserved Unknown (use fingerprint)
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7.4.8.
Revision Code (6Ch)
To access Register 6Ch, Page 00h must be selected in Register 24h. Default: xxxxh
D15 D7 D14 D6 D13 D5 D12 D11 MINORREV D4 D3 MAJORREV Bit(s) Reset Value 15:8 7:0 00h xx Description Minor Revision ID. These bits are read only and will be updated based on minor MINORREV device changes which will not require software changes. Major Revision ID. These bits are read only and will be updated based on major MAJORREV device changes. Name D10 D2 D9 D1 D8 D0
7.4.9.
Analog Special (6Eh)
To access Register 6Eh, Page 00h must be selected in Register 24h. Default: 1000h
D15 D7 RSVD D14 Reserved D6 MUTEFIX DISABLE D13 D5 ADCSLT1 Name Reserved D12 AC97MIX D4 ADCSLT0 D11 D3 D10 D2 D9 Reserved D1 D8 D0 SPLYOVR VAL
RSVD MIC GAIN VAL SPLYOVR EN
Bit(s) Reset Value 15:13 0
12
1
AC97MIX
11:7
0
Reserved MUTEFIX DISABLE
6
0
Description Bits not used, should read back 0 0 = mixer record contains a mix of all mono and stereo analog input signals, not the DAC (ALL ANALOG mode) 1 = mixer record contains a mix of all mono and stereo analog input signals plus the DAC signal (AC97 mode) This bit only has an effect when either Stereo Mix or Mono Mix is selected as the record source in Reg. 1Ah. The "ALL" mode is useful in conjunction with the POP BYPASS mode (Reg. 20h;D15) to record all analog sources, perform further processing in the digital domain, including combining with other PCM data, and routing through the DACs directly to Line Out, Headphone Out, or Mono Out. A Stereo Mix recording will be affected by the setting of the 3D Effects bit (Reg. 20h;D13) Bits not used, should read back 0 0 = MUTE FIX Enabled 1 = MUTE FIX Disabled When this bit is zero, and either channel is set to -46.5dB attenuation, 1Fh, then that channel is fully muted. When this bit is one, then operation is per AC'97 specification.
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Bit(s) Reset Value
5:4
0
3
0
2
0
Description Select slots for ADC data on ACLINK 00 = left slot 3, right slot 4 ADCSLT1:0 01 = left slot 7, right slot 8 10 = left slot 6, right slot 9 11 = left slot 10, right slot 11 Reserved Reserved Adds +10dB gain to the selected MIC input. Use in conjunction with BOOSTEN (Reg. 0Eh;D6) BOOSTEN MICGAINVAL MIC GAIN VAL 0 0 = 0 dB 0 1 = 10 dB 1 0 = 20 dB 1 1 = 30 dB Supply Override bit allows override of the supply detect. SPLYOVR_EN 0 = no override on supply detect 1 = override supply detect with bit 0 Supply Override Value provides the analog voltage operation values.
Name
1
0
0
0
SPLYOVR_VA L 0 = force 3.3 V operation 1 = force 5 V operation
7.4.10.
Analog Current Adjust (72h)
To unlock Register 72h, write 0xABBA to Register 70h. Default: 0000h
D15 D7 INT APOP D14 D6 D13 D5 D12 D4 D11 Reserved D3 Reserved D2 D1 D0 D10 D9 D8
Bit(s) Reset Value 15:8 0
7
0
6:0
0
Description Reserved 0 = Anti Pop Enabled 1 = Anti Pop Disabled The STAC9752A/9753A includes an internal power supply anti-pop circuit that prevents audible clicks and pops from being heard when the CODEC is powered on and off. This function is accomplished by delaying the charge/discharge of the VREF capacitor (Pin 27). C VREF value of 1 F will cause a turn-on delay of INT_APOP roughly 3 seconds, which will allow the power supplies to stabilize before the CODEC outputs are enabled. The delay will be extended to 30 seconds if a value of C VREF value of 10 F is used. The CODEC outputs are also kept stable for the same amount of time at power-off to allow the system to be gracefully turned off. The INT_APOP bit allows this delay circuit to be bypassed for rapid production testing. Any external component anti-pop circuit is unaffected by the internal circuit. Reserved Reserved
Name Reserved
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7.4.11.
EAPD Access Register (74h)
Default: 0800h
D15 EAPD D7 D14 D6 D13 Reserved D5 Reserved Bit(s) Reset Value 15 14:12 11 10:3 0 0 1 0 Name D12 D4 D11 EAPD_OEN D3 D10 D2 INTDIS D9 Reserved D1 GPIOACC D8 D0 GPIOSLT12
Description EAPD data Enable EAPD EAPD data output on EAPD when bit D11 = 1 EAPD data input from pin when bit D11 = 0 Reserved Bit not used, should read back 0 EAPD Pin Enable EAPD_OEN 0 = EAPD configured as input pin 1 = EAPD configured as output pin Reserved Bit not used, should read back 0 Interrupt disable option. Interrupts cleared by writing a 1 to I4 (Reg24h:D15) 0 = will clear both SENSE and GPIO interrupts 1 = will only clear SENSE interrupts. GPIO interrupts will have to be cleared in Reg54h. GPIO ACCESS GPIOACC 0 = ACLINK access from GPIO Pads 1 = ACLINK access from GPIO Register 54h 0 = GPIO0/1 access via Reg54h when GPIO is set as an output, for input Slot12 data will be 0h. 1 = GPIO0/1 access via Slot 12 when GPIO is set as an output, for inputs GPIOSLT12 Reg54h will not be updated. This can only be used if a modem CODEC is not present in the system and using Slot12. INTDIS
2
0
1
0
0
0
7.4.12.
Register 78h Enable (76h)
Default: 0000h
D15 EN15 D7 EN7 D14 EN14 D6 EN6 D13 EN13 D5 EN5 D12 EN12 D4 EN4 D11 EN11 D3 EN3 D10 EN10 D2 EN2 D9 EN9 D1 EN1 D8 EN8 D0 EN0
7.4.13.
Universal Jacks TM Selection (78h)
To unlock Register 78h, write 0xABBA to Register 76h.
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Default: 0000h
D15 HP SEL D7 STMIC SEL D6 MSPWDN D5 HP3dB D14 D13 LO SEL D4 DACBYHP D12 D11 RSVD D3 DACBYLO D10 LI SEL D2 Reserved D1 Reserved D9 MIC SEL D0 ADC HPF BYP D8
Bit(s)
Reset Value
Name Headphone Amp Selection 00 - HP on pins 39/41 (default) 01 - HP on pins 35/36 10 - Off 11 - Off Line Out Selection 00 - LO on pins 35/36 (default) 01 - LO on pins 23/24 10 - Off 11 - Off Reserved Line In Selection 0 - LI on pins 23/24 (default) 1 - LI on pins 35/36 Microphone Selection 00 - MIC on pins 21/22 (default) 01 - MIC on pins 23/24 10 - MIC on pins 35/36 11 - MIC on pins 39/41 Stereo MIC Select 0 - Mono MIC 1 - Stereo MIC MIC Sense Power Down 0 - On 1 - Off Headphone 3dB 0 - Off 1 - On
Description
15:14
00
HP SEL
13:12
00
LO SEL
11 10
0 00
RSVD LI SEL
9:8
00
MIC SEL
7
0
STMIC SEL
6
0
MSPWDN
5
0
HP3dB
4
0
DACBYPHP
Independent DAC bypass for HP Volume (Reg 04h) This can be over ridden by Reg 20h D15, pop bypass 0 - Off 1 - On Independent DAC bypass for LO Volume (Reg 02h) This can be over ridden by Reg 20h D15, pop bypass 0 - Off 1 - On Reserved
3
0
DACBYPLO
2
0
Reserved
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Bit(s) 1 0
Reset Value 0 0
Name Reserved ADC HPF BYP Reserved
Description
0 = Normal operation, (ADC High Pass Filter active) 1 = ADC High Pass Filter Bypass
7.5.
Vendor ID1 and ID2 (Index 7Ch and 7Eh)
These two registers contain four 8-bit ID codes. The first three codes have been assigned by Microsoft using their Plug and Play Vendor ID methodology. The fourth code is a IDT assigned code identifying the STAC9752A/9753A. The ID1 register (index 7Ch) contains the value 8384h, which is the first (83h) and second (84h) bytes of the Microsoft ID code. The ID2 register (index 7Eh) contains the value 7652h, which is the third (76h) byte of the Microsoft ID code, and 52h which is the STAC9752A/9753A ID code.
7.5.1.
Vendor ID1 (7Ch)
Default: 8384h
D15 1 D7 1 D14 0 D6 0 D13 0 D5 0 D12 0 D4 0 D11 0 D3 0 D10 0 D2 1 D9 1 D1 0 D8 1 D0 0
7.5.2.
Vendor ID2 (7Eh)
Default: 7652h
D15 0 D7 0 D14 1 D6 1 D13 1 D5 0 D12 1 D4 1 D11 0 D3 0 D10 1 D2 0 D9 1 D1 1 D8 0 D0 0
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8. LOW POWER MODES
The STAC9752A/9753A is capable of operating at reduced power when no activity is required. The state of power down is controlled by the Powerdown Register (26h). There are seven separate commands of power down. The power down options are listed in Table 28. The first three bits, PR0..PR2, can be used individually or in combination with each other, and control power distribution to the ADCs, DACs and Mixer. The last analog power control bit, PR3, affects analog bias and reference voltages, and can only be used in combination with PR1, PR2, and PR3. PR3 essentially removes power from all analog sections of the CODEC, and is generally only asserted when the CODEC will not be needed for long periods. PR0 and PR1 control the PCM ADCs and DACs only. PR2 and PR3 do not need to be "set" before a PR4, but PR0 and PR1 should be "set" before PR4. PR5 disables the DSP clock and does not require an external cold reset for recovery. PR6 disables the headphone driver amplifier for additional analog power saving.
Table 28. Low Power Modes GRP Bits PR0 PR1 PR2 PR3 PR4 PR5 PR6 Function PCM in ADCs & Input Mux Powerdown PCM out DACs Powerdown Analog Mixer powerdown (VREF still on) Analog Mixer powerdown (VREF off) Digital Interface (AC-Link) powerdown (BIT CLK forced low) Digital Clock disable, BIT CLK still on Powerdown HEADPHONE_OUT
Figure 22. Example of STAC9752A/9753A Powerdown/Powerup Flow
PR0=1 PR1=1 PR2=1 PR4=1
Normal
ADCs off PR0
DACs off PR1
Analog off PR2 or PR3
Digital I/F off PR4
Shut off AC-Link
PR0=0 & ADC=1
PR1=0 & DAC=1
PR2=0 & ANL=1
Warm Reset
Default Ready =1 Cold Reset
The Figure 22 illustrates one example procedure to do a complete powerdown of STAC9752A/ 9753A . From normal operation, sequential writes to the Powerdown Register are performed to power down STAC9752A/9753A a section at a time. After everything has been shut off, a final write (of PR4) can be executed to shut down the AC-Link. The part will remain in sleep mode with all its registers holding their static values. To wake up, the AC'97 Controller will send an extended pulse on the sync line, issuing a warm reset. This will restart the AC-Link (resetting PR4 to zero). The STAC9752A/9753A can also be woken up with a cold reset. A cold reset will reset all of the registers to their default states (Paged Registers are semi-exempt). When a section is powered back on, the Powerdown Control/Status register (index 26h) should be read to verify that the section is ready (stable) before attempting any operation that requires it.
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Figure 23. Powerdown/Powerup Flow With Analog Still Alive PR0=1 PR1=1 PR4=1
Normal
ADCs off PR0
DACs off PR1
Digital I/F off PR4
Shut off AC-Link
PR0=0 & ADC=1
PR1=0 & DAC=1
Warm Reset
Figure 23 illustrates a state when all the mixers should work with the static volume settings that are contained in their associated registers. This configuration can be used when playing a CD (or external LINE_IN source) through the STAC9752A/9753A to the speakers, while most of the system in low power mode. The procedure for this follows the previous example, except that the analog mixer is never shut down.
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9. MULTIPLE CODEC SUPPORT
The STAC9752A/9753A provides support for the multi-CODEC option according to the Intel AC'97, rev 2.3 specification. By definition there can be only one Primary CODEC (CODEC ID 00) and up to three Secondary CODECs (CODEC IDs 01,10, and 11). The CODEC ID functions as a chip select. Secondary devices therefore have completely orthogonal register sets; each is individually accessible and they do not share registers.
9.1.
Primary/Secondary CODEC Selection
In a multi-CODEC environment the CODEC ID is provided by external programming of pins 45 and 46 (CID0 and CID1). The CID pin electrical function is logically inverted from the CODEC ID designation. The corresponding pin state and its associated CODEC ID are listed in the "CODEC ID Selection" table. Also see slot assignment discussion, "Multi-Channel Programming Register (Index 74)".
Table 29. CODEC ID Selection CID1 State DVdd or floating DVdd or floating 0V 0V CID0 State DVdd or floating 0V DVdd or floating 0V CODEC ID 00 01 10 11 CODEC Status Primary Secondary Secondary Secondary
9.1.1.
Primary CODEC Operation
As a Primary device the STAC9752A/9753A is completely compatible with existing AC'97 definitions and extensions. Primary CODEC registers are accessed exactly as defined in the AC'97 Component Specification and AC'97 Extensions. The STAC9752A/9753A operates as Primary by default, and the external ID pins (45 and 46), have internal pull-ups so that these pins may be left as no-connects for primary operation. When used as the Primary CODEC, the STAC9752A/9753A generates the master AC-Link BIT_CLK for both the AC'97 Digital Controller and any Secondary CODECs. The STAC9752A/ 9753A can support up to four, 10K / 50pF loads on the BIT_CLK output. This is to ensure that up to four CODEC implementations will not load down the clock output.
9.1.2.
Secondary CODEC Operation
When the STAC9752A/9753A is configured as a Secondary device the BIT_CLK pin is configured as an input at power up. Using the BIT_CLK provided by the Primary CODEC insures that everything on the AC-Link will be synchronous. As a Secondary device, it can be defined as CODEC ID 01, 10, or 11 in the two-bit field(s) of the Extended Audio and/or Extended Modem ID Register(s).
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9.2.
Secondary CODEC Register Access Definitions
The AC'97 Digital Controller can independently access Primary and Secondary CODEC registers by using a 2-bit CODEC ID field (chip select) which is defined as the LSBs of Output Slot 0. For Secondary CODEC access, the AC'97 Digital Controller must invalidate the tag bits for Slot 1 and 2 Command Address and Data (Slot 0, bits 14 and 13) and place a non-zero value (01, 10, or 11) into the CODEC ID field (Slot 0, bits 1 and 0). As a Secondary CODEC, the STAC9752A/9753A will disregard the Command Address and Command Data (Slot 0, bits 14 and 13) tag bits unless it sees a 2-bit CODEC ID value (Slot 0, bits 1 and 0) that matches its configuration. In a sense the Secondary CODEC ID field functions as an alternative Valid Command Address (for Secondary reads and writes) and Command Data (for Secondary writes) tag indicator. Secondary CODECs must monitor the Frame Valid bit, and ignore the frame (regardless of the state of the Secondary CODEC ID bits) if it is not valid. AC'97 Digital Controllers should set the frame valid bit for a frame with a secondary register access, even if no other bits in the output tag slot except the Secondary CODEC ID bits are set. This method is designed to be backward compatible with existing AC'97 controllers and CODECs. There is no change to output Slot 1 or 2 definitions.
Table 30. Secondary CODEC Register Access Slot 0 Bit Definitions Output Tag Slot (16-bits) Bit 15 14 13 12-3 2 Description Frame Valid Slot 1 Valid Command Address bit (Primary CODEC only) Slot 2 Valid Command Data bit (Primary CODEC only) Slot 3-12 Valid bits as defined by AC'97 Reserved (Set to "0")
1-0 2-bit CODEC ID field (00 reserved for Primary; 01, 10, 11 indicate Secondary) Note: New definitions for Secondary CODEC Register Access
Using three CODECs typically requires a controller to support SDATA_IN2.
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10. TESTABILITY
The STAC9752A/9753A has two test modes. One is for ATE in-circuit test and the other is restricted for IDT's internal use. STAC9752A/9753A enters the ATE in-circuit test mode if SDATA_OUT is sampled high at the trailing edge of RESET#. Once in the ATE test mode, the digital AC-Link outputs (BIT_CLK and SDATA_IN) are driven to a high impedance state. This allows ATE in-circuit testing of the AC'97 controller. Use of the ATE test mode is the recommended means of removing the CODEC from the AC-Link when another CODEC is to be used as the primary. This case will never occur during standard operating conditions. Once either of the two test modes have been entered, the STAC9752A/9753A must be issued another RESET# with all AC-Link signals held low to return to the normal operating mode.
Table 31. Test Mode Activation SYNC 0 0 1 1 SDATA_OUT 0 1 0 1 Description Normal AC '97 operation ATE Test Mode IDT Internal Test Mode Reserved
10.1. ATE Test Mode
ATE test mode allows for in-circuit testing to be completed at board level. For this to work, the outputs of the device must be driven to a high impedance state (Z). Internal pullups for digital I/O pins must be disabled in this mode. This mode initiates on the rising edge of RESET# pin. Only a cold reset will exit the ATE Test Mode.
Table 32. ATE Test Mode Operation Pin Name SDATA_OUT BIT_CLK SDATA_IN SYNC RESET# N.C. N.C. N.C. GPIO0 GPIO1 CID0 CID1 EAPD SPDIF Pin # 5 6 8 10 11 31 33 34 43 44 45 46 47 48 Function 1 Z Z 0 1 Z Z Z Z Z Z Z Z Z Always an input Always an input Always an input Must be held low at rising edge of RESET# Description Must be held high at the rising edge of RESET#
Note: Pins 31, 33, and 34 are NO CONNECTS.
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11. STAC9752A/9753A PIN DESCRIPTION 11.1. Pin Description for the 48-pin LQFP Package
Figure 24. Pin Description Drawing
MONO_OUT AVdd2 HP_OUT_L No Connect HP_OUT_R AVss2 GPIO0 GPIO1 CID0 CID1 EAPD SPDIF OUT
37 38 39 40 41 42 43 44 45 46 47 48
36 35 34 33 32 31 30 29 28 27 26 25
LINE_OUT_R LINE_OUT_L NC NC CAP2 NC AFILT2 AFILT1 VREFout VREF AVss1 AVdd1
48 pin LQFP
24 23 22 21 20 19 18 17 16 15 14 13
LINE_IN_R LINE_IN_L MIC2 MIC1 CD_R CD_GND CD_L VIDEO_R VIDEO_L AUX_R AUX_L PHONE
Pin 48: To Disable SPDIF, use an 1K - 1 0 K external pullup resistor. Pin 19: The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at about 2.5V. The name of the pin in the AC'97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to ground will change the internal bias of the entire CODEC, and cause significant distortion. If there is no analog CD input, then this pin can be No-Connect.
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DVdd1 1 XTL_IN 2 XTL_OUT 3 DVss1 4 SDATA_OUT 5 BIT_CLK 6 DVss2 7 SDATA_IN 8 DVdd2 9 SYNC 10 RESET# 11 PC_BEEP 12
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11.2. Pinout List 48-pin LQFP Package
Table 33. STAC9752A/9753A 48 Pin LQFP Pin List Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN Name DVDD XTAL_IN XTAL_OUT DVSS1 SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD SYNC RESET# PC_BEEP PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD L CD GND ** CD R MIC_L MIC_R LINE_IN_L LINE_IN_R Pin# 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name AVDD1 AVSS1 VREF IN VREF_OUT AFILT1 AFILT2 N.C. CAP2 N.C. N.C. Line_Out_L Line_Out_R MONO AVDD2 HP_L No Connect HP_R AVSS3 GPIO0 GPIO1 CID0 CID1 EAPD / GPIO S/PDIF-OUT
Pin 48: To Disable SPDIF, use an 1K - 1 0 K external pullup resistor. ** The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at about 2.5V. The name of the pin in the AC'97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to ground will change the internal bias of the entire CODEC, and cause significant distortion. If there is no analog CD input, then this pin can be No-Connect.
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11.3. Pin Description for the 32-pad QFN Package
Figure 25. STAC9752A/9753A 32 pad QFN Pin Description Drawing
MONO_OUT AVDD2 HP_L HP_R AVSS GPIO3 EAPD/GPIO4 SPDIF-OUT
25 26 27 28 29 30 31 32
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
LINE_OUT_R LINE_OUT_L CAP2 AFILT2 AFILT1 VREF_OUT VREF AVSS1
32 pad QFN
LINE_IN_R LINE_IN_L MIC 2 MIC 1 CD_R CD_GND CD_L PHONE
Pin 32: To Disable SPDIF, use an 1K - 1 0 K external pullup resistor. Pin 11: The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at about 2.5V. The name of the pin in the AC'97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to ground will change the internal bias of the entire CODEC, and cause significant distortion. If there is no analog CD input, then this pin can be No-Connect.
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CLOCK_IN SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD SYNC RESET#
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11.4. Pinout List 32-pad QFN Package
Table 34. STAC9752A/9753A 32 Pad QFN Pin List Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN Name CLOCK_IN SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD SYNC RESET# PHONE CD L CD GND ** CD R MIC 1 MIC 2 LINE IN L LINE IN R Pin# 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name AVSS1 VREF IN VREF_OUT AFILT1 AFILT2 CAP2 Line_Out_L Line_Out_R MONO AVDD2 HP_L HP_R AVSS3 GPIO1 EAPD / GPIO S/PDIF-OUT
Pin 32: To Disable SPDIF, use an 1K - 1 0 K external pullup resistor. Pin 11: The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at about 2.5V. The name of the pin in the AC'97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to ground will change the internal bias of the entire CODEC, and cause significant distortion. If there is no analog CD input, then this pin can be No-Connect.
11.5. STAC9752A/9753A Digital I/O
These signals connect the STAC9752A/9753A to its AC'97 controller counterpart, an external crystal, multi-CODEC selection and external audio amplifier.
Table 35. STAC9752A/9753A Digital Connection Signals Pin Name XTL_IN / CLOCK_IN XTL_OUT SDATA_OUT 48 LQFP 32 QFN Type Pin # Pin # 2 3 5 1 2 I I/O I Description Clock Input 24.576 MHz Crystal AC-Link Serial Data output (inbound stream) Internal Pull-up /Pull-down N/A N/A N/A
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Table 35. STAC9752A/9753A Digital Connection Signals Pin Name BIT_CLK SDATA_IN SYNC RESET# GPIO0 GPIO1 CID0 CID1 EAPD/GPIO SPDIF-OUT 48 LQFP 32 QFN Type Pin # Pin # 6 8 10 11 43 44 45 46 47 48 3 5 7 8 30 31 32 I/O O I/O O I I I/O I/O Description AC-Link Bit Clock AC-Link Serial Data input, (outbound stream) AC-Link Frame Sync AC-Link Reset General Purpose I/O General Purpose I/O Chip ID Select0 Chip ID Select1 External Amplifier Power Down General Purpose I/O SPDIF digital output Internal Pull-up /Pull-down Pull-down 50K +/- 25% N/A N/A N/A Pull-up 50K +/- 25% Pull-up 50K +/- 25% Pull-up 50K +/- 25% Pull-up 50K +/- 25% Pull-down 50K +/- 25% Pull-down 50K +/- 25%
11.6. STAC9752A/9753A Analog I/O
These signals connect the STAC9752A/9753A to analog sources and sinks, including microphones and speakers.
Table 36. STAC9752A/9753A Analog Connection Signals Pin Name PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1_L* MIC1_R* LINE_IN_L* LINE_IN_R* LINE_OUT_L* LINE_OUT_R* 48 LQFP 32 QFN Type Pin # Pin # 13 14 15 16 17 18 19 20 21 22 23 24 35 36 9 10 11 12 13 14 15 16 23 24 I^ I^ I^ I^ I^ I^ I^ I^ I^ I^ I* I* O* O* Phone Input Aux Left Channel Aux Right Channel Video Audio Left Channel Video Audio Right Channel CD Audio Left Channel CD Audio analog Return (see note 3) CD Audio Right Channel Desktop Microphone Input Second Microphone Input Line In Left Channel Line In Right Channel Line Out Left Channel (with headphone support) Line Out Right Channel (with headphone support) Description Internal Pull-up /Pull-down N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
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Table 36. STAC9752A/9753A Analog Connection Signals (Continued) Pin Name MONO_OUT HP_OUT_L* HP_OUT_R 48 LQFP 32 QFN Type Pin # Pin # 37 39 41 25 27 28 O O* O* Description To telephony subsystem speakerphone Headphone Out Left Channel Headphone Out Right Channel Internal Pull-up /Pull-down N/A N/A N/A
1.
^ any unused input pins should be tied together and connected through a capacitor (0.1 F suggested) to ground, except the MIC inputs which should have their own capacitor to ground if not used. * Universal JackTM capable. Only pins 35/36 OR 39/41 may be used to drive headphones. It is not possible to drive 2 sets of headphones at the same time. The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at about 2.5V. The name of the pin in the AC'97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to ground will change the internal bias of the entire CODEC, and cause significant distortion. If there is no analog CD input, then this pin can be No-Connect.
2. 3.
11.7. STAC9752A/9753A Filter/References
These signals are connected to resistors, capacitors, or specific voltages.
Table 37. STAC9752A/9753A Filtering and Voltage References Signal Name VREF IN VREFOUT AFILT0 AFILT1 CAP2 48 LQFP 32 QFN Type Pin # Pin # 27 28 29 30 32 18 19 20 21 20 O O O O O Analog ground Reference Voltage out 5mA drive Anti-Aliasign FIlter Cap - ADC Right Channel Anti-Aliasign FIlter Cap - ADC Left Channel ADC reference Cap Description Internal Pull-up /Pull-down N/A N/A N/A N/A N/A
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11.8. STAC9752A/9753A Power and Ground Signals
Pin Name AVdd2 AVss1 AVss3 DVdd2 DVss1 DVss2 48 LQFP Pin # 38 26 42 9 4 7 32 QFN Pin # 26 17 29 6 4 Type I I I I I I Description Analog Vdd = 5.0V or 3.3V Analog Gnd Analog Gnd Digital Vdd = 3.3V Digital Gnd Digital Gnd Internal Pull-up /Pull-down N/A N/A N/A N/A N/A N/A
Table 38. STAC9752A/9753A Power and Ground Signals
11.9. STAC9752A/9753A No Connects
These pins have no function and may be connected to traditional AC97 functions. 48 LQFP Pin # 31 33 34 40 32 QFN Pin # Internal Pull-up /Pull-down Pull-down 50K +/-25% Pull-down 50K +/-25% Pull-down 50K +/-25% Pin is high impedance, can be left floating
Pin Name N.C. N.C. N.C. N.C.
Type -
Description No Connect No Connect No Connect No Connect
Table 39. STAC9752A/9753A No Connects
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
96
STAC9752A/9753A
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
12. ORDERING INFORMATION Ordering Information
Part Number STAC9752AXTAEyyX STAC9753AXTAEyyX STAC9752AXNAEyyX STAC9753AXNAEyyX Package 48-pin RoHS QFP 7mm x 7mm x 1.4mm 48-pin RoHS QFP 7mm x 7mm x 1.4mm 32-pin RoHS QFN 5mm x 5mm x 0.9mm 32-pin RoHS QFN 5mm x 5mm x 0.9mm Temp Range 0 C to +70 C 0 C to +70 C 0 C to +70 C 0 C to +70 C Supply Range DVdd = 3.3V, AVdd = 5.0V DVdd = 3.3V, AVdd = 3.3V DVdd = 3.3V, AVdd = 5.0V DVdd = 3.3V, AVdd = 3.3V
Note: the yy is the revision. Comtact sales for currnet orderable information. Add an "R" to thye end fo rtape and reel delivery. MOQ is 2Ku for 48pin QFP and 2.5ku for 32pin QFN.
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
97
STAC9752A/9753A
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
13. PACKAGE DRAWINGS AND PC BOARD LAYOUT INFORMATION 13.1. 48-Pin LQFP
Figure 26. Package Drawing - 48-pin LQFP
A2
D D1
b
A A1
Key
A A1 A2 D D1 E E1 L e c b
c
LQFP Dimensions in mm Min. Nom. Max.
1.40 0.05 1.35 8.80 6.90 8.80 6.90 0.45 0.09 0.17 1.50 0.10 1.40 9.00 7.00 9.00 7.00 0.60 0.50 0.22 0.20 0.27 1.60 0.15 1.45 9.20 7.10 9.20 7.10 0.75
E1
48 pin LQFP
e
Pin 1
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
E
98
STAC9752A/9753A
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
13.2. 32-Pad QFN
Figure 27. Package Drawing - 32-pad QFN QFN Dimensions in mm Key A A1 A3 b D D1 E E1 e L D2 E2 ZD ZE R 0.30 3.20 3.20 0.18 Min 0 Nom 0.60 0.02 0.20 REF. 0.25 5.00 BSC 3.50 BSC 5.00 BSC 3.50 BSC 0.50 BSC 0.40 3.50 3.50 0.75 BSC 0.75 BSC 0.20~0.25 0.50 3.60 3.60 0.30 Max 0.80 0.05
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
99
STAC9752A/9753A
V 1.5 1206
STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
13.3. PC Board Recommendations for 32-pad QFN Package
Figure 28. Recommended PCB Layout for 32-pad QFN Package
SUGGESTED FOOTPRINT
4.75 mm
PAD DETAIL
0.30 mm 2.375 mm 32 0.15 mm 24
1
0.50 mm typical 0.375 mm 8 16 0.75 mm
2.375 mm 4.75 mm
NOTES: 1. Oblong pad is preferred geometry. 2. Oblong pad may be replaced with Rectangular pad of the same overall dimensions. 3. Oblong pad may be replaced with Bullet pad of the same overall dimensions. If a Bullet pad is used, flat shall be to the outside. 4. Solderpaste shall be oblong pad regardless of the pad geometry. Solderpaste opening shall be the same dimensions as pad detail. 5. Recommended solderpaste stencil thickness is 0.127 mm, electropolished. 6. Soldermask is to be 1 mm larger in X- and Y-dimensions.
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
100
STAC9752A/9753A
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
14. SOLDER REFLOW PROFILE 14.1. Standard Reflow Profile Data
Note: These devices can be hand soldered at 360 oC for 3 to 5 seconds. FROM: IPC / JEDEC J-STD-020C "Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices" (www.jedec.org/download).
Profile Feature Average Ramp-Up Rate (Tsmax - Tp) Preheat Time maintained above Temperature Min (Tsmin ) Temperature Max (Ts max) Time (ts min - tsmax ) Temperature (T L) Time (t L) 3 o C / second max 150 oC 200 oC 60 - 180 seconds 217 oC 60 - 150 seconds See "Package Classification Reflow Temperatures" on page 102. 20 - 40 seconds 6 o C / second max 8 minutes max Pb Free Assembly
Peak / Classification Temperature (Tp) Time within 5 oC of actual Peak Temperature (tp) Ramp-Down rate Time 25 o C to Peak Temperature
Note: All temperatures refer to topside of the package, measured on the package body surface.
Figure 29. Reflow Profile
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
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STAC9752A/9753A
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
14.2. Pb Free Process - Package Classification Reflow Temperatures
Package Type LQFP 48-pin QFN 32-pad MSL 3 3 Reflow Temperature 260 o C* 260 o C*
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
102
STAC9752A/9753A
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
15. APPENDIX A: PROGRAMMING REGISTERS
Reg # 00h 02h 04h 06h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 20h 22h 24h 26h 28h Name Reset Master Volume HP_OUT Mixer Volume Master Volume Mono PC_BEEP Volume Phone volume Mic Volume Line In Volume CD Volume Video Volume AUX Volume PCM Out Volume Record Select Record Gain General Purpose 3D Control Audio Int. & Paging Powerdownn Ctrl/Stat Extended Audio ID Extended Audio Control/ Status PCM DAC Rate PCM LR ADC Rate SPDIF Control Extended Modem Status GPIO Pin Config GPIO Pin Polarity/Type GPIO Pin Sticky GPIO Pin Mask GPIO Pin Status Reserved CL4 CL3 CL2 I4 EAPD ID1 I3 PR6 ID0 PRL/ RSVD SR14 SR14 DRS I2 PR5 I1 PR4 I0 PR3 REV 1 PRI/ RSVD SR11 SR11 L PR2 REV0 PR1 AMAP MADC/ RSVD SR9 SR9 CC5 PR0 LDAC SDAC Mute POP BYP RSRVD D15 RSRVD Mute Mute Mute Mute Mute Mute Mute Mute Mute Mute Mute Reserved Reserved Reserved Reserved Reserved Reserved Reserved 3D GL3 Reserved GL4 GL4 GL4 GL4 GL4 GL3 GL3 GL3 GL3 GL3 X X F7 F6 D14 SE4 RSRVD RSRVD D13 SE3 ML5 HPL5 D12 SE2 ML4 HPL4 D11 SE1 ML3 HPL3 D10 SE0 ML2 HPL2 Reserved F5 F F3 F2 F1 D9 ID9 ML1 HPL1 D8 ID8 ML0 HPL0 D7 ID7 D6 ID6 D5 ID5 MR5 HPR5 MM5 F0 D4 ID4 MR4 HPR4 MM4 PV3 GN4 boosten RSRVD GL1 GL1 GL1 GL1 GL1 SL1 GL1 MIX Reserved Reserved Reserved CDAC DSA1 DSA0 GL0 GL0 GL0 GL0 GL0 SL0 GL0 MS LPBK Reserved Reserved Reserved Reserved Reserved Reserved Reserved GR3 Reserved DP3 PG3 REF RSVD VRM/ RSVD SR3 SR3 PRE DP2 PG2 ANL SPDIF Reserved PG1 DAC DRA DRA/ RSVD SR1 SR1 #PCM/ AUDIO PG0 ADC VRA GN4 GR4 GR4 GR4 GR4 GR4 D3 ID3 MR3 HPR3 MM3 PV2 GN3 GN3 GR3 GR3 GR3 GR3 GR3 D2 ID2 MR2 HPR2 MM2 PV1 GN2 GN2 GR2 GR2 GR2 GR2 GR2 SR2 GR2 D1 ID1 MR1 HPR1 MM1 PV0 GN1 GN1 GR1 GR1 GR1 GR1 GR1 SR1 GR1 D0 ID0 MR0 HPR0 MM0 Default 6A90h 8000h 8000h 8000h
Reserved Reserved
RSRVD 0000h GN0 GN0 GR0 GR0 GR0 GR0 GR0 SR0 GR0 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 0000h 000Fh 0A05h
Reserved Reserved GL2 GL2 GL2 GL2 GL2 SL2 GL2
Reserved PRK/ RSVD SR13 SR13 PRJ/ RSVD SR12 SR12
2Ah 2Ch 32h 3Ah 3Eh 4Ch 4Eh 50h 52h 54h
VCFG SR15 SR15 V
SPCV SR10 SR10 CC6
LDAC/ SDAC/ CDAC/ RSVD RSVD RSVD SPSA1 SPSA0 SR8 SR8 CC4 PRA SR7 SR7 CC3 SR6 SR6 CC2 SR5 SR5 CC1 SR4 SR4 CC0 Reserved
SPDIF SR2 SR2 COPY
VRA SR0 SR0 PRO GPIO
0400h* BB80h BB80h 2000h 0100h
SPSR1 SPSR2 Reserved
Reserved Reserved Reserved Reserved Reserved
GC1 GC0 (GPIO1) (GPIO0) 0300h GP1 GP0 FFFFh (GPIO1) (GPIO0) GS1 GS0 0000h (GPIO1) (GPIO0) GW1 GW0 (GPIO1) (GPIO0) 0000h GI1 GI0 0000h (GPIO1) (GPIO0) RV7 RV6 RV5 RV4 RV3 RV2 RV1 RV0 12xxh
60h CODEC Class/ Page Rev 01h 62h 62h Page 01h 64h 64h Page 01h 66h 66h Page 01h 68h Function Select PCI SID PI15 PCI SVID PVI15
CL1
CL0
VENDOR Reserved PVI14 PVI13 PVI12 PVI11 PVI10 PVI9 PVI8 PVI7 PVI6 PVI5 PVI4 PVI3 PVI2 PVI1 PVI0 FFFFh
VENDOR Reserved PI14 PI13 PI12 PI11 PI10 PI9 PI8 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 FFFFh
VENDOR Reserved Reserved VENDOR Reserved FC3 FC2 FC1 FC0 T/R 0000h
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
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STAC9752A/9753A
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
Reg # 68h Page 01h 6Ah 6Ah Page 01h 6Ch 6Ch Page 01h 6Eh 6Eh Page 01h 70h 72h 74h 76h
Name Function Information Digital Audio Control Sense Details Revision Code
D15 G4
D14 G3
D13 G2
D12 G1
D11 G0
D10 INV
D9 DL4
D8 DL3
D7 DL2
D6 DL1
D5 DL0
D4 IV
D3
D2 Reserved
D1
D0 FIP
Default xxxxh
Reserved ST2 ST1 ST0 S4 S3 S2 S1 S0 xxxx Reserved AC97 ALL MIX MUTE ADC FIX slot1 DISBLE OR1 OR0 SR5 SR4 SR3
SPOR SR2
DO1 SR1
RSVD SR0
0000h NA xxxxh
Analog Special
Reserved
Reserved
ADC slot0
RSVD
MIC GAIN VALUE
SPLY OVR EN
SPLY OVR VAL
1000h
Reserved VENDOR Reserved Analog Current Adjust EAPD Access Regsiter 78 Enable Universal JackTM Select Reserved Vendor ID1 Vendor ID2 9752 1 0 0 1 0 1 0 1 0 0 0 1 1 1 HP Sel LO Sel RSVD LI Sel MIC Sel EAPD Reserved Reserved EAPD_ OEN EN15:0 STMIC MS DAC SEL PWDN HP3dB BYHP DAC BYLO ADC HPF BYP 0 0 INT APOP Reserved Reserved INTDIS GPIO ACC GPIO SLT12 0000h 0000h 0800h 0000h
78h 7Ah 7Ch 7Eh
RSVD
RSVD
0000h 0000h
VENDOR Reserved 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1
8384 h 7652h
*depends upon chip ID
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
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STAC9752A/9753A
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STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
16. REVISION HISTORY
Revision 0.9 Date Inital Release Corrected Note 4 in performance characteristics, was missing the text "Ratio of Full Scale signal toTHD+N output with -3dB signal, measured "A weighted" over a". Complete note now reads "Ratio of Full Scale signal toTHD+N output with -3dB signal, measured "A weighted" over a 20 Hz to a 20 KHz bandwidth. 48 KHz Sample Frequency". Added updated 32-pin package drawing Added more 32-pin package information - Recommended PCB Layout. Added pull-up/ pull-down column to pin characteristics table. Corrected pin 40 LQFP 48-pin package error . It is not a Headphone_Comm, but is a no connect. Removed "Preliminary" from the Datasheet. Updated 48-pin and 32-pin package drawings. Updated reflow profile information. Revised reflow profile information. Updated Logo. Updated 32-pin package drawing. 30 October 2006 Dec 2006 Release in IDT format. corrected orderable part numbers and added note. Description of Change
0.91
0.92 0.93 0.94 1.0 1.1 1.2 1.3 1.4 1.5
IDTTM AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
105
STAC9752A/9753A
V 1.5 1206
STAC9752A/9753A AC'97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
Innovate with IDT audio for high fidelity. Contact:
www.IDT.com
For Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
For Tech Support
HA.CM@idt.com
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.)
Europe
IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339
(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners.

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